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Hysteresis-Free Carbon Nanotube Field-Effect Transistors Rebecca S. Park, Gage Hills, Joon Sohn, Subhasish Mitra, Max M. Shulaker, and H.-S. Philip Wong ACS Nano, Just Accepted Manuscript • Publication Date (Web): 02 May 2017 Downloaded from http://pubs.acs.org on May 2, 2017

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Hysteresis-Free Carbon Nanotube Field-Effect Transistors Rebecca S. Park*,†, Gage Hills†, Joon Sohn†, Subhasish Mitra†,‡, Max M. Shulaker§, H.-S. Philip. Wong†

†

Department of Electrical Engineering, Stanford University, Stanford, CA, USA ‡

§

Department of Computer Science, Stanford University, Stanford, CA, USA

Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, USA

Keyword Carbon nanotube field-effect transistor, hysteresis, traps, subthreshold swing, threshold voltage variations, beyond-Si

Abstract

While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As

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hysteresis is caused by traps surrounding the CNTs, previous works have shown that clean interfaces that are free of traps are important to minimize hysteresis. Our previous findings on the sources and physics of hysteresis in CNFETs enabled us to understand the influence of gate dielectric scaling on hysteresis. To begin with, we validate through simulations how scaling the gate dielectric thickness results in greater-than-expected benefits in reducing hysteresis. Leveraging this insight, we experimentally demonstrate reducing hysteresis to less than 0.5% of the gate-source voltage sweep range using a very large-scale integration compatible and solidstate technology, simply by fabricating CNFETs with a thin effective oxide thickness of 1.6 nm. However, even with negligible hysteresis, large subthreshold swing is still observed in the CNFETs with multiple CNTs per transistor. We show that the cause of large subthreshold swing is due to threshold voltage variation between individual CNTs. We also show that the source of this threshold voltage variation is not explained solely by variations in CNT diameters (as is often ascribed). Rather, other factors unrelated to the CNTs themselves (i.e., process variations, random fixed charges at interfaces) are a significant factor in CNT threshold voltage variations, and thus need to be further improved.

As scaling of silicon technology is becoming increasingly challenging, intense research on nanomaterials to complement or replace silicon has become essential.1,2 Among them, carbon nanotube (CNT) is a potential channel material for future high-performance scaled technology due to its one-dimensional (1D) structure and ultra-thin body which minimizes short channel effects while simultaneously achieving high carrier transport.3 Additionally, among emerging transistors, complete digital systems fabricated using carbon nanotube field-effect transistors (CNFETs) (Figure 1a) have been experimentally demonstrated.4,5


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Despite this promise, large hysteresis (Figure 1b) remains a major obstacle facing energyefficient CNFET digital logic as hysteresis degrades system-level performance (e.g., by reducing noise margin and increasing delay variations).6 Due to a CNT’s 1D geometry, the physics behind hysteresis is different from a conventional two-dimensional (2D) semiconductor device. Our previous work studying the sources of hysteresis in CNFETs elucidated that CNFET hysteresis is dominated by two sources (Figure 1c): interface traps (traps at the interface of the CNT and the dielectric) and surface traps (traps along the surface of the dielectric, not directly in contact with the CNTs).6 Interface traps also exist in conventional semiconductor devices, which are at the interface of the semiconductor and the dielectric. However, the presence of surface traps in CNFETs becomes an additional source of hysteresis. Even for high CNT density (e.g., 100 CNTs/µm), the surface region is large (e.g., CNT to CNT spacing is 10 nm) compared to the interface region (e.g., CNT diameter is approximately 1 nm). Therefore, hysteresis in CNFETs occurs as both the charged interface traps and surface traps affect the CNT by interfering with the applied gate bias.


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Figure 1. Sources of hysteresis in CNFETs. (a) A typical CNFET structure with a highly-doped silicon substrate as a gate, thermally grown SiO2 as the gate dielectric, and CNTs as the channel material between the source and drain contacts. Inset shows SEM image of CNTs across source and drain. (b) IS-VGS curve of a CNFET such as (a). Large hysteresis is observed in this device structure between the positive sweep and the negative sweep. (c) Illustration of the progression of the charge trapping process at the interface traps and surface traps which are the dominant sources of hysteresis.6,7 Previous attempts to eliminate hysteresis implemented fabrication methods such as suspending the CNT above the substrate,8 passivating the CNT with PMMA or other polymers,9–11 or surrounding the CNT with oxides to form gate-all-around geometries.12 However, there are challenges for these techniques: suspending the CNTs increases the effective oxide thickness (EOT) by using ambient (air or vacuum) as the gate dielectric, the passivation materials are not solid-state especially at elevated temperatures (>100 °C),13 and the fabrication methods to implement gate-all-around structures can be challenging for very large-scale integration (VLSI). For instance, processes used to remove metallic CNTs14,15 are difficult to apply when the CNTs are suspended or wrapped in a dielectric. Despite the challenges, these studies have proven that by reducing the density of traps (i.e., making the interfaces as clean as possible), hysteresis in CNFETs is minimized. Additionally, although negligible hysteresis ranging from 2.5% to 5.5% of the gate-source voltage (VGS) sweep range has been reported using VLSI-compatible CNFET structures,16,17 the focus of the reports was not on illustrating a methodology for reducing hysteresis; the mechanism was not well understood as the authors only briefly explained and attributed reduced hysteresis to fewer charge traps.18,19 Recently, a method of neutralizing the traps by stacking two layers of dielectric (20-nm ALD deposited Al2O3 + 40-nm magnetron


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sputtered SiO2) has been implemented to reduce hysteresis.20 However, the device behavior needs to be further studied with scaling down the total gate dielectric thickness. Here, we present a facile approach to overcoming hysteresis to less than 0.5% of the VGS sweep range: rather than to eliminate traps, we aim to reduce the effect that traps have on the CNTs. Using the physics-based model from our previous work,6 we illustrate the interaction between the metal gate, the traps, and the CNT using COMSOL Multiphysics®21 simulation (Figure S1). We validate through the simulation results that the effect of traps onto the CNTs can be reduced simply by scaling the EOT – which is a requirement for high-performance, deeplyscaled CNFET digital logic regardless. As the electrostatic distance between the metal gate and the CNTs decreases (e.g., by decreasing the EOT by either decreasing the physical oxide thickness or increasing the dielectric constant of the oxide), the effect of the surrounding traps become negligible due to electrostatic shielding from the gate. Thus, as the ratio of the electrostatic CNT-metal gate distance to CNT-trap distance decreases, so too does the electrostatic impact of the trap on the CNT. Consequently, reducing the effect of traps (i.e., scaling down the EOT) results in better electrostatic control and substantial decrease of hysteresis. Hence, the key to overcoming hysteresis is to realize CNFETs with the smallest EOT. Additionally, other methods (i.e., reducing the density of traps, neutralizing the traps) along with reducing the effect of traps can be combined to further minimize hysteresis. RESULTS AND DISCUSSION The CNFET fabrication process (Figure S2 and S3) is as follows: chemical vapor deposition (CVD)-grown aligned CNTs on quartz (approximately 3 CNTs/µm) are transferred onto the SiO2/Si substrate (thermally grown, 73 nm-SiO2 on a highly doped Si substrate) using a lowtemperature layer-transfer technique.22 Source and drain electrodes (1 nm Ti adhesion layer,


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followed by Pt) with channel lengths of 1 µm are patterned using standard optical photolithography and deposited using an e-beam evaporator. The width of the channel is defined by covering the channel area with photoresist, and etching the CNTs in undesired regions with O2 plasma. Since the transferred CNTs include both metallic and semiconducting channels, VLSI-compatible metallic CNT removal (VMR)14 is performed to selectively remove the metallic CNTs. Various thicknesses (5, 10, 20, and 30 nm) of TiO2 (Figure S4) are deposited as the gate dielectric using an e-beam evaporator with a slow (~ 1 Å/s) deposition rate. The gate electrode (1 nm Ti/40 nm Pt) is patterned using photolithography. Lastly, the TiO2 is etched in 2% HF so that the source and drain electrodes are exposed. The final CNFET structure is shown in Figure 2.

Figure 2. CNFET structure. (a) An SEM image of a top view of a fabricated top-gated CNFET. (b) A cross-sectional schematic. (c) A TEM image showing the 5-nm deposited TiO2. The amorphous structure of TiO2, along with the fabrication process (steps 3 and 4 in Figure S3), ensures minimal leakage current through the gate electrode.


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The reason for using a top-gated structure is to minimize variations induced by oxygen or water molecules in air onto the CNTs, which are known factors that cause hysteresis.9 The gate dielectric thickness is varied to study the effect of the dielectric thickness on hysteresis. It is important to note that the interface and surface trap densities, which are the dominant sources of hysteresis, are kept constant as we only change the dielectric thickness. Therefore, the quality of the interfaces (the density of traps at the interface surrounding the CNTs) is not impacted. TiO2 is chosen as the gate dielectric due to its high dielectric constant23–25 as shown in the inset of Figure 3a. To determine the dielectric constant, metal-insulator-metal (MIM) structures are fabricated. The capacitances of the 10, 20, and 30 nm TiO2 are measured, and that of the 5 nm TiO2 (which is equivalent to 1.6 nm EOT) is extracted by fitting a linear curve. The decrease in the measured dielectric constant as the TiO2 layer becomes thinner could be due to the degradation of film quality as the thickness is decreased, or imperfections at the interface of the dielectric and the electrodes.26,27 Figure 3a plots the amount of hysteresis averaged over 30 CNFETs for each TiO2 thickness. Figure S5 shows the hysteresis histograms for each TiO2 thickness. The amount of hysteresis is calculated as the difference between the gate voltages where the current reaches the average of the maximum and the minimum current of the forward and backward sweep. VDS is set as -0.5 V because for future advanced logic technologies, it is expected that the power supply will need to be scaled down to 0.5 V.28,29 The VGS sweep ranges are scaled according to the measured dielectric constants as shown in the inset of Figure 3a, normalizing for differences in EOT. As an example, the normalized IS – VGS curves for the 5 nm and 30 nm TiO2 thicknesses are plotted in Figure 3b. Better electrostatic control of the CNTs by the metal gate, and less coupling between the gate and the traps is observed for smaller EOT, resulting in reduced hysteresis. On average, hysteresis of less than 0.5% (7 mV) of the VGS


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sweep range (-0.5 V to 1 V) is achieved for CNFETs with 5 nm TiO2 as the gate dielectric (Figure 3a).

Figure 3. Hysteresis reduction in CNFETs. (a) Amount of hysteresis averaged over 30 devices for each TiO2 thickness for the scaled VGS sweep range based on the EOT. VGS sweep ranges are from -0.5 V to 1 V (5 nm), from -0.85 V to 1.7 V (10 nm), from -1.25 V to 2.5 V (20 nm), and from -1.5 V to 3 V (30 nm). Error bar is one sigma. Inset shows the measured dielectric constants (by capacitance measurements) for TiO2 of 10, 20, and 30 nm using the MIM and the extracted dielectric constant for TiO2 of 5 nm. (b) Example of normalized IS – VGS curves from part (a) showing forward (curve shifted to the left) and backward (curve shifted to the right) sweeps for 5 nm and 30 nm TiO2 thicknesses. (c) Amount of hysteresis averaged over 30 devices for each TiO2 thickness for the same VGS sweep range (-1 V to 1 V). Error bar is one sigma. (d) Example of normalized IS – VGS curves from part (c) showing forward (curve shifted to the left) and backward (curve shifted to the right) sweeps for 5 nm and 30 nm TiO2 thicknesses. All


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measurements are done in ambient air with VDS is set to -0.5 V. (channel length = 1 µm, channel width = 50 µm, gate length = 1.2 µm) In addition, since the amount of hysteresis is affected by the VGS sweep range used in the measurement (e.g., for a given device, smaller VGS sweep range reduces the observed hysteresis),30 the IS – VGS curves are also compared with a fixed VGS sweep range (-1 V to 1 V) to confirm the effect of the gate dielectric thickness only. As shown in Figure 3c and 3d, a decrease in hysteresis is also observed with thinner gate dielectric thickness, even when the devices are measured using the same VGS sweep range which results in larger gate electric fields for the thinner EOT devices. Therefore, as we scale down the dielectric thickness and the power supply voltage concomitantly, not only is the hysteresis reduced due to a smaller VGS sweep range, but also additional benefits come from the decrease of the effect of traps, which leads to greater-than-expected reduction of hysteresis. Figure 4a shows the IS – VGS curves of 65 single-CNT CNFETs (CNFETs with only one CNT as the channel) with 5nm TiO2 as the gate dielectric, where negligible hysteresis is observed for all devices. The gate leakage current is in the pico-amp regime (Figure 4b). The single-CNT CNFETs exhibit an average subthreshold swing (SS) of 77.6 mV/decade (Figure 4c), close to the ideal SS for room temperature FETs.


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Figure 4. Single-CNT CNFETs. (a) IS – VGS curves with negligible hysteresis measured from 65 single-CNT CNFETs with 5 nm TiO2 as the gate dielectric and (b) their gate leakage currents (which are negligible compared to the source current). 0.5 V of VGS sweep range and -0.5 V of VDS are applied. All measurements are done in ambient air. (channel length = 1 µm, gate length = 1.2 µm) (c) SS for the 65 single-CNT CNFETs. The mean value of the SS distribution is 77.6 mV/decade with a standard deviation of 10.2 mV/decade. (d) VT for the 65 single-CNT CNFETs. The mean value of the VT distribution is 102.4 mV with a standard deviation of 125.6 mV. (e) Table summarizes experimentally extracted values.


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However, for high-performance CNFETs, several CNTs in parallel are used as the channel of the CNFET to achieve sufficient drive current (e.g., 100-200 CNTs/µm).31 As can be seen in Figure 4d, there is significant threshold voltage (VT) variation across single-CNT CNFETs. The VT for individual CNFETs is extracted from the single-CNT CNFETs measured in Figure 4a. (According to International Roadmap for Semiconductors,32 the off-state current is fixed at 100 nA/µm for high-performance logic. Since our target density is 100-200 CNTs/µm,31 VT value is determined at VGS where IS(VGS) = IOFF = 1 nA for the single-CNT CNFETs.) This VT variation can degrade SS for multiple-CNT CNFETs since each CNT (controlled by the gate) can now have its steepest SS at a different VGS. This effect is shown experimentally in Figure 5a: the SS increases as the number of CNTs in the CNFET increases (higher on-current corresponds to more parallel CNTs in the channel). Multiple-CNT CNFETs with different number of CNTs as the channel are fabricated by defining various channel widths. Larger channel width corresponds to more CNTs in the device. The number of CNTs is estimated by taking the IS value at a fixed overdrive voltage (VOV) and dividing it by the average IS value at the VOV from the single-CNT CNFET analysis in Figure 4a. In Figure 5b, we experimentally extract the SS for the various number of CNTs per device and compare them with the SS obtained from 10,000 iterations of Monte Carlo simulation to predict the SS using the maximum, average, and minimum SS values and the standard deviation of VT as summarized in Figure 4e. The well-matched trends between the experiment and the simulation corroborates the hypothesis that the SS degradation can be attributed to the VT variation of CNFETs as the number of CNTs in the CNFET channel increases. It has been predicted by simulation that VT variation will converge and become insignificant as the number of CNTs per transistor increases due to averaging effects.33,34 Figure 5c confirms the prediction. However, it is important to note that while increasing the number of


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CNTs per transistor decreases VT variation, it can degrade SS, and thus must be carefully considered for VLSI systems.

Figure 5. Multiple-CNT CNFETs. (a) IS – VGS curves measured from 254 CNFETs with 5 nm TiO2 as the gate dielectric with different number of CNTs per device. (channel length = 1 µm, gate length = 1.2 µm) (b) SS analysis: experimental and simulation results demonstrating increase in SS as the number of CNTs is increased. The parameters in the legend are taken from Figure 4e. (c) VT analysis: VT variation is reduced as the number of CNTs is increased. Note that σ(VT) in the legend of (b) is from the analysis of single-CNT CNFETs in Figure 4e, and σ(VT) on the y-axis of (c) is from the analysis of (a). Therefore, to realize CNFETs with both reduced hysteresis and steep SS, VT variations must also be controlled. VT variation in CNFETs is known to be caused by multiple factors, ranging from CNT diameter variations, random fixed charges between oxides, processing variations, etc.33–35 To understand the sources of VT variations, we test a common explanation: that the CNT diameter distributions cause the VT variations.35 To test the impact of CNT diameter variations on SS, the diameters of individual CNTs were measured by scanning the CNTs using atomic force microscopy (AFM). The distribution across 126 CNTs (Figure 6a) has a mean value of 1.4 nm and a standard deviation of 0.34 nm (we remove all CNTs with a diameter > 2 nm, since we


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only test semiconducting CNTs and CNTs with diameters > 2 nm are metallic). As the bandgap of the CNT is dependent on the CNT diameter (dCNT) as ~

,

the VT is also dependent on dCNT. Therefore, the standard deviation of VT due to the dCNT distribution is defined as ,

,

where 2.7 (nearest neighbor overlap integral) and 1.42 Å (carbon-carbon bond length).33 Using the above equation, the standard deviation of VT due to dCNT variations is 98.9 mV.

Figure 6 (a) CNT diameter distribution with a mean value of 1.4 nm and standard deviation of 0.34 nm. Inset shows an example of the scanned CNTs using AFM. (b) Simulation comparing the increase in SS due to the measured (total) VT variation and the dCNT-induced VT variation.


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Monte Carlo simulations are performed to study the effect of CNT diameter variation on SS degradation as the number of CNTs increases in the CNFETs. Figure 6b compares the simulated SS due to the measured (total) VT variations in CNFETs (which is the same simulated curve from Figure 5b) and the simulated SS due to VT variations only from the dCNT distribution. Although dCNT distribution largely contributes to SS degradation, it alone does not account for the experimental SS degradation. Previous studies show that VT variations from diameter distributions becomes negligible as the channel length is scaled down (since random fluctuation of fixed charges between oxides – in our case, TiO2/SiO2 interface – becomes the major source of VT variations due to less averaging effects from random variations).33,34 Therefore, non-ideal aspects of device processing, such as random fixed charges on the oxide surface, must be further controlled and improved. CONCLUSION We have successfully demonstrated a VLSI-compatible and solid-state method to fabricate CNFETs with hysteresis less than 0.5% of the gate-source voltage (VGS) sweep range, and that hysteresis is naturally overcome by scaling the gate dielectric thickness in CNFETs, even without optimizing the interfaces to minimize traps. Despite reducing hysteresis, large SS remains a challenge and is attributed to single-CNT VT variations. The VT variations cannot be entirely attributed to dCNT variations, but rather additional non-ideal aspects of device processing contribute a non-negligible portion. Therefore, the next major challenge is to control single-CNT VT to achieve steep SS for multiple-CNT CNFETs, which will require further work improving the interface qualities. METHODS


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CNFET Structure. As shown in steps 3 and 4 of Figure S3, the source and drain metal contacts are deposited in two separate evaporations (“thin” layer + “thick” layer). As shown in Figure S6, the two separate evaporations are required to prevent shorts between metal contacts for CNFETs with thin (5 nm) dielectrics and when the gate overlaps the source and drain metal contacts. Minimal overlap between the gate and the source (or drain) will further minimize leakage current. The overlap area on each side in our devices is 65 µm × 100 nm. TiO2 Material. Black-colored TiO2 pellets (item number: EVMTIO2314) were purchased from Kurt J. Lesker Company. TiO2 is deposited in Kurt J. Lesker Company’s PVD 75 e-beam evaporator system using conditions 7 kV for voltage and 20 mA for current. The deposition rate is 1 (± 0.3) Å/s.

ASSOCIATED CONTENT Supporting Information. The Supporting Information is available free of charge. Simulation showing effect of gate dielectric scaling; CNT growth process; CNFET fabrication process; XPS analysis of evaporated TiO2; Histograms of hysteresis data; Structure of source and drain metal contacts (PDF)

AUTHOR INFORMATION Corresponding Author * E-mail: [email protected].


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Author Contributions The manuscript was written through contributions of all authors. All authors have given approval to the final version of the manuscript. Notes The authors declare no competing financial interest. ACKNOWLEDGMENT We acknowledge support in part by Systems on Nanoscale Information fabriCs (SONIC), one of the six SRC STARnet Centers, sponsored by MARCO and DARPA, the National Science Foundation (CISE: CNS-1059020, CCF-0726791, CCF-0702343, and ECCS-0954423), member companies of the Stanford SystemX Alliance, SRCEA/Intel fellowship for R.S.P., and Doctorate Program Scholarship from Kwanjeong Educational Foundation for J.S. We also extend our gratitude to P. Ramesh (Stanford) for fruitful discussions.

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