4745
2009, 113, 4745–4747 Published on Web 03/03/2009
Illumination-Enhanced Hysteresis of Transistors Based on Carbon Nanotube Networks Chun Wei Lee,† Xiaochen Dong,† Seok Hong Goh,† Junling Wang,† Jun Wei,‡ and Lain-Jong Li*,† School of Materials Science and Engineering, Nanyang Technological UniVersity, 50 Nanyang AVenue, Singapore, 639798, Singapore Institute of Manufacturing Technology, 71 Nanyang DriVe, Singapore 638075 ReceiVed: December 13, 2008; ReVised Manuscript ReceiVed: January 23, 2009
The hysteresis in single-walled carbon nanotube (SWNT) transistors comprising Si backgate (SiO2 on doped Si) is normally attributed to either carrier injections from SWNTs to their surroundings or the presence of charge traps at a Si-SiO2 interface. We show that the hysteresis in SWNT transistors with a nearly trap-free Si backgate is thermally activated (activation energy Ea ∼ 129-184 meV) in a dark ambient condition, and it is attributed to hole trappings at the SiO2 surfaces proximate to SWNTs. Photon-illumination on the SWNT transistor devices with thin SiO2 dielectrics (80 nm) results in the ON-current increase due to the effective gating from the photovoltage generated at the Si-SiO2 interface. The light-induced simultaneous enhancement of ON-current and hysteresis suggests that the illumination-enhanced hysteresis is due to the photovoltageactivated hole trapping process on SiO2 surfaces. Hysteresis between forward and reverse gate bias sweeps is usually observed in field-effect transistors (FETs) based on single-walled carbon nanotubes (SWNTs). This raises concerns of using SWNT FETs for electronic integrated circuits. These FETs are normally with SWNTs lying on a Si backgate (SiO2 on doped Si). Therefore, the hysteresis is reasonably related to the mobile charges or traps in the gate structures.1-3 Other studies have suggested that the charges injected from SWNTs into the surrounding dielectrics contribute to the hysteresis.4-6 The surface bound-water layer has also been suggested to act as a charge trap or mediator.7 However, several recent studies have raised questions on the role of water layers.8,9 Instead, the hysteresis has been suggested to involve surface silanol groups as the major sources of charge screening.9 Although the origin of the hysteresis in SWNT FETs is still under debate, the charge exchange between SWNTs and their surroundings is believed to be the root cause. In this contribution, we study the hysteretic behaviors of transfer characteristics (drain current Id vs gate voltage Vg) for SWNT FETs lying on a nearly trap-free backgate substrate (80 nm SiO2 on Si) to exclude the hysteresis contributing from the underlying backgate. The hysteresis observed in the dark is thermally activated and with the extracted activation energy (Ea) ∼ 129-184 meV, indicating that the charge trapping/detrapping process is involved. We attribute the corresponding negative shift of threshold voltage (Vth) to the electric field (negative Vg)driven hole trapping at SiO2 surfaces proximate to SWNTs, as suggested by Lee et al.9 Interestingly, the photon illumination on the SWNT transistors results in the simultaneous enhancement of ON-current and hysteresis. These results suggest that the illumination-enhanced hysteresis is due to the photovoltageactivated hole-trapping process on SiO2 surfaces. Moreover, the * E-mail:
[email protected]. † Nanyang Technological University. ‡ Singapore Institute of Manufacturing Technology.
10.1021/jp811006r CCC: $40.75
Figure 1. Typical transfer curves (Id vs gate voltage Vg) of SWNT FETs with and without light exposure (632 nm). The hysteresis is defined as the difference between the forward threshold voltages (Vthf) and reverse threshold voltage (Vthr). The scheme illustrates the device structure of a SWNT FET.
pronounced changes in electrical characteristics upon light exposure postulate a sensitive strategy for light detection. In our experiments, the typical SWNT FETs were fabricated in a bottom contact device geometry, where a p-doped silicon wafer (boron-doped with resistivity ∼1-5 Ω cm) with an 80nm-thick thermal SiO2 layer was used as the backgate, and Au electrodes spaced by a channel length of 100 µm were patterned on top of it (scheme of Figure 1). SWNT and multiwalled carbon nanotube (MWNT) electrodes were also used to replace the commonly used Au electrodes for transistor fabrications. The fabrication of SWNT or MWNT electrodes was reported elsewhere.10,11 Arc-discharge-produced SWNTs were then dropcast to the networks in channel areas. The arc-dischargedproduced SWNTs used for device fabrication were semiconductorenriched through the density gradient ultracentrifugation proposed by Arnold et al.12 In brief, arc-discharged-produced SWNTs (diameter from 0.8 to 1.4 nm) were dispersed in an aqueous 2009 American Chemical Society
4746 J. Phys. Chem. C, Vol. 113, No. 12, 2009 solution with 1:4 (weight ratio) of sodium dodecyl sulfate and sodium cholate hydrate. After density-gradient centrifugation, the semiconductor-enriched portion of the solution was used for device preparation.13 The transistors obtained show a typical p-type behavior, and the representative mobility is around 1.5 cm2/V-s with a high on-off ratio around 104. Electrical measurements were carried out using a Kiethley semiconductor characterization system (model 4200-SCS) or HP precision LCR meter (model 4284A) at desired temperatures in an ambient environment. A desired band of light was selected by using band-pass filters ((10 nm) from a broadband light source (250 W of W-lamp), and the light intensity was attenuated with neutral density filters. The measurements of capacitancevoltage (C-V) loops were carried out for the Au electrode/ SiO2-Si structure at 100 Hz to characterize the traps existing in our Si backgate substrates. No significant hysteresis is observed between forward and reverse C-V curves in both cases, with and without light exposure. In addition, the threshold voltages for all C-V curves are around 0 V (data not shown). These suggest that the Si-SiO2 interface is nearly trap-free, and the light illumination does not induce trapped charges at Si-SiO2 interface. Similarly, the observation is also valid for the FETs using SWNTs or MWNTs as electrodes on the same Si backgate substrate. It has been reported that the conductivity change in SWNT FETs upon visible light exposure is dominated by the photovoltage, an effectively negative Vg generated at the Si backgate, resulting from the accumulation of photon-generated charges at the SiO2-Si interface.14,15 It is also suggested that the direct excitation through SWNTs does not significantly contribute to the photoconductivity to SWNT EFTs. Reference 16 has revealed that at a positive Vg, where the Si band bending is not suitable for generating photovoltage, photo illumination on SWNT network FETs does not cause the increase in Id. When Vg is negative, the photon illumination causes the increase in the ON-current only for the SWNT-FETs lying on a backgate with thin SiO2 (80 nm), but not obvious for those devices with 300 nm SiO2. Figure 1 shows the typical transfer curves for a SWNT FET on a Si backgate (80 nm of SiO2) using SWNTs as electrodes with and without light exposure, where the light (4.69 nW/mm2 at 632 nm with a spot size 100 µm) was focused onto the channel area through optical objectives. A significant increase in Id is observed with photon illumination at Vg < 0, attributed to the effect of photovoltage.14,16 Interestingly, the hysteresis for the SWNT FETs lying on the backgate with 80 nm of SiO2 under light illumination is significantly larger as compared to that measured in a dark, ambient condition. The forward threshold voltages (Vthf), threshold voltage (Vth) extracted from forward sweeps (positve to negative Vg), measured in the dark were close to those measured under light exposure. By contrast, the reverse Vth (Vthr) is largely shifted to a more negative value with photon illumination, as compared to the Vthr in the dark. Twenty devices have been characterized to understand the effect of the light illumination on SWNT FET, and all devices show consistent results. The FETs fabricated on Au or MWNT electrodes also exhibit consistent behaviors. In addition, we notice that no hysteresis enhancement or Id increase is observed for the SWNT FETs lying on a backgate with 300 nm of SiO2, indicating that it is unlikely the surfactants are contributing to the photoenhanced hysteresis. To describe the evolution in transfer curves, we define the hysteresis as a threshold voltage difference (∆Vth), the difference between Vthf and Vthr, as indicated in Figure 1. It is observed that the ∆Vth for this device with light illumination is ∼23 V,
Letters
Figure 2. (a) Typical transfer curves of SWNT FETs at various temperatures (25, 60, and 90 °C) in a dark and ambient condition. (b) The Arrhenius plot of ∆Vth for SWNT FETs under dark and room light illumination over the temperature range from 18 to 100 °C.
higher than the ∆Vth in the dark (∼7 V). First, we examine the hysteresis for SWNT FET in the dark. It has been widely quoted that the hysteresis of SWNT FET is due to the charges injected from SWNTs into the surrounding dielectrics.4-6,9 To reveal the causes of the observed hysteresis for our SWNT FETs, temperature dependence of the hysteretic behaviors is studied in ambient. Figure 2a shows typical transfer curves at various temperatures for a selected device. By using a nearly trap-free Si backgate substrate according to C-V loop measurement, the observed hysteresis is not likely due to the traps in Si backgate. Thus, the negative shift of Vthr with increasing temperature observed in Figure 2a is attributed to the electric field (negative Vg)-driven hole trapping at SiO2 surfaces proximate to SWNTs.9 Figure 2b shows the Arrhenius plot of ∆Vth for five SWNT FETs over the temperature range from 18 to 100 °C. The results for four devices (D1-D4) in the dark and one device (D1) under room light exposure are demonstrated. The ∆Vth measured in a dark and ambient condition is thermally activated and exhibits an Ea of ∼129-184 meV when the temperature is
