NANO LETTERS
Improved Subthreshold Slope in an InAs Nanowire Heterostructure Field-Effect Transistor
2006 Vol. 6, No. 9 1842-1846
Erik Lind,† Ann I. Persson, Lars Samuelson, and Lars-Erik Wernersson* Solid State Physics/Nanometer Structure Consortium, Lund UniVersity, Box 118, S-221 00 Lund, Sweden Received December 14, 2005; Revised Manuscript Received July 13, 2006
ABSTRACT An n-type InAs/InAsP heterostructure nanowire field-effect transistor has been fabricated and compared with a homogeneous InAs field-effect transistor. For the same device geometry, by introduction of the heterostructure, the threshold voltage is shifted 4 V, the maximum current on-off ratio is enhanced by a factor of 10 000, and the subthreshold swing is lowered by a factor 4 compared to the homogeneous transistor. At the same time, the drive current remains constant for a fixed gate overdrive. A single nanowire heterostructure transistor has a transconductance of 5 µA/V at a low source−drain voltage of 0.3 V. For the homogeneous InAs transistor, we deduced a high electron mobility of 1500 cm2/Vs.
Electronic devices based on narrow-band-gap materials, such as InAs, are promising candidates for future high-speed, lowpower electronic devices. The narrow band gap (Eg ) 0.35 eV for InAs) implies a small effective electron mass, which yields a very high mobility. For undoped InAs, the mobility can be as high as µn ) 33 000 cm2/Vs, compared with µn ) 1500 cm2/Vs for Si. Furthermore, the large intravalley separation energy of InAs allows for a high saturated velocity, Vsat ) 4.0 × 107 cm/s. The narrow band gap, however, also has some negative issues for transistor performance, such as large leakage currents due to the small achievable barrier height and a low break down field strength related to impact ionization and Zener tunneling. Recently, there has been rapid progress in the growth and processing technology for nanowire structures, including atomically abrupt heterojunctions,1 wrap-gate field-effect transistors,2 pn junctions,3 and core-shell structures.4 For field-effect transistors (FETs), the wire-geometry provides an ample opportunity to form wrap-gate transistors, which effectively reduces short channel effects.5 Also, the efficient radial strain relaxation in the nanowire geometry makes it possible to form dislocation-free heterojunctions between materials with a large lattice mismatch,1 which allows for freedom in designing different heterostructure devices. In this letter, we demonstrate a backgated nanowire InAs/ InAsP heterojunction field-effect transistor, with a substantially improved subthreshold swing and current on-off ratio * Corresponding author. E-mail:
[email protected]. † Current Adress: Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106. 10.1021/nl052468b CCC: $33.50 Published on Web 08/16/2006
© 2006 American Chemical Society
compared with a homogeneous InAs back-gated nanowire FET. The design makes use of a heterostructure barrier between the source and drain region, which increases the gate control of drain current because the heterojunction energy barrier is independent of any applied source-drain bias. For a fixed nanowire radius, one can thus achieve a subthreshold slope closer to 60 m/decade by utilizing a heterostructure. Similarly, heterojunctions have been proposed previously to improve Si/SiGe p-MOSFETs currentvoltage (I-V) characteristics by decreasing drain-induced barrier-lowering (DIBL) effects.6,7 InAs nanowires were grown by chemical beam epitaxy (CBE) using 50 nm gold aerosols as seed particles on an InAs B substrate. The material sources used in the epitaxy were trimetylindium (TMIn), tertiarybutylarsine (TBAs), and tertiarybutylphosphine (TBP), and the growth temperature was 435 °C. The wire diameter was around 50 nm, verified by scanning transmission electron microscope (STEM) inspection. The total wire length was 6 µm, with a 150-nm-thick8 InAs0.7P0.39 segment placed roughly 1.5 µm away from the top of the wires. In Figure 1a, a STEM image of the barrier is shown, showing sharp interfaces between InAs and InAsP segment. The composition of the InAsP segment was further quantified using energy dispersive X-ray spectroscopy (EDX) in TEM, and the composition was determined to be InAs0.7(0.05P0.3(0.05. Unstrained InAs0.7P0.3 has a nominal barrier offset of about 160 meV to InAs,9 which should have a substantial effect on the off current, as described later.
Figure 1. STEM and SEM images of the nanowire transistor. (a) STEM image of the barrier region, showing the interfaces between InAs and InAsP. (b) SEM image of a nanowire device ready for measurement. The three terminals allow for independent measurement of a transistor with and without a barrier. The approximate position of the barrier has been marked red.
The InAs wires are nominally undoped, but have an estimated effective carrier concentration of around 1 × 1018 cm-3 with the carriers originating from carbon incorporation during the growth and from surface-induced states. After the growth, the wires were placed on a degenerately doped Si substrate with a 20-nm-thick SiO2 layer, and nonalloyed NiAu contacts were formed to the wires using electron-beam lithography and thermal metal evaporation.10 Three ohmic contacts were made to each wire, forming one source and two drain electrodes, as shown in Figure 1b. The Si substrate is used as the gate electrode. This four-terminal configuration allows for a direct comparison of a homogeneous InAs FET with an InAs/InAsP FET, without any deviations due to process related variations between different fabrication runs. Measurements were performed by grounding the source electrode, and simultaneously applying drain voltages to both drain electrodes, while independently measuring the different drain currents. The measurements were done in ambient atmosphere at room temperature, and without any illumination. Figure 2 shows the drain current as a function of drain bias for different gate voltages. A substantial improvement in the current control for the InAs/InAsP device is obtained, in particular for small Vds voltages, while the on-current remains similar to the pure InAs transistor. The drain current as a function of gate voltage at a fixed Vds ) 0.3 V, obtained at room temperature, is shown in Figure 3. The data in Figure 3 shows a presence of hysteresis effects in the devices. This is most likely due to traps in the SiO2, the SiO2/Si interface, and in the wire/SiO2 interface. However, we have measured several devices and in all cases the hysteresis effects are smaller than the differences between the two types of devices under comparison in this paper. The simultaneous measurement of the device characteristics further enables a fair comparison between the devices. This is enabled by the two drain contacts used. We note that the off current is readily suppressed in the heterostructure device, and a large increase in the maximum on-off current ratio is clearly obtained, approaching 3 × 104 between Vgs ) 2 V and Vgs ) -6 V, compared with 7.5 for similar gate values for the pure InAs transistor, Figure 3a. (For Vgs < -6 V, there is little change Nano Lett., Vol. 6, No. 9, 2006
Figure 2. I-V characteristics obtained at room temperature. The red curves correspond to the InAs FET, and the blue curves correspond to the InAs/InAsP FET. Vgs is changed in steps of 1 V, from Vgs ) -5 V up to Vgs ) 2 V.
in the current levels.) From the linear plot in Figure 3b, we note a shift of about 4 V in the threshold voltage, Vt, of the two devices, as determined from the downward sweep of the gate bias. This affects the determination of the drive current, which in Figure 2 seems lower for the heterostructure device, but actually remains constant for a fixed gate overdrive (Vgs - Vt ). Furthermore, the subthreshold swing improves from 3-4 V/decade to 900 mV/decade when the heterostructure is introduced. The still large swing value originates mainly from the nonideal device geometry with the wire lying on top of the gate, coupled to the fairly large nanowire diameter and high effective doping. A substantial improvement is expected for a device in a wrap-gate geometry, where the gate is aligned to the heterostructure, and where the potential is controlled from all sides simultaneously. In fact, drift-diffusion simulations using ATLAS by Silvaco indicates that it is possible to achieve a subthreshold swing of 60 mV/decade for gate length at least down to 100 nm.11 Because of the hysteresis, it is not possible to obtain an unambiguous value for the transconductance, dIds/dVgs. For the InAs/InAsP transistor, the measured transconductance at Vds ) 0.3 V is between 3.8 and 6.4 µA/ V, compared with 3.3 and 4.7 µA/V for the InAs transistor, depending on the direction of the sweep. It is interesting that the transconductance for the barrier transistor compares favorably to the pure InAs transistor. Because the drain current in the on state for the InAs/InAsP transistor is to a large extent controlled by tunneling through parts of the barrier, it is likely to be more sensitive to the gate voltage as compared to the situation in the device without any barrier. To obtain a rough estimate for the mobility of our pure InAs wires, we first calculate the gate capacitance per unit length using a cylinder on a conducting plate model12 Cg ) L
2πox0 r+h cosh-1 r
(
)
(1)
where r is the nanowire radius, L is the source-drain distance 1843
Figure 3. Plots of Ids vs Vgs and transconductance plot. (a) Logarithmic plot of Ids-Vgs at Vds ) 0.3 V. A large increase in the maximum current on-off ratio (from ∼10 to 27 000 at Vgs ) -6 V) as well as reduced subthreshold swing is obtained (from 4 V/decade to 0.9 V/decade). The arrows indicate the direction of the gate sweep. (b) Linear plot of the curves shown in Figure 3a. The gate sweep here is from Vgs ) 2 V to -7 V.
(L ≈ 2 µm), h is the SiO2 thickness (h ) 20 nm), and ox is the SiO2 dielectric constant (ox ) 3.9). The mobility in the low field region can then be calculated by µn )
dIds L2 dVgs VdsCg
(2)
Using our obtained values, we obtain a mobility of µn ≈ 1500 cm2/Vs. This value compares favorably to published data from wires in other material systems,12-13 most likely originating from the small effective mass of InAs. A further increase in mobility is expected by using surface passivation techniques. Because the barrier device shows similar oncurrent levels, the InAsP segment is also expected to have a mobility of the same order of magnitude as the pure InAs wire. The devices display a fairly large output conductance, which is visible in Figure 2, for both transistors’ cases. This large output conductance is often seen in the back-gate geometry, especially for thicker nanowires, and can be effectively minimized in a wrap-gate geometry.2,11 The barrier height of the InAsP barrier is further estimated by taking I-V measurements at temperatures between 300 and 460 K and then fitting an activation energy from an Arrhenius plot (extrapolated to Vds ) 0 V), by using the standard expression for thermionic emission over a barrier
( )
J ∝ T 2 exp -
qφb kT
(3)
where T is the temperature and Φb is the heterojunction barrier. In Figure 4, the obtained barrier height as a function of gate voltage is shown. For a gate voltage of 0 V, a barrier height of 280 meV is obtained. The nominal barrier height for unstrained InAs0.7P0.3 is expected to be about 160 meV.9 We find this to be a reasonable agreement because in this 1844
Figure 4. (a) Extracted barrier height as a function of applied gate voltage. (b) Example Arrhenius plots for barrier height extraction, at Vds ) 0.1 V, for three different values of Vgs.
device geometry it is difficult to obtain the exact barrier height due to a possible built-in gate voltage shift originating from work function differences and charges in the oxide and oxide/wire interface. Equation 3 is strictly only valid for flat band conditions, that is, around Vgs ) 0 V. For large enough negative gate voltages, the entire channel is depleted, and the current is limited by diffusion, changing eq 3 to
(
J ∝ T exp -
)
qφb + qUc(Vgs) kT
(4)
where Uc(Vgs) is the source-channel potential barrier due to the negative gate voltage, as illustrated in Figure 5. This implies that the minimum achievable thermionic off current should be smaller for a heterostructure transistor compared with the homogeneous transistor. We also point out that, for large negative gate biases, the deduced barrier height saturates at ∼Eg + ∆Ec, in agreement with eq 4. For large positive gate voltages, the measured value of Φb reduces toward zero because of field-assisted tunneling processes and a strong electron accumulation in front of the barrier. Nano Lett., Vol. 6, No. 9, 2006
Figure 5. Schematic band diagrams for field-effect transistors in on and off state. (a) Band diagram for a conventional FET. (b) The band structure of the heterostructure FET under similar gate conditions.
To discuss the various contributions to the subthreshold reduction, we first consider the influence of the barrier using modeling and simulations and then add the effect of the surface conduction using simulations. Figure 5a shows a schematic band diagram for a conventional n-type FET. In the long channel case, the on current (Vgs > VT) for small source-drain voltages is essentially set by the drift current between source and drain, J ≈ µn × n, where n is the electron concentration in the channel. The off current (Vgs < VT) is determined by diffusion across the channel.14 In Figure 5b, a similar band diagram of the heterostructure FET is shown. A thin segment, with a thickness wb, of largerband-gap material is introduced into the channel, giving rise to an offset in the conduction and valence band. The induced offset is similar to the induced barrier in a conventional n-type enhancement mode MOSFET. This will result in a shift in of the threshold voltage toward larger values of Vgs. For large enough values of Vds and a Vgs above threshold, the barrier will be essentially triangular, and electrons can easily tunnel through the barrier. For Vgs below threshold, the barrier is rectangular (because most of the field drops close to the drain contact) and can effectively block the off current. For a fixed nanowire radius, the subthreshold slope is therefore expected to be smaller for a heterostructure FET compared with a homogeneous FET.7,11 By designing the barrier with an appropriate thickness and barrier height, it is possible to achieve an on current close to that of the homogeneous InAs FET. To validate the model and to get a better understanding of the transport properties in these InAs back-gated transistors, we have performed numerical 3D drift-diffusion simulations using ATLAS by Silvaco. The transistor was modeled as a 2-µm-long 50 × 50 nm2 square InAs wire including a 150-nm-thick InAs0.75P0.25 barrier for the heterostructure device. The wire was placed on a 20-nm-thick SiO2 layer separating the wire from the back gate. Ideal, 200-nm-wide ohmic contacts were used for source and drain contacts. The electron and hole mobilities were set to constants µn ≈ 2500 cm2/Vs and µp ≈ 150 cm2/Vs, respectively, for both the InAs and InAsP. A background doping level of 2 × 1017 cm-3 was used. To account for the surface pinning of InAs, Nano Lett., Vol. 6, No. 9, 2006
Figure 6. Comparison of transfer characteristics for measured and simulated data taken at Vds ) 0.3V. Solid lines are experimental data for four different InAs and InAsP devices, respectively. The dashed lines are corresponding 3D drift-diffusion simulations.
additional positive surface charge of 1.0 × 1012 cm-2 has been introduced to create a surface accumulation layer in the model, which is known to exist for InAs. A good agreement between the experimental values and the simulated transfer characteristics is obtained; see Figure 6. For the InAs transistor, the simulations confirm that the poor offcharacteristics are set mainly by hole accumulation at the nanowire/SiO2 interface. This accumulation of positive charge screens the potential control of the rest of the nanowire, which allows for a conductive path along the top of the nanowire. Adding the barrier alone in the simulations while keeping the concentration of surface charges constant does not alter the simulated characteristics substantially and does not agree with the experimental data. This is expected, because in this case the gate also has a weak effect on the potential close to the top of the nanowire due to hole accumulation for large negative gate biases. With the addition of a conduction band offset, the InAsP segment also affects the surface pinning. To model this, we lowered the interface charge to 1.0 × 1011 cm-2 in the barrier region (while keeping the InAs surface charge fixed at 1 × 1012cm-2) and observed a substantially better fit with the experimental data, including a maximum on-off current ratio of almost 103, as shown in Figure 6. To verify that the change in surface charge is not alone responsible for the observed behavior, we replaced the barrier with a segment with zero interface charge. The simulated data (not shown) for this test structure has stronger similarities with the data for the homogeneous InAs nanowire than that for the InAsP heterostructure nanowire, which again demonstrates the importance of the barrier in the structure. In this comparison, we not only learn that the surface charge along the InAs nanowire considerably influences the transistor characteristics but also that the barrier has a stronger influence. The operation of the barrier is further experimentally supported from the determination of the barrier height in Figure 4, which shows that the maximum effective barrier is substantially larger than the InAs band 1845
gap. Surface passivation, the use of core/shell structures, wrap-gate formation, or the introduction of heterostructure barriers, as shown in this paper, will reduce the influence of the surface states and improve the transistor characteristics. In fact, the wrap-gated transistors with 100 mV/decade subthreshold slopes and 103 maximum on-off current ratio have been reported already.2 Applying the concept in this paper, the introduction of the heterobarrier into the channel, to the wrap-gate transistor will allow for further tailoring of the device characteristics and allow careful benchmarking.11 To summarize, we have introduced a heterostructure in the channel of an InAs field-effect transistor and shown that it is possible to enhance the transistor characteristics. The maximum current on-off ratio, the subthreshold swing, and the transconductance can all be improved by using heterostructures. For optimum performance, the heterostructure design has to be optimized, with respect to barrier height, thickness, and grading. The nanowire diameter also has to be addressed. A vertical wrap-gate geometry should also be used to maximize the gate coupling. The nanowire geometry is ideal for this kind of transistor, with its possibilities for perfect heterojunctions of defect-free growth of non-latticematched materials. Furthermore, our pure InAs nanowires show a high low-field mobility of 1500 cm2/Vs, which makes them interesting for high-speed applications. Acknowledgment. We thank Greg Snyder at Notre Dame for providing the SiO2/Si substrates. This work was supported by the Swedish Foundation for Strategic Research and the EU program NODE 015783.
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NL052468B
Nano Lett., Vol. 6, No. 9, 2006
