In Situ Axially Doped n-Channel Silicon Nanowire Field-Effect

Nov 1, 2008 - Alan Colli , Abbes Tahraoui , Andrea Fasoli , Jani M. Kivioja , William I. Milne and Andrea C. Ferrari. ACS Nano 2009 3 (6), 1587-1593...
0 downloads 0 Views 638KB Size
Download PDF
NANO LETTERS

In Situ Axially Doped n-Channel Silicon Nanowire Field-Effect Transistors

2008 Vol. 8, No. 12 4359-4364

Tsung-ta Ho,† Yanfeng Wang,† Sarah Eichfeld,‡ Kok-Keong Lew,‡ Bangzhi Liu,‡ Suzanne E. Mohney,‡,§ Joan M. Redwing,†,‡,§ and Theresa S. Mayer*,†,§ Department of Electrical Engineering, Department of Materials Science and Engineering, and Materials Research Institute, The PennsylVania State UniVersity, UniVersity Park, PennsylVania 16802 Received July 22, 2008; Revised Manuscript Received September 26, 2008

ABSTRACT (n+-p--n+)

Axially doped silicon nanowires were synthesized using the vapor-liquid-solid technique by sequentially modulating the introduction of phosphine to the inlet gas stream during growth from a silane source gas. Top-gate and wrap-around-gate metal oxide semiconductor field-effect transistors that were fabricated after thermal oxidation of the silicon nanowires operate by electron inversion of the p- body segment and have significantly higher on-state current and on-to-off state current ratios than do uniformly p--doped nanowire field-effect devices. The effective electron mobility of the devices was estimated using a four-point top-gate structure that excludes the source and drain contact resistance and was found to follow the expected universal inversion layer mobility versus effective electric field trend. The field-effect properties of wrap-around-gate devices are less sensitive to global-back-gate bias and thus provide better electrostatic control of the nanowire channel. These results demonstrate the ability to tailor the axial doping profile of silicon nanowires for future planar and vertical nanoelectronic applications.

Engineering materials on the nanoscale by combining controlled nanomaterial synthesis and self-assembly methods offers the potential to create new electronic and optical devices with improved performance and functionality.1-3 Semiconductor nanowires grown using the vapor-liquid-solid (VLS) technique have been of particular interest as a model system for studying new physical phenomena arising from their scaled geometries4-6 as well as for applications in highperformance vertical transistors and 7-11 thin-film electronic,12 electro-optical,2,13 and sensing devices14-16 and circuits.17 However, the use of relatively immature nanowire growth, doping, and device integration processes have made it difficult to elucidate and compare electrical transport properties across different device platforms (e.g., nanowire versus planar) and length scales.18-24 In this letter, we show that thermally oxidized axially doped n+-p--n+ silicon nanowires (SiNWs) grown by the VLS technique can be used to fabricate stable and reproducible top-gate (TG) and wrap-around-gate (WAG) metal oxide semiconductor field-effect transistors (MOSFETs) that operate by electron inversion of the p- body segment and have both a high on-state current (Ion) and a high on-to-off-state current ratio (Ion/Ioff). Measurements using back-gated structures that separately probe the n+ and p- regions confirm * Corresponding author. E-mail: [email protected]. † Department of Electrical Engineering. ‡ Department of Materials Science and Engineering. § Materials Research Institute. 10.1021/nl8022059 CCC: $40.75 Published on Web 11/01/2008

 2008 American Chemical Society

that radial thin film deposition of n-type Si onto the p- body is prevented during the growth of the second n+ SiNW segment. The dependence of the effective channel mobility on the effective electric field of long-channel TG SiNW MOSFETs is estimated from four-point TG-dependent measurements of the channel resistance. The properties of the TG and WAG devices are compared as a function of global-back-gate bias to show that the WAG SiNW MOSFET is shielded from external electric fields and thus provides better control of the channel potential for effective device switching. The axially doped (n+-p--n+) SiNWs studied here were synthesized by Au-catalyzed VLS growth in a hot-wall lowpressure chemical vapor deposition (LPCVD) reactor using silane (SiH4) as the Si source gas and phosphine (PH3) for n+-type doping of the source and drain regions. Heavily doped source and drain regions were previously demonstrated by Si epitaxy and ion implantation of unintentionally doped VLS-grown SiNWs following their on-chip assembly.25,26 However, such top-down doping methods may be difficult to incorporate into future vertical nanowire MOSFET fabrication processes8,11,27 or nanowire MOSFET biosensors that rely on coating the nanowire surfaces with probe molecules prior to on-chip assembly.28 In contrast, in situ axial doping is a viable technique for both of these device technologies and may be combined with axial heterostructures (e.g., doped SiGe source/drain)29-31 and radial gate dielectrics32,33 to improve device performance further.34

Figure 1. (a) Schematic and (b) FE-SEM image of a thermally oxidized axially doped WAG SiNW MOSFET. The device contains two pairs of source and drain contacts, a local back gate and top gate that together form a wrap-around gate and a global back gate. The n+ source and drain segments are light blue, and the SiO2 shell is red. The p- body is positioned underneath the top-gate electrode.

Achieving pure axial doping of VLS-grown nanowires has been challenging because the addition of many common LPCVD dopant precursors to the source gas can result in radial thin film deposition on the nanowire surface, which occurs simultaneously with axial VLS growth. For example, the use of diborane (B2H6) as a p-type dopant source at the elevated B2H6 partial pressures required for heavy p+-type doping resulted in the formation of an amorphous Si shell on the single crystal Si core20,35,36 as well as the precipitation of Au nanoparticles along the SiNW surface.36 Moreover, in other systems such as germanium (Ge)-Au, the p- and ntype dopants were incorporated via the nanowire surface instead of through the growth catalyst.37 The addition of B2H6 during LPCVD of Si thin films grown using SiH4 increased thin film deposition because of gas-phase interactions with SiH4, whereas PH3 suppressed the thin film growth rate by an order of magnitude or more because of competitive adsorption effects.38 Therefore, PH3 is a better choice for in situ axial doping of SiNWs using SiH4 as a source gas and previously has been used to grow uniformly doped n+, n+-n-n+, and p+-i-n+ SiNWs18,23,39-42 with negligible radial overcoating. Figure 1a,b show a schematic illustration and a field emission scanning electron microscope (FE-SEM) image of a non-self-aligned long-channel WAG MOSFET that was fabricated using the n+-p--n+ SiNWs. A silicon dioxide (SiO2) shell that was grown by dry thermal oxidation of the SiNWs prior to on-wafer integration served as the gate dielectric of the SiNW MOSFET.32 The completed device structure consists of two pairs of source/drain metal electrodes that electrically contact the n+ SiNW segments, a local back gate and top gate that together form a WAG that fully surrounds the p- body and overlaps the n+ source and drain segments, and a global back gate. Additional devices were fabricated without the local back gate to compare the fieldeffect properties of TG and WAG structures. The n+-p--n+ axial doping profile of the SiNWs was achieved by the introduction of PH3 into the input gas stream at a PH3 to SiH4 gas flow ratio of 10-3 in the following sequence: (1) PH3 and SiH4 f (2) SiH4 f (3) PH3 and SiH4.43 Our previous work demonstrated that heavily doped n+ SiNWs grown under these conditions have a four-point resistivity of (5.1 ( 2.1) × 10-3 Ω cm, whereas the unintentionally doped SiNWs grown in this reactor are p type with a resistivity of (4.7 ( 2.5) × 104 Ω cm.44 The acceptor 4360

concentration (NA) of the unintentionally doped SiNWs is probably considerably larger than the corresponding bulk value of ∼1011 cm-3. This is because the high Si/SiO2 interface charge densities present on the as-grown (native oxide) SiNWs used for the resistivity measurements can fully deplete the nanowire with an NA of up to ∼1017 cm-3. The Au catalyst nanoparticles used for these growths were formed by heating a 5-nm-thick layer of Au that was sputter deposited on an oxide-coated Si substrate, which gave asgrown SiNWs with diameters varying from 40 to 120 nm. The growth time of each segment was adjusted to deposit n+ segments on each side of a 1-µm-long p- body. This allowed the integration of two independent electrical contacts on each n+ segment to estimate the source/drain series resistance of the device. Moreover, the 1-µm-long p- body minimized the impact of short-channel effects in determining the effective mobility of the SiNW MOSFETs; doped segments as short as 120 nm have been demonstrated under these conditions.45 Following VLS growth, the Au catalyst particles were removed by selective wet etching, and the SiNWs were thermally oxidized using dry O2 in an isothermal furnace held at 700 °C for 4 h.32 These conditions gave SiO2 shells that varied from 7 to 10 nm in thickness depending on the starting diameter of the as-grown SiNWs. Transmission electron microscopy (TEM) was used to study the structural properties of as-grown and thermally oxidized n+-p--n+ SiNWs. Selective electroless plating of Au metal on the n+ relative to the p- SiNW segments was used to determine the segment lengths relative to the Au catalyst particle.45 Figure 2 a-d shows the schematic and plan-view TEM images of a representative as-grown SiNW (not plated) collected near the base of the first n+ segment, the midpoint of the p- segment, and the tip of the second n+ segment using the Au tip as a measurement reference. The single crystal n+-p--n+ SiNW has a smooth surface with no visible evidence of tapering or a decrease in wire diameter from the base to the tip, which indicates that the Si thin film coating during VLS is negligible for these growth conditions. Figure 2e shows a plan-view TEM image of a thermally oxidized SiNW with a Si core diameter and SiO2 shell thickness of 37 and 8 nm, respectively. The n+-p--n+ SiNW MOSFETs were fabricated by positioning single thermally oxidized SiNWs between pairs of Ti/Au (20/60 nm) electrodes patterned on an n+ Si Nano Lett., Vol. 8, No. 12, 2008

Figure 2. (a) Schematic and (b-d) TEM images of an as-grown axially doped n+-p--n+ SiNW. The positions along the length of the SiNW where the TEM images were collected are shown by the square boxes on the schematic. The SiNW is a single crystal with a very thin native oxide. (e) TEM image of a thermally oxidized axially doped n+-p--n+ SiNW where the Si core diameter is 37 nm and the SiO2 shell thickness is 8 nm.

substrate (0.001 Ω cm) coated with a 100-nm-thick silicon nitride (Si3N4) back-gate dielectric layer using electric-fieldassisted assembly.46 The long- and short-range forces exerted on the SiNWs during assembly tend to center a single NW, and thus the corresponding p- body, in the gap between each pair of electrodes. (See Figure 1b.) A global-back-gate contact was formed by sputtering Ti/Au (20/60 nm) metal on the backside of the n++ Si substrate, and the source/drain contacts were defined on the n+ SiNW segments using electron beam lithography (Leica EBPG-5HR, MAA-MMA/ PMMA bilayer resist). The SiO2 shell layer that was exposed during this lithographic step was removed by the use of a highly selective buffered oxide etch before thermally evaporating and lifting off Ti/Au (100/100nm) source/drain metal contacts. Top-gate SiNW MOSFETs were completed using electron beam lithography and lift off of thermally evaporated Ti/Au (80/40 nm) metal to define the non-self-aligned topgate electrode that covered the 1 µm p- body and overlapped the n+ Si segments. Cross-sectional TEM indicated that the evaporated top-gate metal surrounded ∼75% of the nanowire circumference, leaving the base of the SiNW in contact with the global back gate. The WAG devices incorporated an additional local back gate that was aligned to the top gate and thus fully surrounded the p- body. (See Figure 1). Transfer characteristics were measured in TG, global-backgate, and WAG device configurations to investigate the electrical properties of the axially doped n+-p--n+ SiNW MOSFETs, the n+ source and drain segments, and the pbody region. Figure 3a plots the drain-to-source current (IDS) versus TG-to-source voltage (VGS-TG) at two different drainto-source voltages (VDS) of 0.1 and 1 V (forward and reverse sweeps, sweep rate ) 200 mV/sec) for a device that was fabricated from a single 82 nm diameter SiNW with a 9 nm SiO2 shell. These data show that the hysteresis between successive gate voltage sweeps is negligible and that the axially doped SiNW FET turns on for values of VGS-TG that are more positive than the threshold voltage (Vth) ) 0 V, where Vth is extrapolated from linear plot of transfer characteristics measured at low drain bias. The drain induced barrier lowering determined by calculating the difference in Vth at VDS ) 0.1 and 1 V (∆Vth vs ∆VDS) is < 50 mV/V, as expected for a long-channel device.47 The inverse subthreshold slope (S) is 217 mV/decade, which is degraded from the Nano Lett., Vol. 8, No. 12, 2008

Figure 3. (a) Transfer characteristics of an axially doped TG SiNW MOSFET measured at VDS ) 0.1 V (O) and 1 V (b) by sweeping VGS-TG from -3 to 3 V at 200 mV/sec. The devices have negligible hysteresis with Ion ) 2.7 µA and Ion/Ioff ≈ 107 (VDS ) 1 V). Inset shows characteristics of the n+ SiNW segment measured between the two source electrodes that show high Ion ≈ 12 µA at VDS ) 1 V and weak global-back-gate bias dependence. (b) Transfer characteristics of a global-back-gated control device shown in the inset. The data given by O were collected by applying VDS across the two outer contacts, which probes the n+-p--n+ SiNW. The data plotted with b were collected by applying VDS across the two inner contacts, which probes only the p- SiNW body segment. These properties are consistent with those measured on uniformly p--doped back-gated SiNW FETs. (c) Plot of µeff versus Eeff determined from the measured Rch. Inset is schematic showing the circuit model used to estimate µeff that excludes the effect of contact resistance. 4361

Figure 4. Transfer characteristics measured on (a) an axially doped TG SiNW MOSFET and (b) an axially doped WAG SiNW MOSFET at six global-back-gate biases from -10 to 15 V in steps of 5 V (from right to left) with VGS-TG sweeping from -3 to 3 V at VDS ) 1 V. The S remains constant with varying global-back-gate bias for the WAG SiNW MOSFET because of complete shielding of the channel from the back-gate electric field.

ideal value of 60 mV/decade because of the high Si/SiO2 interface state density. Significant improvements in S are expected by the optimization of the SiNW surface preparation prior to oxidation and by the implementation of a postoxidation anneal.48,49 In contrast with uniformly doped p- SiNW FETs that have an Ion of a few nanoamperes and are turned off at positivegate biases,39 these axially doped n+-p--n+ SiNW MOSFETs have an Ion of 2.7 µA, which is three orders of magnitude higher, while maintaining a low Ioff with Ion/Ioff ≈ 107 at VDS ) 1 V. The low Ioff suggests that there is negligible n+ Si overcoating on the p- body, which would form a leakage path between the source and drain regions. The inset of Figure 3a plots the transfer characteristics of the n+ segments exposed between the pairs of source/drain contacts measured by varying global-back-gate voltage (VGS-GBG). The high Ion of 12 µA at VDS ) 1 V and weak dependence on back-gate voltage confirms that the n+ SiNW segments are sufficiently heavily doped to facilitate efficient electron tunneling through the Schottky barrier at the metal to n+ source/drain contacts of the device. To confirm that radial n+ Si overcoating of the p- body segment is prevented during VLS growth of the second n+ SiNW segment, additional global-back-gate control devices were fabricated by making outer electrical contacts to the n+ segments and inner contacts to the p- segment. (See inset of Figure 3b.) As shown in Figure 3b, the global-back-gated transfer characteristics measured between the two outer contacts is consistent with the axially doped TG SiNW MOSFET that has an Ion of 2.5 µA with Ion/Ioff ≈ 107 at VDS ) 1 V. In contrast, the FET formed by contacting the pbody region turns on for values of VGS-GBG that are more negative than Vth ) 2 V and has an Ion of 10 nA with Ion/Ioff ≈ 104 at VDS ) 1 V. These same properties are observed for uniformly doped p- SiNWs grown in the same reactor without n+ segments, which are dominated by the modulation of holes injected at the Schottky barrier formed between the source contact and the lightly doped p- SiNW.39 Therefore, these data indicate that the switching properties of the n+-p--n+ TG SiNWs MOSFETs are due to the formation of an electron inversion layer in the p- SiNW body region as in conventional planar n channel Si MOSFETs.50 The effective mobility of the n+-p--n+ SiNW MOSFETs can be estimated by the use of the linear long-channel 4362

MOSFET equation given by µeff ) L2/RchCox(VGS-TG - Vth),47 where L is the p- SiNW segment (channel) length, Rch is the channel resistance, and Cox is the gate capacitance. As shown in Figure 1a,b, the additional contacts that are integrated onto the n+ SiNW segments allow direct measurement of the TG-dependent four-point SiNW MOSFET resistance (R4-pt-TG) excluding the source/drain contact resistance,51 which is a significant fraction of the two-point MOSFET resistance for these devices. Therefore, when the SiNW MOSFET is biased in the on state (VGS > Vth) with low drain bias in the linear region (VDS < VGS - Vth), Rch ) R4-pt-TG - RS - RD, where RS and RD are the extrinsic series resistances of the n+ SiNW source and drain segments, respectively. The values for RS and RD were found by multiplying the measured n+ SiNW four-point resistivity44 by the SiNW segment length and dividing by the crosssectional area (both determined from FE-SEM). The dependence of µeff on the effective electric field (Eeff) determined from Rch and the value of Cox estimated from the top-gate geometric capacitance52 is shown in Figure 3c and follows the universal inversion layer mobility trend for a doped source/drain Si MOSFET.53 The maximum value of µeff estimated for this TG SiNW MOSFET is 28 ( 2.6 cm2/ V·sec at Eeff of 0.16 MV/cm,54,55 which is lower than expected for planar Si devices.53 This is most likely due to the increased scattering from the high density of charge centers at the Si/SiO2 interface56 as well as an overestimate of the inversion layer charge (Cox(VGS-TG - Vth)) because of these charge states.57 Postoxidation annealing is currently being studied to improve the performance of the n+-p--n+ SiNW MOSFETs.49,56 The transfer characteristics of TG and WAG n+-p--n+ SiNW MOSFETs with 3-µm-long p- segments are compared in Figure 4 for global-back-gate biases varying from -10 to 15 V in steps of 5 V at VDS ) 1 V. The TG SiNW MOSFET shows a significant degradation in S from 240 to 315 mV/decade and a decrease in Vth from -120 to -690 mV as the global-back-gate bias is increased from -10 to 15 V. These properties are consistent with those observed for silicon-on-insulator trigate MOSFETs where the degradation of S and roll off of Vth can be qualitatively explained by the formation of a global-back-gate-induced inversion charge leakage path for electron conduction between the source and drain regions.58 In contrast, the S and Vth for the Nano Lett., Vol. 8, No. 12, 2008

WAG SiNW MOSFET are relatively insensitive to the global-back-gate bias because of complete shielding of the back-gate-induced electric field by the wrap around gate. Because these SiNW MOSFETs are long-channel devices (L ) 3 µm), the improvement of S to 165 mV/decade can be attributed to the larger Cox of the wrap gate as compared with the TG devices rather than a suppression of shortchannel effects. Nevertheless, the WAG structure is expected to reduce short-channel effects in aggressively scaled Si MOSFETs because of its superior electrostatic control of the channel.59 In summary, axially doped n+-p--n+ SiNWs were grown by direct introduction of n-type dopants from a PH3 gas source during VLS growth. The as-grown SiNWs were thermally oxidized to form Si/SiO2 core-shell structures and were integrated into doped source/drain TG and WAG MOSFETs that incorporated a global back gate and two separate contacts to the n+ SiNW segments. The transfer characteristics of these SiNW MOSFETs were stable with gate voltage cycling, and the devices turned on for values of VGS were more positive than Vth, which is consistent with switching by forming an electron inversion layer in the pbody segment. Additional electron microscopy and electrical characterization of back-gated control devices confirmed that radial overgrowth of n-type Si on the p- body was prevented during the growth of the second n+ SiNW segment. Both types of MOSFETs had high Ion values of 2.5 µA and Ion/Ioff ratios of 107 at VDS ) 1 V with S in the range of 217 to 165 mV/decade for TG and WAG devices, respectively. A maximum µeff estimated using the measured TG-dependent four-point SiNW MOSFET resistance was ∼28 ( 2.6 cm2/ V·sec at Eeff ) 0.16 MV/cm, which is lower than expected for planar Si MOSFETs. The degraded S and lower µeff can be attributed to the nonoptimized Si/SiO2 interface and are expected to improve with enhancements in surface preparation and postoxidation annealing. A comparison of globalback-gated TG and WAG SiNW MOSFETs shows that the WAG structure provides better electrostatic control of the nanowire channel with applied back-gate bias, which is expected to reduce short-channel effects in aggressively scaled devices. This work demonstrates the potential to use SiNWs in future nanoelectronic applications by engineering the device structure via axial doping during VLS growth. Acknowledgment. We thank Raseong Kim and Prof. Mark Lundstrom of Purdue University for insightful discussions on methods for estimating µeff. We also acknowledge the financial support of NSF NIRT (ECS-0609282 & CCF0303976), NSF MRSEC (DMR-0213623), and NRI/SRC Midwest Institute for Nanoelectronics and Discovery. The devices were fabricated at the PSU site of the NSF NNIN under grant no. 0335765. References (1) Cui, Y.; Lieber, C. M. Science 2001, 291, 851. (2) Duan, X.; Huang, Y.; Cui, Y.; Wang, J.; Lieber, C. M. Nature 2001, 409, 66. (3) Huang, Y.; Duan, X.; Cui, Y.; Lauhon, L. J.; Kim, K. H.; Lieber, C. M. Science 2001, 294, 1313. (4) Kotlyar, R.; Obradovic, B.; Matagne, P.; Stettler, M.; Giles, M. D. Appl. Phys. Lett. 2004, 84, 5270. Nano Lett., Vol. 8, No. 12, 2008

(5) Wang, J.; Solomon, P. M.; Lundstrom, M. IEEE Trans. Electron DeVices 2004, 51, 1366. (6) Ramayya, E. B.; Vasileska, D.; Goodnick, S. M.; Knezevic, I. IEEE Trans. Nanotechnol. 2007, 6, 113. (7) Takato, H.; Sunouchi, K.; Okabe, N.; Nitayama, A.; Hieda, K.; Horiguchi, F.; Masuoka, F. IEEE Trans. Electron DeVices 1991, 38, 573. (8) Ng, H. T.; Han, J.; Yamada, T.; Nguyen, P.; Chen, Y. P.; Meyyappan, M. Nano Lett. 2004, 4, 1247. (9) Bryllert, T.; Wernersson, L. E.; Froberg, L. E.; Samuelson, L. IEEE Trans. Electron DeVices 2006, 27, 323. (10) Bjork, M. T.; Hayden, O.; Schmid, H.; Riel, H.; Riess, W. Appl. Phys. Lett. 2007, 90, 142110. (11) Schmidt, V.; Riel, H.; Senz, S.; Karg, S.; Riess, W.; Gosele, U. Small 2006, 2, 85. (12) Duan, X.; Niu, C.; Sahi, V.; Chen, J.; Parce, J. W.; Empedocles, S.; Goldman, J. L. Nature 2003, 425, 274. (13) Huang, M. H.; Mao, S.; Feick, H.; Yan, H.; Wu, Y.; Kind, H.; Weber, E.; Russo, R.; Yang, P. Science 2001, 292, 1897. (14) Cui, Y.; Wei, Q.; Park, H.; Lieber, C. M. Science 2001, 293, 1289. (15) Zheng, G.; Patolsky, F.; Cui, Y.; Wang, W. U.; Lieber, C. M. Nat. Biotechnol. 2005, 23, 1294. (16) Zhou, X. T.; Hu, J. Q.; Li, C. P.; Ma, D. D. D.; Lee, C. S.; Lee, S. T. Chem. Phys. Lett. 2003, 369, 220. (17) Friedman, R. S.; McAlpine, M. C.; Ricketts, D. S.; Ham, D.; Lieber, C. M. Nature 2005, 434, 1085. (18) Cui, Y.; Duan, X.; Hu, J.; Lieber, C. M. J. Phys. Chem. B 2000, 104, 5213. (19) Cui, Y.; Zhong, Z.; Wang, D.; Wang, W. U.; Lieber, C. M. Nano Lett. 2003, 3, 149. (20) Lew, K. K.; Pan, L.; Bogart, T. E.; Dilts, S. M.; Dickey, E. C.; Redwing, J. M.; Wang, Y.; Cabassi, M.; Mayer, T. S.; Novak, S. W. Appl. Phys. Lett. 2004, 85, 3101. (21) Lind, E.; Persson, A. I.; Samuelson, L.; Wernersson, L. E. Nano Lett. 2006, 6, 1842. (22) Wang, D.; Chang, Y. L.; Wang, Q.; Cao, J.; Farmer, D.; Gordon, R.; Dai, H. J. Am. Chem. Soc. 2004, 126, 11602. (23) Wang, Y.; Lew, K. K.; Ho, T. T.; Pan, L.; Novak, S. W.; Dickey, E. C.; Redwing, J. M.; Mayer, T. S. Nano Lett. 2005, 5, 2139. (24) Weber, W. M.; Geelhaar, L.; Graham, A. P.; Unger, E.; Duesberg, G. S.; Liebau, M.; Pamler, W.; Che`ze, C.; Riechert, H.; Lugli, P. Nano Lett. 2006, 6, 2660. (25) Cohen, G. M.; Rooks, M. J.; Chu, J. O.; Laux, S. E.; Solomon, P. M.; Ott, J. A.; Miller, R. J.; Haensch, W. Appl. Phys. Lett. 2007, 90, 233110. (26) Hayden, O.; Bjork, M. T.; Schmid, H.; Riel, H.; Drechsler, U.; Karg, S. F.; Lortscher, E.; Riess, W. Small 2007, 3, 230. (27) Thelander, C.; Agarwal, P.; Brongersma, S.; Eymery, J.; Feiner, L. F.; Forchel, A.; Scheffler, M.; Riess, W.; Ohlsson, B. J.; Go¨sele, U. Mater. Today 2006, 9, 28. (28) Li, M.; Bhiladvala, R. B.; Morrow, T. J.; Sioss, J. A.; Lew, K. K.; Redwing, J. M.; Keating, C. D.; Mayer, T. S. Nature Nanotechnol. 2008, 3, 88. (29) Dickey, E. C.; Pan, L.; Lew, K. K.; Redwing, J. M. Microsc. Microanal. 2004, 10, 22. (30) Pan, L.; Lew, K. K.; Redwing, J.; Dickey, E. Microsc. Microanal. 2005, 11, 1722. (31) Wu, Y.; Fan, R.; Yang, P. Nano Lett. 2002, 2, 83. (32) Liu, B.; Wang, Y.; Ho, T.; Lew, K. K.; Eichfeld, S. M.; Redwing, J. M.; Mayer, T. S.; Mohney, S. E. J. Vac. Sci. Technol., A 2008, 26, 370. (33) Wang, D.; Wang, Q.; Javey, A.; Tu, R.; Dai, H.; Kim, H.; McIntyre, P. C.; Krishnamohan, T.; Saraswat, K. C. Appl. Phys. Lett. 2003, 83, 2432. (34) Chen, X.; Ouyang, Q.; Onsongo, D. M.; Jayanarayanan, S. K.; Tasch, A.; Banerjee, S. Appl. Phys. Lett. 2000, 77, 1656. (35) Lauhon, L. J.; Gudiksen, M. S.; Wang, D.; Lieber, C. M. Nature 2002, 420, 57. (36) Pan, L.; Lew, K. K.; Redwing, J. M.; Dickey, E. C. J. Cryst. Growth 2005, 277, 428. (37) Tutuc, E.; Appenzeller, J.; Reuter, M. C.; Guha, S. Nano Lett. 2006, 6, 2070. (38) Meyerson, B. S.; Olbricht, W. J. Electrochem. Soc. 1984, 131, 2361. (39) Wang, Y.; Cabassi, M.; Ho, T. T.; Lew, K. K.; Redwing, J.; Mayer, T. Proceedings of 62nd Device Research Conference, University of Notre Dame, Notre Dame, Indiana, June 21-23, 2004; p 23. (40) Yang, C.; Zhong, Z.; Lieber, C. M. Science 2005, 310, 1307. 4363

(41) Yang, C.; Barrelet, C. J.; Capasso, F.; Lieber, C. M. Nano Lett. 2006, 6, 2929. (42) Bjork, M. T.; Knoch, J.; Schmid, H.; Riel, H.; Riess, W. Appl. Phys. Lett. 2008, 92, 193504. (43) Silane (SiH4, 10% in H2) and phosphine (PH3, 100 ppm in H2) were used as the Si and n-type dopant gas sources, respectively. The growth temperature was 500 °C with a total reactor pressure of 12 Torr. The SiH4 partial pressure was maintained at 0.65 Torr throughout the growth, resulting in a SiNW growth rate of approximately 1 µm/min. (44) Eichfeld, S. M.; Ho, T. T.; Eichfeld, C. M.; Cranmer, A.; Mohney, S. E.; Mayer, T. S.; Redwing, J. M. Nanotechnology 2007, 18, 315201. (45) Eichfeld, C. M.; Wood, C.; Liu, B.; Eichfeld, S. M.; Redwing, J. M.; Mohney, S. E. Nano Lett 2007, 7, 2642. (46) Smith, P. A.; Nordquist, C. D.; Jackson, T. N.; Mayer, T. S.; Martin, B. R.; Mbindyo, J.; Mallouk, T. E. Appl. Phys. Lett. 2000, 77, 1399. (47) Taur, Y.; Ning, T. H. Fundamentals of Modern VLSI DeVices; Cambridge University Press: New York, 1998. (48) Deal, B. E. J. Electrochem. Soc. 1974, 121, 198C. (49) Reed, M. L.; Plummer, J. D. J. Appl. Phys. 1988, 63, 5776. (50) Sze, S. M. Physics of Semiconductor DeVices, 2nd ed.; Wiley: New York, 1981. (51) R4-pt-TG was determined by dividing the differential voltage measured across the two inner electrodes using a high impedance electrometer by the current flowing through the SiNW for different values of top gate voltage.

4364

(52) The TG SiNW MOSFET gate capacitance was estimated from the geometric capacitance Cox ) (2πεoxL)/ln[(D + 2tox)/(D)], where D is the SiNW diameter, εox is the SiO2 permittivity, and tox is the gate oxide thickness. (53) Takagi, S.; Toriumi, A.; Iwase, M.; Tango, H. IEEE Trans. Electron DeVices 1994, 41, 2363. (54) The standard deviation of the estimated effective mobility (( 2.6 cm2/ V·sec) was calculated from the standard deviation of the four-point resistivity (( 2.1 × 10-3 Ω cm). (55) Effective electric field is calculated using Poisson’s equation q(Ndpl + ηNinv)/ε, where Ndpl is the surface depletion charge concentration of the p--body, η is the prefactor that accounts for the dependence of the inversion charge layer thickness on the Si surface crystal orientation, and Ninv is the surface inversion carrier concentration. We used η )1/3 for a (111) Si surface. Ndpl was neglected because the p--body is lightly doped. (56) Sun, S. C.; Plummer, J. D. IEEE J. Solid-State Circuits 1980, 15, 562. (57) Gunawan, O.; Sekaric, L.; Majumdar, A.; Rooks, M.; Appenzeller, J.; Sleight, J. W.; Guha, S.; Haensch, W. Nano Lett. 2008, 8, 1566. (58) Lemme, M. C.; Mollenhauer, T.; Henschel, W.; Wahlbrink, T.; Baus, M.; Winkler, O.; Granzner, R.; Schwierz, F.; Spangenberg, B.; Kurz, H. Solid-State Electron. 2004, 48, 529. (59) Park, J. T.; Colinge, J. P. IEEE Trans. Electron DeVices 2002, 49, 2222.

NL8022059

Nano Lett., Vol. 8, No. 12, 2008