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C: Surfaces, Interfaces, Porous Materials, and Catalysis

In Situ Real-Time Measurements for Ambipolar Channel Formation Processes in Organic Double-Layer Field-Effect Transistors of CuPc and F CuPc 16

Keitaro Eguchi, Michio M. Matsushita, and Kunio Awaga J. Phys. Chem. C, Just Accepted Manuscript • DOI: 10.1021/acs.jpcc.8b08744 • Publication Date (Web): 26 Oct 2018 Downloaded from http://pubs.acs.org on October 27, 2018

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The Journal of Physical Chemistry

In Situ Real-Time Measurements for Ambipolar Channel Formation Processes in Organic Double-Layer Field-Effect Transistors of CuPc and F16CuPc

Keitaro Eguchi,*† Michio M. Matsushita, and Kunio Awaga*

Department of Chemistry and Integrated Research Consortium on Chemical Science (IRCCS), Nagoya University, Furo-cho, Chikusa-ku, Nagoya 464-8602, Japan †

Present address: Physics Department, Technical University of Munich, James-Franck-Straße

1, D-85748 Garching, Germany * E-mail: [email protected] (KE), [email protected] (KA)

Corresponding author Kunio Awaga Department of Chemistry, Nagoya University Furo-cho, Chikusa-ku Nagoya 464-8602, Japan E-mail: [email protected] Tel: +81-52-789-2487 Fax: +81-52-789-2484

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Abstract Molecular donor–acceptor heterostructures have been utilized to obtain ambipolar characteristics in organic field-effect transistors (OFETs). In the present work, we examined the surface morphologies of the double-layer thin films of the donor-acceptor pair of copper phthalocyanine (CuPc) and its fluorinated analogue (F16CuPc). We then performed in situ real-time measurements on the formation processes of ambipolar transport channels in the double-layer CuPc/F16CuPc and F16CuPc/CuPc FETs, with gradual growths of the top layers on the bottom layers under high vacuum conditions. When CuPc was deposited on the F16CuPc bottom layer, the n-type mobility was immediately enhanced due to an electron carrier injection to the F16CuPc layer. In the case of CuPc top-layer growth, ambipolar properties were clearly seen when the top layer was thicker than 2.4 ML. Finally, the CuPc/F16CuPc FET exhibited a well-balanced ambipolar transport with p- and n-type mobilities of 2.6 × 10−2 and 1.4 × 10−2 cm2/Vs, respectively. In contrast, when F16CuPc was deposited on the CuPc bottom layer, the ptype transport of CuPc was suppressed due to the formation of trap states at the interface. Further deposition of F16CuPc resulted in the recovery of p-type transport in CuPc and produced an ambipolar transport with p- and n-type mobilities of 3.2 × 10−3 and 3.7 × 10−3 cm2/Vs, respectively, when F16CuPc was thicker than 3.2 ML. This suggested that smoother interfaces between CuPc and F16CuPc would 2 ACS Paragon Plus Environment

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produce higher mobilities in the heterostructure OFETs.

Introduction Molecular-level control of donor (D)–acceptor (A) heterostructures is a key issue in organic electronics, specifically in the development of organic photovoltaics,1-2 light-emitting diodes,3-4 and field-effect transistors (OFETs),5-7 because DA heterostructures govern the exciton dissociation and hole–electron recombination at the DA interfaces as well as the hole/electron accumulation and dynamics in the donor–acceptor layer. In OFETs, DA heterostructures have been utilized to realize ambipolar characteristics6-11 since the first examples using α-hexathienylene and fullerene, reported by Dodabalapur et al.5 The ambipolar performance of the OFETs with DA double layers depends primarily on the thickness of the first layer on the gate (G)-insulating layer,5, 7, 12 because the carrier density, induced by the field effect, is limited to the interface between the first layer and the gate insulator.13-15 For instance, in an A/D/G structure, the operating mode changes gradually from n-type to ambipolar and p-type transport, with an increase in the thickness of the D layer from zero. It is empirically recognized that ambipolar behavior occurs when the thickness of the first layer is in the range of 2–20 nm7-8, 12 and that well-balanced ambipolar characteristics can be realized by precisely controlling the 3 ACS Paragon Plus Environment


thickness of the first layer.6,

10, 16

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This type of ambipolar characteristics has been applied to

complementary inverters.16 In contrast to the extensive studies on the first layer of DA double-layer OFETs, less attention has been paid to the second layer and the DA interface. This is because FET measurements were conventionally carried out in ex situ conditions, so it was difficult to distinguish the effects of the second layer from those of ambient gases. Therefore, in situ FET characterizations, which are conducted under high vacuum without exposure to air, are required to clarify the effects of the DA heterointerfaces. Copper

phthalocyanine

(CuPc)

and

its

fluorinated

analogue,

copper

hexadecafluorophthalocyanine (F16CuPc) (see Fig. 1a), constitute a promising pair for DA heterostructures in organic electronics by virtue of their high thermal and chemical stabilities as well as their similarities in both molecular shape and thin-film structures. It is notable that CuPc and F16CuPc exhibit p- and n-type transports, respectively, with well-balanced field-effect mobilities μ. The values are on the order of ~10−1 cm2/Vs for their crystalline nanowires17-18 and ~10−2 cm2/Vs for their thin films.8, 19-21 By applying this material pair to the DA double-layer thin-film OFETs, ambipolar characteristics have been realized, though the μ values of hole and electron in these devices were smaller by one or two orders of magnitude than the corresponding values for the single-layer OFETs of CuPc and F16CuPc.8, 10 In the present study, we elucidated the formation processes of ambipolar channels in CuPc4 ACS Paragon Plus Environment

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F16CuPc double-layer OFETs (see Fig. 1b) using in situ real-time OFET measurements under high vacuum conditions (P < 1×10−4 Pa) without exposure to air. We describe the effects of the growth of the second layer on the transfer characteristics and characterize the relationship between FET performance and the morphological properties of the heterointerfaces.

Results and Discussion First we characterized the morphologies of the single- and double-layer thin films of CuPc and F16CuPc because they strongly affect the electrical properties of thin films. These thin films were grown on Si substrates having thermally oxidized surfaces, at substrate temperatures of 25–41℃ with deposition rates of 0.3–0.5 ML/min. In these films, a thickness of 1 ML corresponded to 1.4 and 1.3 nm for F16CuPc and CuPc, respectively.8 Figures 2a-c show atomic force microscopy (AFM) images for a single-layer thin film of F16CuPc (3.8 ML) and two kinds of the double-layer thin films, CuPc (1.5 ML)/F16CuPc (3.8 ML) and CuPc (3 ML)/F16CuPc (3.8 ML). Figure 2d shows the cross-sectional profiles of the films. The single-layer thin film of F16CuPc (Fig. 2a) exhibit caterpillar-like crystalline grains with a height of ~1.5 nm, which nearly corresponds to the molecular length of F16CuPc. This means that, as reported previously, the F16CuPc molecules exhibit an edge-on alignment to the substrates and the crystalline grains grow parallel to the substrate surfaces.22-23 The caterpillar shape is also an evidence 5 ACS Paragon Plus Environment


for the edge-on alignment, as demonstrated by the combined measurements of AFM and X-ray diffraction in Ref. 24. The surfaces of the double-layer thin films also exhibit caterpillar-like structures (Figs. 2b and 2c), indicating an edge-on alignment in the top layers of CuPc, though the height differences in these second layers are larger than that of the F16CuPc single layer. The root-mean-square surface roughness RRMS for the F16CuPc single layer is 0.52 nm, while those for the CuPc (1.5- and 3ML)/F16CuPc double layers are 1.06 and 1.09 nm, respectively. Figures 2e-g show AFM images of the thin films of CuPc (3.6 ML), F16CuPc (1.5 ML)/CuPc (3.6 ML), and F16CuPc (3 ML)/CuPc (3.6 ML). The preparation conditions are the same as those described above. Figure 2h shows the cross-sectional profiles of these thin films. The single-layer CuPc thin film (Fig. 2e) exhibits caterpillar-like crystalline grains with a height of ~1.4 nm, indicating a grain growth parallel to the substrate with a typical edge-on alignment.23 The same feature is observed in the F16CuPc thin films, but the grain edges of the CuPc single-layer thin-film are sharper than those of the F16CuPc. In addition, the RRMS value of the former (0.78 nm) is larger than that of the latter (0.52 nm), probably due to differences in packing density and crystallinity. The second layers of F16CuPc on CuPc (Figs. 2f and 2g) also exhibit caterpillar-like crystalline grains, while the RRMS values for the F16CuPc (1.5- and 3-ML) layers on CuPc are 1.10 and 1.09 nm, respectively. These values are comparable to those of the CuPc/F16CuPc double-layer thin films. It is concluded that the crystalline grains of F16CuPc and CuPc grow parallel to the substrate, reflecting their edge-on alignments, in either the top or bottom 6 ACS Paragon Plus Environment

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layers of double-layer thin films. This is consistent with the structures of these thin films, prepared at 375 K.24 The RRMS value of a single-layer thin film of CuPc is larger than that of F16CuPc, suggesting that the crystallinity of CuPc is slightly higher than that of F16CuPc, though this difference shrinks when they grow as the second layer on their counter compounds. To understand the formation processes of ambipolar channels in OFETs with DA heterostructures, we examined FET performance with an increase in the thickness of the second layer using a real-time in situ measurement system modified from a system reported earlier25-27 (see Fig. S1). The data were obtained at a constant source-drain voltage VDS of +30 V in the repeated scans of VG between +50 and −50 V. The time sequence of VG and the induced source-drain current ISD are shown in Fig. S2. Figure 3 displays the time dependence of the transfer characteristics of a CuPc/F16CuPc (3.8 ML) double-layer FET during the growth of the CuPc second layer. This figure also shows the time dependence of the thickness DCuPc of the second layer. In the time range t = 0~600 s, there is no growth of the CuPc layer on F16CuPc, so that the transfer characteristics simply exhibit n-type behavior of the F16CuPc single layer (see the plots in Fig. S3 at an enlarged scale). As soon as the deposition of the top layer starts at t = 600s, IDS in the positive-VG range immediately increases due to an enhancement of ntype electron transport and, from t = 1100 s, the enhancement of IDS becomes noticeable even in the negative-VG region (see also Fig. S4), indicating the generation of p-type hole transport. At t = 2300 s, the

IDS vs. VG plots exhibit a well-balanced V-shaped dependence (see also Fig. S5). From t = 2300 s, there 7 ACS Paragon Plus Environment


is no deposition of CuPc and IDS gradually decreases, probably due to a decrease in the sample temperature. We calculated the values of the field-effect electron mobility μe, the threshold voltage Vth, the turn-on voltage VON (see Fig. S6), and the ON-to-OFF ratio ION/IOFF for the CuPc/F16CuPc double-layer FETs at various DCuPc. These parameters are shown in Fig. 4a as a function of DCuPc. Before the deposition of CuPc (t < 600 s), the single-layer F16CuPc FET exhibits n-type transport with μe = 1.2 × 10−3 cm2/Vs, Vth = +12 V, VON = +2.6 V, and ION/IOFF = 5 × 103. As soon as CuPc is deposited on this F16CuPc layer, the values of μe and ION/IOFF increase drastically even in the range DCuPc < 1.0 ML, while VON and Vth exhibit no significant change. These initial enhancements in μe and ION/IOFF with nearly constant VON and Vth strongly indicate the filling of deep-trap states with carrier electrons, which are generated at the interface between F16CuPc and CuPc.28 In the range DCuPc > 1.0 ML, VON and Vth begin to show negative shifts under the continuous increases in μe and ION/IOFF. Since a change in Vth is proportional to a change in the carrier density, this behavior suggests an increase in the electron carrier density in the F16CuPc layer. In the range DCuPc > 2.4 ML (namely, t > 1100 s), the ambipolar transport appears in the transfer characteristics (see Fig. 3), and the values of ION/IOFF decrease suddenly by four orders of magnitude. We fit the data of |IDS| in the range from VG = −40 to −50 V to the equation |IDS| = A(VG−B), where A and B are the fitting parameters, and plotted the obtained values of |A| in Fig. S7. These plots indicate a significant enhancement of p-type transport at DCuPc > 2.4 ML, caused by the formation of p-channels 8 ACS Paragon Plus Environment

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in the CuPc layer. In the range 4 < DCuPc < 8.4 ML, Vth, μe, and ION/IOFF in Fig. 4a exhibit the successive changes, which can be explained by a continuous electron doping into the bottom layer. It is concluded that the growth of the CuPc layer on the F16CuPc layer immediately produces carrier electrons in the latter, which fill deep-trap states and enhance n-type transport, and forms the p-channels in the CuPc layer when DCuPc > 2.4 ML. Figure 5a shows the transfer characteristics for a CuPc(8.4 ML)/F16CuPc(3.8 ML) double-layer OFET at various VDS, measured in situ in the dark at room temperature. They confirm the ambipolar behavior of this transistor. The field-effect mobilities of hole and electron are calculated as 2.6 × 10−2 cm2/Vs and 1.4 × 10−2 cm2/Vs (see Table S1), respectively, from the linear regimes, and are indicated by the broken lines in Fig. 5a. The hole and electron mobilities are well balanced and comparable to those of the single-component FETs.19-20 Next, we switched the order of the top and bottom layers, resulting in an F16CuPc/CuPc(3.6 ML) double-layer FET, and performed the same measurements. Figure 6 displays the time dependence of the thickness of the top layer of F16CuPc, DF16CuPc, and the transfer characteristics, obtained at VDS = –30 V under the time sequences of VG and IDS shown in Fig. S8. Before the deposition of the F16CuPc top layer, namely t < 600 s, the single-layer CuPc shows a p-type transport, as shown in Fig. S9. After the deposition of F16CuPc from t = 600 s, IDS in the negative-VG range decreases immediately but then begins to increase from t = 1100 s. This behavior is completely different from the monotonical increase 9 ACS Paragon Plus Environment


in IDS for the CuPc/F16CuPc FET, shown in Fig. 3. From t = 1300 s, IDS in the positive-VG range exhibits a significant increase (see also Fig. S10), indicating the formation of n-channels in the F16CuPc top layer. At t = 2100 s, a typical V-shaped ambipolar characteristic is obtained (see also Fig. S11). In the range t > 2200 s, there is no deposition of F16CuPc, but IDS shows a slight decrease, probably due to sample cooling. Figure 4b shows the DF16CuPc dependence of the field-effect hole mobility μh, Vth, VON, and

ION/IOFF for the F16CuPc/CuPc double-layer FET. Before the deposition of F16CuPc, the single-layer CuPc FET is characterized by the parameters μh = 4.3 × 10−3 cm2/Vs, Vth = –10.3 V, VON = –2.5 V, and ION/IOFF = 2 × 104. In the range DF16CuPc < 2.3 ML, where the initial reduction of IDS takes place, the values of Vth and VON for the hole injection exhibit negative shifts, and those of μh and ION/IOFF show gradual decreases. These changes suggest that the deposited F16CuPc induces the carrier traps at the interface, which hinder the hole transport in the CuPc bottom layer. These initial effects of the second layer are completely different from those for the CuPc/F16CuPc FET, shown in Fig. 4a. In the range 2.3 < DF16CuPc < 2.6 ML, Vth and VON shift toward positive directions, though μh decreases continuously before beginning to increase in the range DF16CuPc > 2.6 ML. In the range DF16CuPc > 3.2 ML, ION/IOFF values decrease abruptly. We fit the data of |IDS| between VG = +40 and +50 V in Fig. 6 to the equation, |IDS| =

A(VG−B) and plotted the values of A in Fig. S12. These plots indicate a significant enhancement of ntype transport at DF16CuPc > 3.2 ML, caused by the formation of n-channels in the F16CuPc layer. In the 10 ACS Paragon Plus Environment

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range DF16CuPc > 3.2 ML, the values of μh and Vth show a continuous increase and a continuous positive shift, respectively. It is concluded that the growth of the F16CuPc layer on the CuPc layer induces the trap states in the latter before the injection of hole carriers. The n-channels in the F16CuPc layer are formed when DF16CuPc > 3.2 ML. Figure 5b shows the transfer characteristics for a F16CuPc(8.2 ML)/CuPc(3.6 ML) double-layer OFET at various VDS values, measured in situ in the dark at room temperature. They confirm the ambipolar behavior of this transistor. The field-effect mobilities of hole and electron are calculated as 3.2 × 10−3 cm2/Vs and 3.7 × 10−3 cm2/Vs, respectively (see Table S1). They are well balanced but are an order of magnitude smaller than those of the single-component FETs.19-20 They are also smaller than those of the CuPc/F16CuPc FET shown above. We described the effects of the growths of the second layers in the CuPc/F16CuPc and F16CuPc/CuPc double-layer FETs on their FET performance. Once the second layers grow thick enough, they exhibit well-balanced ambipolar transport properties, but there is a significant difference in the initial effects on the transport of the first layer. In the CuPc/F16CuPc FET, the initial deposition of CuPc on F16CuPc immediately produces carrier electrons in F16CuPc, which fill the trap states in, whereas in the F16CuPc/CuPc FET, F16CuPc induces trap states in CuPc. To confirm this difference, we estimated the numbers of trap states in these two FETs. With respect to the transfer characteristics, it is known that the trap density governs the curvature of the initial enhancement of IDS in the range between VON 11 ACS Paragon Plus Environment


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and Vth.29 Therefore, we extracted the subthreshold swing S, which is defined as

S =

VG ,  (log I DS )

(1)

from the transfer characteristics (see Fig. S13) of the CuPc/F16CuPc and F16CuPc/CuPc double-layer FETs with second layers of various thicknesses. We then calculated the maximum trap density Ntrap using the following equation,29

S = (kBT/e)(ln10)[1+e2Ntrap/Ci] ,

(2)

where kB is the Boltzmann constant, T is the temperature, e is the elementary charge, and Ci is the capacitance per unit area of the insulating layer. The obtained values of Ntrap are shown in Fig. 7 as a function of the thickness of the second layer. When there are no top layers, the values of Ntrap for the CuPc/F16CuPc and F16CuPc/CuPc FETs are 8.1 × 1012 and 2.5 × 1012 cm−2 eV−1, respectively, which correspond to those for the single-layer F16CuPc and CuPc FETs, respectively. These values are comparable to those for the other thin-film OFETs.21, 30 With an increase in the thickness of the second layer, Ntrap values for the CuPc/F16CuPc double-layer FET decrease to 3.5 × 1012 cm−2 eV−1 at DCuPc = 1.5 ML. In contrast, the F16CuPc/CuPc FET increase in Ntrap with an increase in the thickness of the second 12 ACS Paragon Plus Environment

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layer; Ntrap = 5.0 × 1012 cm−2 eV−1 at DF16CuPc = 2.5 ML. These analyses, based on the curvatures of IDS, are consistent with the conclusion inferred from the dependence of the carrier mobilities and threshold voltages. The other differences between the CuPc/F16CuPc and F16CuPc/CuPc FETs are in the channel formation process in the second layer and in the carrier mobilities. With an increase in the thickness of the second layer, the p- or n-type channel is formed in the CuPc/F16CuPc or F16CuPc/CuPc FET, when

DCuPc > 2.4 ML or DF16CuPc > 3.2 ML, respectively. This means that F16CuPc needs to be thicker than CuPc to make a carrier channel. The hole and electron mobilities of the CuPc/F16CuPc double-layer FET are each an order of magnitude higher than the corresponding ones of the F16CuPc/CuPc FET. As discussed in Fig. 2, the surfaces of CuPc are rougher than those of F16CuPc due to the higher crystallinity of the former. Therefore, it is considered that the CuPc/F16CuPc interface would be smoother than the F16CuPc/CuPc interface. The microscopic formation mechanism of the trap states at these interfaces is not clear, but it is possible that the smoother CuPc/F16CuPc interface would realize smoother carrier transport and higher mobilities in both layers.7 Another possibility is that the trap states arise from solid-state diffusion of molecules at the interfaces. The diffusion of F16CuPc into films of CuPc has been reported to be greater than that of CuPc into F16CuPc,23 so that F16CuPc would spoil the properties of CuPc more significantly. The other possibilities are (i) a larger disturbance to the HOMO band in highly crystalline CuPc from the interfaces than the LUMO band in F16CuPc, and (ii) Fermi-level pinning 13 ACS Paragon Plus Environment


at the LUMO of F16CuPc at the CuPc/F16CuPc interface and unpinning at the HOMO of CuPc at F16CuPc/CuPc, respectively.33

Conclusions We performed in situ real-time OFET measurements for the DA-heterostructure systems of CuPc and F16CuPc to examine the effects of the second layer on the carrier transport in the first layer and on the formation processes of ambipolar channels on double-layered OFETs. The present results indicate that the initial depositions of the top layers enhance the mobilities of the first layers due to the filling of trap states at the interfaces of F16CuPc/CuPc, and reduce the mobilities of the first layers due to the generation of trap states at the interfaces of CuPc/F16CuPc. With an increase in the thickness of the top layer, the ION/IOFF ratio rapidly decreases in the formation of the opposite channel. Although either F16CuPc/CuPc or CuPc/F16CuPc double-layer thin film can exhibit an ambipolar transport, the resulting hole and electron mobilities differ significantly between them. The morphological analysis using AFM suggests that smoother interfaces would be favorable for higher mobilities in both p- and n-channels. These findings should serve to deepen our understanding of the relationship between FET performance and the organic heterointerface, and assist in the interface engineering to realize high-performance ambipolar OFETs with DA heterostructures. 14 ACS Paragon Plus Environment

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Experimental Methods CuPc and F16CuPc (Tokyo Chemical Industry) were purified by thermal-gradient sublimation prior to mounting on homemade deposition cells. Thin films of these molecules were prepared after being degassed for ~4 hours by thermal depositions under high vacuum conditions (P < 1 × 10−4 Pa) on FET substrates with a bottom gate, bottom-contact-device architecture with SiO2 insulating layers (300 nm) thermally grown on highly doped n-Si substrates (gate electrodes), and comb-shaped Pt electrodes (width/length = 32 cm/5 μm). The first (bottom) layer was prepared without the FET operation, and then FET measurements were performed in situ by repeated scans of gate voltage during deposition of the second (top) layer, using a source-measure unit (R6245A; Advantest). The deposition rates of CuPc and F16CuPc were estimated to be 0.3–0.5 ML/min using a quartz-crystal microbalance. The temperature of the FET substrate was monitored using a K-type thermocouple attached directly to the FET substrate. During the deposition, the substrate temperature changed from 25℃ to 41℃ due to thermal irradiation from the deposition cells. The values of FET parameters were extracted from the transfer curves 31-32. The morphology was characterized ex situ for the thin films at room temperature by AFM (SPI 3800/SPA400; Seiko Instruments). The AFM images were obtained in dynamic-force mode using a Si tip under ambient conditions. 15 ACS Paragon Plus Environment


Acknowledgments This study was supported by Japan Society for the Promotion of Science (JSPS) KAKENHI Grants (nos. JP15J11122 and JP16H06353) and by the JSPS Core-to-Core Program (A. Advanced Research Networks).

Associated Content Supporting Information. The Supporting Information is available free of charge on the ACS Publications website.

Schematic of a real-time in situ measurement system (Fig. S1); Time sequence of VG and the corresponding change in IDS for the CuPc/F16CuPc FET (Fig. S2); Transfer curves of the CuPc/F16CuPc FET measured at t = ~600 s (Fig. S3), ~1100 s (Fig. S4) and ~2200 s (Fig. S5); Extraction of Vth and VON from the experimental data (Fig. S6); Thickness dependence of the slop for the CuPc/F16CuPc FET (Fig. S7); Time sequence of VG and the corresponding change in IDS for the F16CuPc/CuPc FET (Fig. S8); Transfer curves of the F16CuPc/CuPc FET measured at t = ~600 s (Fig. S9), ~1300 s (Fig. S10) and ~2100 s (Fig. S11); Thickness dependence of the slop for the F16CuPc/CuPc FET (Fig. S12); Extraction and obtained values of S by fitting analysis 16 ACS Paragon Plus Environment

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(Fig. S13); Field-effect mobilities of hole and electron in the CuPc/F16CuPc and F16CuPc/CuPc FETs (Table S1).

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Figure 1. (a) Molecular structures of CuPc and F16CuPc. (b) Organic heterojunction FETs with bottom-gate bottom-contact structures.


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Figure 2. AFM images of (a) F16CuPc (3.8 ML), (b) CuPc (1.5 ML)/F16CuPc (3.8 ML), (c) CuPc (3 ML)/F16CuPc (3.8 ML), (e) CuPc (3.6 ML), (f) F16CuPc (1.5 ML)/CuPc (3.6 ML), and (g) F16CuPc (3 ML)/CuPc (3.6 ML). (d, f) Cross-sectional profiles of the dashed lines shown in panels (a)-(c) and (e)(g).



Figure 3. Time trajectory of the transfer characteristics of the CuPc/F16CuPc (3.8 ML) OFET during the deposition of CuPc. The top left panel shows the time dependence of the thickness of the CuPc layer

DCuPc.


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Figure 4. The second-layer-thickness dependence of the field-effect electron/hole mobility μe/μh, the threshold voltage Vth, the turn-on voltage VON, and the ON-to-OFF ratio ION/IOFF for the CuPc/F16CuPc (3.8 ML) (a) and F16CuPc/CuPc (3.6 ML) (b) OFETs. These data are extracted from their transfer characteristics, shown in Figs. 3 and 6.



Figure 5. Transfer characteristics in the CuPc/F16CuPc (3.8 ML) (a) and F16CuPc/CuPc (3.6 ML) (b) OFETs, measured at different drain voltages at room temperature. The broken lines were used to calculate the field-effect mobilities.


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Figure 6. Time trajectory of the transfer characteristics of the F16CuPc/CuPc (3.6 ML) OFET during the deposition of F16CuPc. Top left panel shows the time dependence of the thickness of the F16CuPc layer

DF16CuPc.



Figure 7. Top-layer-thickness dependence of the maximum trap densities for the CuPc/F16CuPc (3.8 ML) and F16CuPc/CuPc (3.6 ML) FETs. The blue and red experimental error bars are common to the plots for the CuPc/F16CuPc and F16CuPc/CuPc devices, respectively.


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