backscattering event in the immediate vicinity of the TaTa205interface. Representative values used for the stopping cross-section t, the backscattering energy loss parameter [SI,and the relative yield y for Ta2O5 on T a are given in Table 11.
ACKNOWLEDGMENT The authors thank W. Worobey for supplying six samples (measurements of these samples are plotted as x in
Figure 2), and H. Muller for participating in some of the measurements. We thank R. K. Lewis for providing a cross-check SIMS analysis on two of the Ta205 samples. RECEIVED for review April 18, 1974. Accepted August 12,
1974. Work supported at Caltech by the Office of Naval Research (L. Cooper) and at the University of Illinois by the National Science Foundation (Grants G P 33273 and GH 33634).
Inexpensive Digital Correlator for Spectrophotometric and Other Analytical Measurements T. A. Woodruff and H. V. Malmstadt’ School of Chemical Sciences, University of Illinois, Urbana, Ill. 6 180 1
A digital instrument is described which performs the basic data correlations required in double beam spectrophotometers and similar ratiometric analytical systems. It is designed to economically replace the presently-used analog circuitry, and offers an absolute accuracy equivalent to 0.002 YO transmittance, selectable 0.02 to 100 Hertz measurement rate, complete freedom from drift, great ease of Operation, remote programmability, automatic background correction, and automatic referencing of 0 and 100 % transmittance. It digltally integrates transducer information encoded as pulses by event-counting techniques or chargeto-count converters, and Is ideally suited for use with instruments using double-beam-in-time and/or double-beam-inspace techniques. It is constructed from three types of basic dlgital building blocks, counters, latches, and rate multipliers, which are controlled by a simple sequencer. The correlator illustrates fundamental principles of wide applicability in analytical instrumentation.
An inexpensive digital correlator is described for the replacement of analog circuitry that is presently used in double beam spectrophotometers and similar ratiometric instruments. Commercial spectrophotometers which have been introduced in recent years have almost universally incorporated the convenience of a digital readout. Often, however, the instruments are not truly “digital.” In most cases, a small digital panel meter is added to the conventional analog data correlation circuitry. Scale reading errors are thus reduced, and in some cases convenient data logging can be performed, but several limitations of the analog circuitry are still present. These limitations include signal degradation which is often caused by certain analog stages because of noise, inaccuracy, and drift. Analog signal processing is particularly troublesome when very high accuracy is required from double beam spectrophotometers and other ratiometric instruments. In addition, doublebeam-in-time systems require rather complicated sampleand-hold systems or tuned ac amplifiers/demodulators to recover the time-multiplexed information. Instruments employing analog data correlation are also often difficult to program by remote digital signals when this is required for use in automated systems. Send request for reprints to this author.
Two minicomputer-controlled spectrophotometers have recently been described ( I , 2 ) , one of which uses photon counting and eliminates the problems of analog signal processing. These instruments offer great flexibility, but for many routine analytical measurements they are not necessary. The computer and its peripherals are still moderately expensive, and a significant amount of operator training is required for the setup and operation of such a system. The computer and peripherals are also sufficiently complex to require professional maintenance and repairs. The inexpensive digital correlator described in this paper, however, is conceptually more simple than many analog systems and does not require any calibrations or adjustments of any sort. I t provides simple instrumental operation when included as part of a spectrophotometer. For example, with manual operation, two pushbuttons are the only basic operating controls necessary. With the sample and reference beams blocked, the “background cycle” button is pressed momentarily to store the background information, which is then available for subtraction from subsequent measurements to reference 0% transmittance. Cells containing solvent are then placed in the sample and reference beams and the “reference cycle” button is pushed. The background-corrected sample-to-reference channel ratio is computed and stored for automatic utilization in all subsequent measurements. Samples containing the absorbing species may then be placed in the spectrophotometer, and digital transmittance readings which are automatically corrected for background and cell transmission differences are displayed and typed out. For completely automatic operation, the above functional switches are programmed to operate automatically in relation to the cell status for calibration or sample measurements. A switch is provided for the selection of measurement integration time or repetition rate, which might typically be 0.5 second ( 2 Hz) to 2 seconds (0.5 Hz) for manual measurements. Other measurement rates from 0.02 to 100 Hz are also available so that the instrument may be used in high speed automated analyzers. The digital correlator has a basic absolute accuracy equivalent to 0.002% transmittance. A minor circuit modification permits the measurement rate to be increased to faster than 1 KHz through reduction of the instrument res(1) R. B. Timmer and H. V. Malmstadt, Amer. Lab., 4 (9), 43 (1972). (2) U. B. Ranalder, H. Kanzig, and U. P. Wild, Appl. Spectrosc., 28 ( I ) , 45 (1974).
ANALYTICAL CHEMISTRY, VOL. 4 6 , NO. 1 4 , DECEMBER 1974
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olution from 16 to 12 bits. All of the digital correlator functions are readily programmed by external signals, including the measurement integration time. The correlator digitally integrates transducer information encoded as pulses by photon counting techniques ( 3 ) or charge-to-count converters ( 4 ) . Using these pulse encoding techniques eliminates or minimizes analog signal processing. The digital integration may also be interrupted many times during a total measurement cycle, or extended for long periods, without causing error. The correlator is thus readily used for the decoding of time-multiplexed information, and the same instrument may be used for double-beam-in-time and/or double-beam-in-space techniques. With minor modifications, the instrument could be advantageously applied to various single-beam techniques, to chopped source atomic absorption work, etc. The easily controllable integration period of the digital correlator makes it very well suited for use with the increasingly important pulsed light sources for spect,roscopy. BASIC PRINCIPLES An ideal absorption spectrophotometric measurement of the transmittance T of a sample would result if the transmitted radiation information for sample and reference could be accurately obtained simultaneously, using the identical radiation beam in a single channel, and with the identical sample holder for sample and reference. This, of course, is impossible but many double and multiple beam systems have been devised (5-9) that attempt to approximate the ideal measurement. Regardless of the technique used, some type of normalization is generally required so as to correct for differences in sample and reference cells, geometry and intensity of sample and reference beams, and detector characteristics for the two beams separated in space orland in time. Also, background must often be corrected for. In this section, these factors are considered and the general methods are presented which show how the correlator collects, stores, and utilizes these factors so as to provide an accurate measurement of T . If the sample channel count integrated over a measurement period, proportional to the light intensity, is symbolized as S, and the reference channel count as R, with a zero subscript ( S O ,Ro) used to indicate the initial reference conditions in which the sample cell as well as the reference cell contain solvent only, we want
This may be achieved by multiplying by the factor R o / S o :
When subsequent measurements are made with an absorbing species in the sample cell, the ratio SIR0 is multiplied by the stored normalization factor, Ro/So:
(3) H. V. Malmstadt. M. L. Franklin, and G. Horlick. Anal. Chem., 44 (8), 63A (1972). (4) T. A. Woodruff and H. V. Malmstadt, Anal. Chem., 46, 1162 (1974). (5) C. D. Scotland C. A. Burtis, Anal. Chem., 45, 327A (1973). (6) J. E. Stewart, Amer. Lab., 5 (3), 51 (1973). (7) P. F. Loft, J. Chem. Educ., 45 (3), A169 (1968). (8) J. W. Strojek, G. A. Gruver. and T. Kuwanna, Anal, Chem., 41, 481 (1969). \ , (9) E. Chance, N. Graham, J. Sorge, and V. Legallais, Rev. Sci. lnstrurn., 43 ( l ) , 62 (1972).
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Thus, the ratio of the intensity with sample in the cell to the intensity with pure solvent in the cell is obtained. If the light source intensity varies during measurements after the ratio RolSo has been obtained and stored, and if the two information channels are equally affected by the factor k , then the transmittance calculation will be:
Thus, the factor k cancels as desired. It is usually necessary to reference Ooh T as well as 100% T . The sample (and reference) channels will typically have some effective intensity, perhaps only because of the nonideal characteristics of the light-to-electrical domain transducers, even when the light paths are blocked. For an analog system, another reason for having to reference 0% T is to cancel circuit offset drift. Neglecting to correct for background in the sample channel can came gross errors, especially at low transmittances where the background may become comparable to the intensity of the desired light signal. Consequently, it is common practice in analog spectrophotometers to replace the sample cell by an opaque block and manually set 0% T on the readout. If the sample-channe1 intensity corrected for background is S * = S - s b , where S b is the sample channel background, the transmittance calculation becomes: S* R0- S* - - = T Ro So* So* While this procedure eliminates gross error at low transmittances, the background contribution in the reference channel, R b, can also contribute to error. When the source intensity varies, the factor k is not completely cancelled if the reference channel is not corrected for background. Thus, when R o = R O* R b and k deviates from unity,
+
It is thus desirable to correct for background in both channels, and the calculation becomes:
(E)($) s',** =
= T
The digital correlator described here performs automatic background correction for both the sample and reference channels and then uses the corrected values in the calculation of the normalizing factor Ro*/So*, and final calculation of the normalized, corrected transmittance. Mathematical Operations Performed. The first operation which the correlator must perform is to determine and store the average background values for the sample and reference channels, s b and b. These values are to be subtracted from all subsequent measurements of the reference and sample channel counts. During the instrument reference cycle, the ratio of the corrected reference counts ( R0 - R b ) to corrected sample counts ( S 0 - S b), i.e., ( Ro - Rb)/(SO - S b ) , must be calculated and stored so that it may be used for normalization of subsequent measurements to 100% T . In these subsequent normal cycle measurements, the ratio of corrected sample to corrected reference counts must be found and multiplied by the above normalizing factor to yield:
Thus, subtraction, multiplication, and division are necessary. Building Blocks Used for Performing Operations. The digital correlator is built from three types of basic digi-
A N A L Y T I C A L C H E M I S T R Y , V O L . 46, N O . 1 4 , DECEMBER 1 9 7 4
tal building blocks. These are counters, latches for storing digital information, and rate multipliers. The counters are used for performing summations or integration with respect to time. With an up/down (U/D) counter, the average values over successive integration periods may be subtracted from each other. For example, if it is desired to subtract a background value, the U/D counter is cleared a t the beginning of a measurement period and counts down as the negative of the background .information is accumulated in 2's complement form (in the case of binary counters). At the end of the integration period, the number is stored in a latch. During subsequent and equally long measurement intervals, the counter is initially loaded from the latch with the 2's complement of the background information, and the counter counts up from negative values through zero to reach the desired corrected value at the end of the measurement period. The rate multiplier ( I O ) operates as a speical type of counter which contains internal gating. It allows through to its frequency output only a controlled fraction of the clock pulses applied. The logic levels at the rate multiplier rate inputs determine the number of pulses passed. The device provides a multiplication function since the fraction of pulses passed is directly proportional to the number at the rate inputs. Rate multipliers (RMs) accept either straight binary coded numbers (BRMs) or binary coded decimal (DRMs) a t the rate inputs. Operation of Building Block Combinations. The combination of latches and counters for background subtraction was described in the previous section, as was the multiplication function of rate multipliers. Division is accomplished by making use of the fact that the time A t required for a counter to count down from an initial value n to zero, bears a reciprocal relationship to the counter input frequency f :
If f is the output from a binary rate multiplier with an input clock frequency of F , and a control input m, f
)?I F = ---c
2'
where 1 is the number of bits in the rate multiplier, and At =
122
111F,
During time At, F , is also gated to an initially cleared up counter, so that the count c in the up counter when the down counter reaches zero and the gate is closed is:
Thus c is the ratio of n to m, scaled by a binary factor. If decade counters and rate multipliers were used instead of binary units, the ratio would be scaled by a power of ten. Correlator Operation. The building blocks described are combined to perform the desired digital correlator operations, as shown in Figure 1. In addition, a simple control and sequencing circuit is used to, for example, load the latches at the appropriate times and have the counters count up or down. However, the details of this circuit are not important to an understanding of the basic correlator operation, except for the parts of the control circuit which are included in Figure 1 as I/*-sizeblocks. For this initial discussion, a double-beam-in-space sys-
BACKGPOUND -ATC3
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Figure 1. Correlator basic block diagram
tem will be assumed so that two channels of data are simultaneously accumulated. Referring to Figure 1, the sample and reference channel frequencies are supplied to the sample and reference U/D counters C1 and C 2 , respectively. In the first cycle of correlator operation, the background cycle, the sequencer causes the counters to be cleared at the beginning of a measurement period, and then to count down during the desired integration time. At the end of the integration time, the counts - s b and - R b are stored in the background sample and reference latches L1 and L2, respectively. At the beginning of the reference cycle, and for every subsequent measurement (until new background data are obtained), the data from these latches are loaded back into the sample and reference counters at the beginning of each measurement period. For the reference and normal integration periods, the sample and reference U/D counters count up and the background counts are subtracted out. At the end of a reference or normal cycle, the corrected sample and reference counts, So* (or S * ) and Ro* are loaded into down counter C3 and latch L3, respectively. A new measurement cycle begins immediately as new background information is loaded into the U/D counters. While this next measurement period is proceeding, the calculations for the previous measurement period are completed. For the reference cycle, a 7-MHz clock frequency F , is applied to the clock input of rate multiplier R M l (through multiplexer M l ) . The rate input for R M l is the data stored in latch L3 from the reference U/D counter. The RM output frequency is then
(10) "The TTL Data Book for Design Engineers", 1st ed., Texas Instruments, Dallas, Texas, 1973, p 248.
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I
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14 M H L CLOCK 14 M Y 1 C R Y S T I L
and the output from RM1 will be: (RM2 output freq. ) R M 1 rate input 216
-
FcSo* 216
The time required for down counter C3 to count down will be: s*216 S* - At = C3 input freq. - So*Fc
MODULO 14 SCALER ~
The count in the binary up counter C4 will be: s*216
count = FcAt = SO * This is the desired binary transmittance value. The same counts applied to the binary up counter C4 are also applied through a scaling rate multiplier RM3 to a decade up counter C5. The configuration of RM3 and counter C5 results in an effective multiplication by 1O5/2I6. Thus, the count available in the decade counter block after it has ceased counting is:
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Figure 2. Instrument time base
The rate multiplier output is used to clock down counter C3, which initially contains the corrected sample count SO*.The down counter proceeds to count down, starting a t the end of the old measurement period (and start of the new one), until it reaches zero and its borrow flag goes low. The time required, At, will be: AI =
SO*
C3 input freq.
-
so*216 Ro*Fc
The borrow flag signal is used to gate ( G l ) the 7-MHz clock frequency into an initially cleared binary up counter C4, and thus the count in C4 after the borrow flag goes low will be: * 216 count = F , A ~ =
RO *
The corrected sampleheference ratio obtained during the reference cycle is stored in latch block L4 from binary counter C4. For each subsequent normal cycle, instead of applying the 7-MHz clock directly to RM1, the clock is first applied to the input of rate multiplier RM2, which has as its rate input the ratio stored in L4. The output from RM2 is selected by multiplexer M1 as the clock for RM1. Then, during the normal cycle, the output from RM2 will be: F,(rate input) - F A * 216 RO* 2144
count = SO * This count is loaded into latch block L5, which provides the correlator BCD output. Proper placement of the decimal point in the readout provides a reading in % T . The rate multiplier scaling block RM3 and the decade counter block C5 could be eliminated if only a binary output was required, for use with further correlator stages, or if the system were built entirely of decade, rather than binary, counters and rate multipliers. The approach shown was chosen because it resulted in a net savings over a decade system in the number of integrated circuits required for the instrument and their cost. Furthermore, the binary output will be used as the capabilities of the correlator are expanded. The circuitry making up the digital correlator is discussed in the following order: the basic control and sequencing circuit, followed by the gating used between the sequencer and the system building blocks (which will include a more complete indication of the inputs and outputs of these blocks), and finally, the circuits of the building blocks will be given. Control and Sequencing Circuit. Time Base. The schematic diagram of the instrument time base is shown in Figure 2. Three gates, a crystal, and a resistor form a crystal-controlled 14-MHz T T L oscillator. A 4-bit binary counter and a three-input gate are connected to form a modulo14 divider which generates 1 MHz from the 14-MHz oscillator signal. The first stage of this counter divides by two and thus produces a 7-MHz frequency; this is used as the system clock F , mentioned in the basic principles section. The 1-MHz frequency is applied to the inputs of divideby-2 and divide-by-5 counters; either counter output, or the original 1 MHz, is selected by a multiplexer controlled by a front panel switch or by programming logic signals. The 0 3 , 0.5-, or 1-MHz output is further divided by lo4, 105, 106, or lo7 by a MOS IC. This division is again controlled by the front panel switch or remote programming. The output from this stage is the 100-Hz to 0.02-Hz instrument measurement rate time base. An external signal could alternatively be used here to set the measurement rate and integration time. Intermittent Operation Generator. Some of the operations of the instrument building blocks are intermittent in character. For example, the loading of latches or clearing of counters requires a pulse lasting only a few tens or hun-
ANALYTICAL CHEMISTRY, VOL. 46, NO. 14, DECEMBER 1974
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dreds of nanoseconds. In contrast, for example, the signal controlling whether a counter is to count up or down is required to be present for an entire measurement integration period. Pulses for the production of the system intermittent operations are required a t the end of each measurement integration period and immediate start of the next, and a t the completion of the transmittance calculation period, The pulses are generated by the circuit shown in Figure 3. The measurement frequency time base is applied to the clock input of monostable MS1. The falling edge of the time base signal represents the end (and beginning) of each measurement cycle, so this monostable and the other monostables and flip-flops used in the sequencer are negativeedge triggered. When clocked, MS1 produces a t its Q output a nominally 250-nsec logic 1 pulse P1; the Q output gives a logic 0 pulse NP1. The completion of P1 triggers MS2 to produce pulse NP2, which is inverted through a gate to produce 50-nsec pulse P2. The start of these pulses is separated from the completion of P1 by the propagation delay of MS2. Thus, a t the end of each measurement period, two sets of pulses separated by a significant interval are produced. This enables one set of intermittant operations to be performed, a period allowed to ensure the completion of these first operations. and then a second set to be performed. An additional monostable, MS3, is clocked from the measurement time base and produces 320-nsec pulses P 3 and N P 3 which have a duration equal to that of P1 and P2 combined, so that some system operations (such as clocking of the U/D counters) may be inhibited while the operations activated by P1 or P2 are performed. The end of the transmittance calculation period is signaled by the down counter borrow flag going low when the counter borrows, as discussed in the basic principles section. This borrow flag signal clocks monostable MS4 to produce 320-nsec pulses P4 and NP4. M e a s u r e m e n t Cycle Controller. As mentioned in the preceding section, some of the operations performed by the blocks of the digital correlator require control signals lasting for an entire measurement integration period. In particular, the operations required during a cycle depend upon whether a background, reference, or normal cycle is under way. The circuit given in Figure 4 is activated to initiate a background or reference cycle, provides the appropriate logic levels to the system building blocks (in conjunction
L__i HI
Figure 4. Cycle controller
with the intermittant operation generator in the case of intermittant operations dependent upon what type of cycle is being executed), and reverts to its normal state after the background or reference cycle has been completed. When it is desired to initiate a background cycle, flipflop FF1 is set by momentarily depressing a front panel switch or, for programming, applying a logic low pulse to the set input. The Q output of FF1, named QBACK, goes to a logic 1, and the 8 output, NQBACK, goes to a logic 0. A front panel light, LED1, is activated through gate G1 when NQBACK goes low and indicates visually when a background cycle is in progress. QBACK remains high for one complete measurement period. A reference cycle is initiated by setting flip-flop FF2, with outputs $REF and NQREF, and a front panel indication of this state is provided via LED2. QREF remains high for one complete integration period, plus the time required for the calculation of' the corrected sample to reference ratio. FF1 and FF2 are prevented from returning prematurely to their quiescent states by keeping their K inputs low for one period; this is performed by FF3. FF4 is used to additionally ensure that FF2 is clocked back to its normal state only after the sampleheference ratio is obtained, and P4 occurs. Sequencer-Operation Block Interface. The connections between the control and sequencing circuity discussed in the previous section, and the system's major blocks, are given in Figures 5 , 6, and 7' . Also shown are five gates which complete the interface between the controller and the blocks. These figures show the control inputs of the blocks in addition to the clock inputs and flag and frequency outputs already shown in the basic system block diagram, Figure 1. The multibit parallel data connections between blocks already given in Figure l are not repeated. Functional Block Circuits. The schematic for the 4 binary counter blocks used in the digital correlator is given in Figure 8. For the sample and reference up/down counters, a
A N A L Y T I C A L C H E M I S T R Y , VOL. 46, NO. 1 4 , D E C E M B E R 1 9 7 4
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synchronizing circuit using 2 D flip-flops was employed to be able to turn the counters on and off, or change the count direction, without producing counting glitches. This circuit was not included for the up and down binary counters; the clock was fed directly into the up or down input of the least significant counter, with the other input held a t a logic 1. Similarly, the borrow detection latch activated from the borrow output of the most significant counter was used only for the down counter. If it is desired t o use the binary transmittance output of the correlator, another latch, or a flip-flop, should be included a t the carry output of the binary up counter. This provides a seventeenth bit of data necessary to indicate transmittance greater than 100%. Where the load or clear capability of a counter was not needed, the respective input was held a t the inactive logic state indicated in Figure 8. The schematic for the decade counter block, which produces the correlator BCD output, is given in Figure 9. The binary computation circuits of the correlator employ 16 2146
*
bits, equivalent to 65,536 counts, and for the transmittance readout it is necessary to scale this to 100,000% T. This is accomplished by using a divide-by-5 counter in the first decade of the counter block, followed by four decade counters, and a divide-by-2 stage for the most significant digit. Then, 50,000 counts gives an output reading of 100,000, The scaling down from 216 counts to 50,000 is performed with a rate multiplier, as described in the next paragraph. An alternative to the use of a modulo-5 counter for the least significant digit would have been to gate the 14-MHz oscillator frequency, instead of 7-MHz, into the scaling BRM. A modulo-10 counter could then be used. The BRM could have been eliminated if an additional oscillator, of the appropriate frequency, were included so that its output could be gated directly into the BCD counters. The circuit used for scaling 2 l 6 counts down to 50,000 for the decade readout stage consists of 2 6-bit binary rate multiplier IC's which are cascaded to form a 12-bit rate multiplier (Figure 10). The scaling from 216 to 50,000 requires a multiplication by 5,000/216 which reduces to S5/2l2. This can be written as (211 21° 25 24 22 2O)/2I2, or (0.110000110101)base 2, and multiplication by this factor is achieved by applying this sequence of logic ones 2nd zeros to the most through least significant bits of the rate multiplier, as shown in Figure 10. This and the other rate multiplier blocks used in the correlator are cleared a t the beginning of each measurement cycle so that the internal counters will be a t the same state at the beginning of each cycle; this aids calculation precision. The circuit for the two 16-bit BRM blocks used in the correlator is given in Figure 11. A three-input NAND gate is used to cascade three 6-bit RMs to form an 18-bit RM; the least significant 2 bits are not used and are grounded. Each latch block used in the correlator consists of four or five 7475 4-bit latch IC's, with all clock inputs tied together. This common clock line is buffered by one 7437 NAND buffer gate for the 16-bit binary latch blocks or two gates with outputs tied together for the 20-bit decade latch block. The gate inputs for each block are all tied together; a logic 0 a t the gate inputs loads the latches. A few provisions were included in the correlator design to aid in testing, but which have no effect on normal opera-
ANALYTICAL CHEMISTRY, VOL. 46, NO. 14, DECEMBER 1974
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