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Interface Defect Hydrogen Depassivation and Capacitance−Voltage Hysteresis of Al2O3/InGaAs Gate Stacks Kechao Tang,† Felix Roberto Palumbo,§,# Liangliang Zhang,‡ Ravi Droopad,∥ and Paul C. McIntyre*,† †
Department of Materials Science and Engineering and ‡Department of Electrical Engineering, Stanford University, Stanford, California 94305, United States § National Scientific and Technical Research Council, CONICET/GAIANN-CNEA, Buenos Aires, Argentina # National Technological University, Buenos Aires, Argentina ∥ Ingram School of Engineering, Texas State University, San Marcos, Texas 78666, United States S Supporting Information *
ABSTRACT: We investigate the effects of pre- and postatomic layer deposition (ALD) defect passivation with hydrogen on the trap density and reliability of Al2O3/InGaAs gate stacks. Reliability is characterized by capacitance−voltage hysteresis measurements on samples prepared using different fabrication procedures and having different initial trap densities. Despite its beneficial capability to passivate both interface and border traps, a final forming gas (H2/N2) anneal (FGA) step is correlated with a significant hysteresis. This appears to be caused by hydrogen depassivation of defects in the gate stack under bias stress, supported by the observed bias stress-induced increase of interface trap density, and strong hydrogen isotope effects on the measured hysteresis. On the other hand, intentional air exposure of the InGaAs surface prior to Al2O3 ALD increases the initial interface trap density (Dit) but considerably lowers the hysteresis. KEYWORDS: InGaAs, Al2O3, MOSCAP, reliability, interface traps, border traps, hydrogen depassivation hysteresis as well as flat band voltage (Vfb) shift under bias stress.16,20,21 Moreover, Al2O3/InGaAs MOSFETs exhibit positive bias temperature instability (PBTI) that is significantly greater than in Si devices and a clear bias-induced degradation of transconductance and subthreshold swing.22−24 Bias stressinduced instability has been attributed to charge trapping at pre-existing and stress-generated defects in the oxide layer. In other publications, poor reliability was either ascribed to the charge traps at the oxide−channel interface20,21 or assumed to be associated with border traps in the high-k dielectric layer.16,22,23 There have been few studies of the effects of different device fabrication and treatment procedures on the reliability of Al2O3/InGaAs gate stacks. It is also important to elucidate the relationship between bias-induced stability and charge traps in the gate stacks, including the roles of interface traps and border
1. INTRODUCTION For future high performance III−V n-MOS devices, In0.53Ga0.47As is a promising channel material due to its high electron mobility.1−3 Atomic layer deposited (ALD) Al2O3 has a large conduction band offset and can form a low defectdensity interface with InGaAs.4,5 Therefore, Al2O3 has received attention as either a candidate dielectric layer for InGaAs nMOSFETs6,7 or a large band-offset interface layer interposed between the InGaAs channel and a higher-k dielectric such as HfO2.8,9 Over the past decade, much progress has been made in the passivation of charge trapping defects in the Al2O3/InGaAs gate stacks, including traps at the oxide/III−V interface10−13 and border traps in the dielectric layer itself.14−16 High electron mobility (∼3000 cm2/(V s)), low interface trap density (Dit < 3 × 1011 cm−2 eV−1), and good subthreshold swing (SS ∼ 75 mV/dec) have been demonstrated by several groups using InGaAs channel devices with Al2O3 gate oxide.17−19 For the fabrication of high performance III−V channel devices, however, reliability has been an emerging issue in recent years. Al2O3/InGaAs MOS capacitors display notable C−V © 2017 American Chemical Society
Received: December 18, 2016 Accepted: February 2, 2017 Published: February 2, 2017 7819
DOI: 10.1021/acsami.6b16232 ACS Appl. Mater. Interfaces 2017, 9, 7819−7825
Research Article
ACS Applied Materials & Interfaces traps, respectively. In this work, we fabricate Al2O3/InGaAs MOS capacitors with different procedures and quantify the trap density, including Dit and Nbt, of each set of devices. Measurements of C−V hysteresis, an important indicator of device reliability, were performed under different bias stress conditions. For device fabrication procedures that significantly impacted hysteresis, follow-up experiments were also performed to test the underlying mechanisms.
2. MATERIALS AND METHODS Epitaxial n-type In0.53Ga0.47As (100) substrates doped with Si (1 × 1017 cm−3) (epilayers deposited on lattice-matched n-InP (100) wafers) were coated with ∼200 nm thick amorphous As2 cap layers during postgrowth cooling in the InGaAs molecular beam epitaxy chamber. The As2 capping protects the InGaAs surface from oxidation and contamination during air exposure before the substrates are loaded into the ALD chamber.25 Prior to the initiation of Al2O3 ALD, the As2 capping was thermally desorbed at 350 °C in the ALD chamber at a pressure of 10−6 Torr. A reference sample was made with a standard ALD procedure: immediately following the As2 decapping, ∼4.5 nm of Al2O3 was deposited using 60 cycles of alternating trimethylaluminum (TMA) and H2O pulses at a substrate temperature of 270 °C. The estimated doses per cycles were 900 and 1200 L for TMA and H2O, respectively, and the chamber pressure was maintained at 0.68 Torr by continuous flow of dry N2. Samples with intentionally modified trap densities were prepared by first exposing the InGaAs substrate surface to room temperature lab air in the light for 5 days after As2 decapping and then reloading them into the ALD chamber for the same 60 cycles of Al2O3 ALD. After Al2O3 deposition for both the reference and test samples, 40 nm thick circular (50−125 μm radius) Pd top electrodes and 100 nm thick Al back contacts were deposited by thermal evaporation.25 Further details of the experimental methods can be found in ref 25. A subset of the Pd/Al2O3/InGaAs MOS capacitor samples prepared with both types of decapping conditions were treated with forming gas (5% H2/95% N2) for 30 min at 400 °C, thus generating four types of samples with different fabrication procedures. To check the surface chemistry of the InGaAs prepared with different procedures, X-ray photoelectron spectroscopy (XPS) was performed using a PHI VersaProbe scanning XPS microprobe with Al Kα radiation (1486 eV). These Al2O3/InGaAs stacks for XPS measurement were made with a very thin (∼1 nm) Al2O3 layer to improve the sensitivity to photoelectrons emitted from the Al2O3/InGaAs interface region. Multifrequency C−V curves were measured in the 1 kHz−1 MHz frequency range at room temperature in the dark, using a HP4284A LCR meter. The trap density are quantitatively analyzed by a full interface state model26 and a border trap model27 through the fitting of C−V and conductance−voltage (G−V) data. To characterize the reliability of the devices, consecutive C−V hysteresis measurements were employed. Starting at a fixed voltage point in inversion, the gate voltage was swept up to a certain voltage in accumulation (Vacc) at a rate of 0.5 V/s. The voltage was held at Vacc for 1 s and then ramped down to the starting point in inversion at the same sweeping rate. The hysteresis was measured as the difference between the flat band voltage (Vfb) for the ramping up versus the ramping down curve. Vfb was estimated by the recently introduced inflection point technique.28 The inflection point technique is useful in quantifying the Vfb based on C− V data of arbitrary ac frequencies and is confirmed to produce very similar results (
