Investigations on Substrate Temperature-Induced Growth Modes of

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Investigations on Substrate Temperature-Induced Growth Modes of Organic Semiconductors at Dielectric/semiconductor Interface and Their Correlation with Threshold Voltage Stability in Organic FieldEffect Transistors Narayanan Padma,*,† Priya Maheshwari,‡ Debarati Bhattacharya,§ Raj B. Tokas,∥ Shashwati Sen,† Yoshihide Honda,⊥ Saibal Basu,§ Pradeep Kumar Pujari,‡ and T. V. Chandrasekhar Rao† †

Technical Physics Division, ‡Radiochemistry Division, §Solid State Physics Division, and ∥Atomic and Molecular Physics Division, Bhabha Atomic Research Centre, Mumbai, India ⊥ The Institute of Scientific and Industrial Research, Osaka University, Ibaraki, Osaka, Japan S Supporting Information *

ABSTRACT: Influence of substrate temperature on growth modes of copper phthalocyanine (CuPc) thin films at the dielectric/ semiconductor interface in organic field effect transistors (OFETs) is investigated. Atomic force microscopy (AFM) imaging at the interface reveals a change from ‘layer+island’ to “island” growth mode with increasing substrate temperatures, further confirmed by probing the buried interfaces using X-ray reflectivity (XRR) and positron annihilation spectroscopic (PAS) techniques. PAS depth profiling provides insight into the details of molecular ordering while positron lifetime measurements reveal the difference in packing modes of CuPc molecules at the interface. XRR measurements show systematic increase in interface width and electron density correlating well with the change from layer + island to coalesced huge 3D islands at higher substrate temperatures. Study demonstrates the usefulness of XRR and PAS techniques to study growth modes at buried interfaces and reveals the influence of growth modes of semiconductor at the interface on hole and electron trap concentrations individually, thereby affecting hysteresis and threshold voltage stability. Minimum hole trapping is correlated to near layer by layer formation close to the interface at 100 °C and maximum to the island formation with large voids between the grains at 225 °C. KEYWORDS: OFET, substrate temperature, growth mode of CuPc, threshold voltage stability, positron annihilation spectroscopy, X ray reflectivity

1. INTRODUCTION Organic field effect transistors (OFETs) have been providing viable technology in a variety of applications in the field of large area electronics. Even though OFET research community has improved the mobility of charge carriers to about 43 cm2/V s, it is still far beyond that of conventional silicon based transistors.1 Along with charge carrier mobility, serious attention has also been paid in the past decade to improve the operational stability of OFETs, manifesting as hysteresis and as threshold voltage shift under prolonged gate and drain bias stress, which is of paramount importance in practical and commercial applications of these devices. Charge traps at dielectric/ semiconductor interface, in the dielectric and/or semiconductor itself influenced by grain size and morphology, and their interaction with extraneous factors like oxygen and moisture from the ambient result in hysteresis and bias stress effects.2−5 Many studies have noted improvement in molecular ordering and grain size in the films by dielectric surface © XXXX American Chemical Society

modification, either using self-assembled monolayers (SAM) or polymers,6,7 post deposition annealing of organic semiconductors etc.2,8,9 and in turn on threshold voltage stability. It should be noted that while most of these studies focus on the grain size and morphology of the bulk of the film, influence of the grain size and the growth conditions at the dielectric/ semiconductor interface (where most of the charge carriers accumulate) on threshold voltage stability is less addressed.10,11 Since practical applications of OFETs demand excellent stability of these devices in ambient conditions,12 it is essential to have knowledge on the influence of different parameters that affect their threshold voltage stability. Though substrate temperature has been a most important parameter to modify the morphology for thermally evaporated small molecules like Received: November 23, 2015 Accepted: January 13, 2016

A

DOI: 10.1021/acsami.5b11349 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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ACS Applied Materials & Interfaces

self-assembled monolayers (SAM). In the present study, we have employed the above-mentioned techniques to probe the buried interface between CuPc and SiO2 to monitor substrate temperature-induced growth conditions. We have shown again that complemented with XRR, the PAS technique can be successfully employed to probe the buried interfaces modified under different experimental conditions. Many studies generally attribute hysteresis to either electron or hole trapping at dielectric/semiconductor interface or in the bulk of semiconductor.34−36 In our previous study on CuPcbased OFETs, we have identified contributions of both hole and electron trapping to hysteresis where grain boundary density was found to affect the former and hydroxyl groups at the interface was found to predominantly influence the latter.37 Previous studies correlating conditions at the initial monolayers to threshold voltage stability do not discriminate influence of the same on electron and hole trapping effect individually.10,11,21,22 In the present study, from the detailed knowledge of the growth modes obtained from the above-mentioned techniques, we have not only suggested the connection between the same and threshold voltage stability, but have also identified the influence of the same on electron and hole trap concentrations contributing individually to threshold voltage stability. It is well reported that grain boundaries act as serious hole traps and silanol (Si−OH) groups on the SiO2 dielectric act as electron and hole traps, and are seriously influenced by oxygen and moisture from the ambient.37,38 Since the aim of this study is to understand how the defects/disorders and the growth modes at the interface determine the extent of interaction of the semiconductor as well as the trap centers on the dielectric surface with the ambient, it is essential to carry out studies in ambient conditions without encapsulation of the devices as well as using suitable dielectrics without surface modification. We have observed hole trap concentration to be severely influenced with growth modes and electron trap concentration to be affected only moderately. Island formation at the dielectric/semiconductor interface was predominantly responsible for the hole trapping effect. It is worth mentioning here that even though there are many semiconductors offering higher mobility than CuPc, it is still suited for such studies as a model semiconductor under particular experimental conditions, as it offers better thermal and chemical stability. As the present study is on bias stress effect and threshold voltage stability, CuPc is more suited since it undergoes lesser degradation in air compared to other semiconductors thereby avoiding additional degradation factors. Since growth modes of CuPc was found to vary in a similar fashion with substrate temperature as mentioned for other p-type organic semiconductors before,16−20 it can be considered to be a valid model semiconductor. It is to be pointed out that our earlier studies have also shown severe hole trapping for the devices with island growth mode (on OTS/ SiO2) dielectric. Therefore, we can suggest that even though the present study is on substrate temperature induced growth conditions, they can be also be applicable in general to similar growth conditions under any experimental conditions, though further studies are required to confirm this. From this study, we have shown that using XRR and PAS technique we can identify growth modes at the buried interfaces in order to understand not only charge carrier mobility23 but also threshold voltage stability.

pentacene, copper phthalocyanine (CuPc), etc., studies on the dependence of threshold voltage stability on the same is scarce.13,14 Recently Ahmed et al. have attributed change in threshold voltage shift with substrate temperature for C60 based OFETs to radicals formed at the dielectric/semiconductor interface and to increase in grain size at certain substrate temperatures.15 But they have also not discussed about the change in growth conditions at the interface. As some studies reveal the variation in the growth modes with substrate temperature for organic semiconductors like pentacene, N,N′bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI8-CN2), C10-DNTT, etc.,16−20 it is essential to examine its correlation with threshold voltage stability. Therefore, in the present study, we have focused on the investigations on the substrate temperature induced growth mode variations of CuPc films, used as active layer. While Lee21 and Kim et al.22 connected threshold voltage stability to trapping of charges in the dielectric, Zhang et al. to the grain size at the initial monolayers10 and Ahmed et al. to overall grain size of the semiconductor films,15 in this study, we have identified that different growth modes, rather than the grain size, played a crucial role in determining threshold voltage stability. The use of same dielectric and with other experimental conditions the same, the difference in threshold voltage stability could be attributed to substrate temperature effect. In our previous study, we have discussed the necessity of techniques that can be used to study the buried interfaces and have demonstrated the potentiality of positron annihilation technique, complemented with X-ray reflectivity (XRR), to identify the growth conditions at buried interfaces.23Though Atomic Force Microscopy (AFM) is commonly used to study initial growth conditions, changes in interface conditions with increase in thickness of active layer at which the device operates, necessitates employment of techniques like positron annihilation, XRR, etc., to probe buried interfaces. Reflectivity measurements in specular mode of X-ray reflectivity technique map the variations in electron density along the direction normal to the surface providing useful information about the thickness of the layers and surface/interface properties with high sensitivity and nanometer accuracy.24,25 Though XRR has been used previously for studying growth conditions of organic semiconductor films,16,26−31 studies on substrate temperature controlled growth conditions are scarce,16 offering ample scope for investigations in that direction. Our group has been using beam-based positron annihilation technique to probe buried layers and interfaces in organic multilayers.25,32 The ability of the positron to get localized in low electron density regions (defects/open volumes) enables probing atomic order defects in materials. The annihilation γ radiation contains information about the trapping site and helps indentifying defects in the materials. The trapped state of a positron is manifested as increase in the lifetime of positron and narrowing of momentum distribution of the annihilation photon (measured from the Doppler broadening of annihilation γ radiation). In molecular systems (like organic semiconductors), the open/free volumes generated due to different packing arrangements of the molecules acts as a trapping site for the positron and can be probed by the technique. Therefore, beam-based PAS employing monoenergetic positrons can be used to probe surfaces, buried layers, interfaces and structural inhomogeneities in nanoscale thin films.33 In our previous study, we have probed the surface-energy-induced growth conditions at the CuPc/SiO2 interface modified using B


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2. EXPERIMENTAL SECTION Highly doped n-type (100) silicon wafer (0.01−0.015 Ω cm) was used as substrate and gate electrode, with 230 nm thermally grown SiO2 layer acting as the gate dielectric in the top contact OFET device structure used in this work. CuPc, purchased from Sigma-Aldrich and used as received, was thermally evaporated on to the SiO2 layer at a pressure of 1 × 10−5 mbar. The evaporation rate and the thickness of the film, as measured by quartz crystal monitor, were 0.5−1 Å/s and about 30 nm, respectively. The substrates were maintained at room temperature (RT/28), 100, 150, and 225 °C during the deposition of CuPc (devices/films A, B, C, and D, respectively). The OFET devices were fabricated by thermally evaporating gold through a shadow mask for source (S) and drain (D) electrodes above CuPc film with channel length (L) and width (W) of 25 μm and 2 mm, respectively. The current−voltage (I−V) characteristics were measured in air at room temperature under normal room light conditions using a Keithley voltage source current meter (model 6487). Structure of the films was determined by carrying out X-ray diffraction measurements (RIGAKU RINT 2000) using Cu Kα radiation at a low incident angle (angle fixed at 0.1°). The surface morphology of CuPc films were verified using scanning electron microscopy (SEM) (VEGA TC) and Atomic Force Microscopy (AFM) (NT MDT SOLVER). X Ray reflectivity measurements were carried out with a rotating anode X-ray source using Cu Kα (λ = 0.154 nm). Depth profiling to probe interfacial nanostructure was carried out using Doppler broadening of annihilation γ radiation (511 keV) in positron incidence energy range from 0.2 to 18.2 keV. Further details are given in Supporting Information. Positron/Ps lifetime measurements were carried out at two different incident energies viz. 0.8 and 1.1 keV (corresponding to sub-surface and near-interface regions, respectively) using pulsed positron beam facility at National Institute of Advanced Industrial Science and Technology, Tsukuba, Japan.39

Figure 1. AFM imaging of 2 nm CuPc film at different substrate temperatures: (a) RT,23 (b) 100, (c) 150, and (d) 225 °C, with their corresponding height profiles.

3. RESULTS AND DISCUSSION 3.1. Structural Characterization of CuPc Films. A change in morphology of CuPc films verified by SEM (Figure S1) and the improvement in crystallinity of CuPc films with increase in substrate temperature seen from XRD patterns (Figure S2) are discussed in Supporting Information. 3.2. Interface Characterization. Growth conditions at dielectric/semiconductor interface were monitored using AFM as well as XRR and PAS techniques, as described below. 3.2.1. Atomic Force Microscopy (AFM). About 2 nm thin CuPc films were deposited at different substrate temperatures and the morphology were imaged using AFM as shown in Figure 1. Height profile of RT deposited CuPc film (Figure 1a) shows 2D + island growth mode with some of the grains having heights much less than 1.3 nm, which is the length of CuPc molecule.23 The average surface roughness of the film was about 0.5 nm. If the molecule had been standing upright, one monolayer height would have been close to 1.3 nm, but because of significant tilting, the height is much less than 1.3 nm. Height profile for the film deposited at 100 °C (Figure 1b) also shows nearly 2D + island growth with increase in grain size as compared to that for film deposited at room temperature. Additionally, the CuPc molecules are found to be standing more upright compared to that at room temperature since height profile shows minimum height of islands to be more than 1.3 nm, which is a desirable condition for efficient charge transport. The height of most of the grains is about 2.5 nm indicating formation of second layer above the first monolayer in almost layer by layer fashion within the grains, though occasionally island growth is also observed (island with height 3.5 nm shown in Figure 1b). For the film deposited at 150 °C, grain

size due to first monolayer is further increased (300−500 nm) where CuPc molecules are clearly in upright condition. Island formation is observed above the first monolayer (location p in the height profile in Figure 1c), leaving this layer incomplete. As compared to 100 °C film, number of islands and height of islands both seem to be increasing. The average surface roughness for both 100 and 150 °C film increases as compared to RT film, which could be due to the upright standing of CuPc molecules. For the film deposited at 225 °C, larger grains (350−1000 nm) with huge islands forming right from substrate surface, i.e. from first monolayer itself (a in Figure 1d), leading to columnar growth and increased gap between the grains are observed. Large grains of size increasing to even about 1 μm, with continuous film up to the height corresponding to many monolayers and island or columnar growth above such continuous films (grain b in Figure 1d) are also observed. Earlier studies have shown similar growth changes of pentacene with substrate temperatures on SiO2 and alkylated SiO2 reporting 2D or layer-by-layer growth at room temperature19,28,31 and 3D island growth at higher substrate temperatures, similar to the case observed here.28 Liscio et al. have also reported change from layer by layer growth at room temperature to island growth at higher substrate temperature for N,N′-bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI8-CN2).16 Hofmockel et al. have reported dewetting of C10-DNTT molecules on the substrate surface and lack of connectivity between the grains for substrate temperatures above 80 °C,40 similar to that observed for CuPc films deposited around 225 °C in our study. All these studies show change in growth conditions at different substrate temperatures as seen in the present study, validating the use C


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above 0.8 keV reaching the substrate S-value indicates change in the packing mode of the film from sub-surface to near-interface region while no significant variation in the same is observed throughout the film thickness in the case of film D. The difference in S-parameter profile in the near-interface region in the films B and D shows that molecular packing mode is different in the two cases, as also seen from AFM imaging, i.e 2D+island for former and 3D island for latter respectively (Figure 1b, d). The difference in growth behavior is attributed to the effect of substrate temperature on the kinetics of CuPc molecules as discussed above. The sensitivity of S-parameter to the variation of molecular ordering as a function of depth has been observed by us earlier.23 In the near-interface region, film A shows an increase in S-parameter with a hump like feature around 1.1 keV, whereas, the profiles for films B and D show smooth variation of S-parameter with S-value approaching smoothly to the substrate value. The increase in S-parameter near the interface in film A indicates trapping of positrons in disorder/defects present at the interface giving rise to a distinct interfacial layer near the dielectric surface. The smooth variation of S-parameter in the case of film B and D shows the absence of a distinct interfacial region near the dielectric surface revealing ordered arrangement of molecules on the dielectric surface. The presence of defects/disorder at the initial layers near the dielectric surface in film A leads to random arrangement of molecules in the subsequent layers giving rise to a large number of structural defects within the grains throughout the thickness of the film, as reflected from the S-parameter profile. On the other hand, since the molecules are arranged in ordered fashion on the dielectric surface itself in films B and D, they probably continue to grow in ordered manner throughout the bulk of the film, resulting in less structural disorder in the films. Table 1 shows the positron/positronium (Ps) lifetimes in films A, B, and D at positron energies 0.8 and 1.1 keV corresponding to sub-surface and near-interface regions, respectively. In general there is no Ps formation in bulk phthalocyanines.33 Ps formation was also not observed in our earlier study on the growth behavior of CuPc on SAM modified substrates.23 However, in the present study, it is interesting to see the presence of Ps formation in the case of film D unlike films A and B. The presence of Ps formation could be ascribed to the difference in the packing mode of CuPc molecules due to the variation in growth behavior as discussed below. The average positron lifetime (τavg) is sensitive to electron density at the annihilation site and, in molecular systems can provide information about the molecular packing. In the case of film A, there is marginal decrease in τavg from the near-interface to sub-surface region where it corresponds to positron lifetime in bulk phthalocyanines33 while there is no significant variation in τavg in the two regions in the case of film B. Interestingly, the S-parameter has shown significant variation in molecular ordering from sub-surface to near-interface region in the film

of CuPc as a model system for this study. The above observed different growth conditions are dictated by the growth kinetics dominated by the increased diffusion of molecules on the surface of the substrate and their re-evaporation at higher substrate temperatures, described in detail in the Supporting Information. As mentioned before, variation of film characteristics at the interface can be expected with increase in thickness of the film. Since the above AFM imaging is for 2 nm film while the devices are operated at about 30 nm thickness, other techniques which can probe the buried interfaces are required. In the present study, we have demonstrated the sensitivity and capability of positron annihilation and XRR techniques to probe the substrate temperature controlled growth conditions. 3.2.2. Positron Annihilation Spectroscopy (PAS). Figure 2a shows the S-parameter profile for films A, B and D, normalized

Figure 2. (a) S-parameter profile for CuPc films deposited at different substrate temperatures: (A) RT,23 (B) 100, and (D) 225 °C and (b) the corresponding S-parameter profiles up to 6 keV.

with respect to the average S-value in the silicon substrate. The positron implantation energy ∼1.2 keV corresponds to the interface between ∼30 nm CuPc layer and the dielectric substrate. Figure 2b shows the S-parameter profile up to 6 keV positron energy for better illustration of the differences in the CuPc layers. The S-parameter shows a decreasing trend in the sub-surface region (∼0.2−0.8 keV) for all the films indicating the crystalline nature of the films, as observed by us earlier.32 However, there are significant differences (sub-surface and near-interface region) in the S-parameter profiles for all the films. The S-parameter decreases from surface to the region corresponding to ∼0.8 keV positron energy (corresponding to ∼16 nm depth) in the case of films A and B, whereas, film D shows decrease in the same until ∼1.25 keV positron energy (corresponding to the thickness of the CuPc layer). The change in S-parameter with implantation energy as well as its magnitude is seen to be smaller in film A compared to films B and D, indicative of hindered diffusion of positrons in the bulk of the film A. This indicates that trapping of positrons in structural defects arising due to disordered packing/arrangement of molecules is more in the case of film A as compared to films B and D. In the case of film B, the increase in S-parameter

Table 1. Positron/Ps Lifetimes and Intensities at Sub-surface (0.8 keV) and near-Interface (1.1 keV) Regions 0.8 keV (sub-surface region) films A B D

τ

avg

(ns)

0.333 0.339 0.335

I

avg

(%)

100 100 92.87

τ 3 (ns)

1.39

1.1 keV (near-interface region) I3 (%)

7.08 D

τ

avg

(ns)

0.340 0.337 0.329

I

avg

(%)

100 100 90.31

τ 3 (ns)

I3 (%)

1.46

9.68


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ing fits for CuPc films grown at different substrate temperatures are shown in Figure S3. The physical structure of the films was modeled as CuPc/intermediate layer/SiO2 (230 nm)/Si to get the best fits to the profiles. Zero position of the depth axis indicates the air−film interface. The SiO2 layer of thickness 230 nm has been truncated to highlight the interface. The scattering length density (SLD) profiles clearly show the presence of the interface layer between CuPc and SiO2 dielectric for all the films with significant difference in interface layer thickness. This is a clear indication of the variation of molecular ordering/ packing with substrate temperature at CuPc/SiO2 interface. Interface layer thickness is seen to be increasing with substrate temperature even though roughness was found to be reducing. Interface width generally depends on roughness, which could be due to both physical roughness caused by misorientation of molecules and graded variation of electron density along the plane normal to the surface.41 Variation in interface width in the present study could be attributed to mainly variation in molecular packing causing difference in electron density. SLD profile for RT deposited film (A) is included for comparison.23 As discussed in that study for film A, highly defective CuPc layer at dielectric/ semiconductor interface with clustering of CuPc molecules (CuPc molecules tilted and stacked one above the other) resulting in a rough interface layer with large physical roughness can be expected. Since Cu in these molecules acted as main scattering center for X-rays, clustering of Cu atoms per unit volume resulted in higher SLD. Since the tilted and defective molecules are expected to gradually flip to upright standing orientation with increase in thickness, gradual variation in electron density could be observed for this film with interface width extending up to about 4 nm above SiO2 surface with SLD higher than that of bulk CuPc. In the case of film B (deposited at 100 °C), flipping of CuPc molecules to nearly upright standing position at the first monolayer itself and nearly layer by layer growth within the grains up to a few monolayers initially and the island formation beyond, could be leading to abrupt change in electron density at a distance even farther away from SiO2 surface. This could be resulting in increased interface width as compared to that for film A. Increase in grain size compared to that of film A (Figure 1b) could be leading to lesser physical roughness at interface layer than that for film A. In the case of film C (150 °C), there is only a slight increase in interface width further. Since admolecules diffusivity is expected to increase with substrate temperature, better molecular packing can be expected at this temperature which is also indicated by reduced FWHM in XRD pattern (Figure S2). As seen from AFM height profile (Figure 1c) increase in grain size with closely spaced island formation in the second layer could be averaging out to an electron density condition almost similar to that observed for film B, with only a slight increase in interface width. Improved molecular packing for both films B and C could be resulting in larger density of CuPc molecules per unit volume and hence increased Cu scattering centers, thus resulting in higher interface layer SLD than the bulk. For CuPc films deposited at 225 °C, SLD profile shows even higher increase in interface width with large and abrupt change in electron density much farther from the dielectric surface as compared to the other three films. Stronger molecular packing, formation of huge islands and coalescence of islands leading to nearly continuous film up to many monolayers height (grain b in Figure 1d), could have led to large increase in electron density with lesser physical roughness in the interface region.

B. It is to be noted that the change in electron momentum distribution due to structural arrangement of molecules is reflected in S-parameter, however, the electron densities can be same for two different arrangements. Therefore, it is observed that although positron lifetime offers insight about the molecular packing density, S-parameter is seen to be sensitive to molecular ordering in organic systems. The S-parameter behavior for film B shows similarity with that of CuPc film on PTS/SiO2 in our previous study23 which we had attributed to ordered 2D like growth at initial monolayers with island formation above. However, there is significant difference in the variation in τavg between sub-surface and near-interface regions in the two cases. In the present case (film B), τavg indicates no significant change in average electron density from near-surface to sub-surface region unlike that of CuPc grown on PTS modified substrate although the molecular ordering can change with the thickness in both the cases (as seen from AFM imaging). The increase in molecule−molecule compared to molecule−surface interaction resulted in closer molecular packing at higher thicknesses in the latter case whereas, the high temperature (100 °C) of the substrate could have resulted in closer packing of the molecules even in the near-interface layers resulting in insignificant variation in τavg from nearinterface to sub-surface region. On the other hand, in the case of film D, there is reduction in τavg from sub-surface to near-interface region with the presence of a long Ps component in both the regions. Reduction of τavg in near-interface region as compared to that at sub-surface region implies much higher molecular packing density at the former as compared to that at the latter. The long Ps component in this film indicates the presence of nanovoids (free-volume) or surfaces unlike other films. The probability of desorption of molecules during the growth at high substrate temperature is more and may lead to nanovoids/free-volume in the film structure. The increase in Ps intensity from sub-surface to nearinterface region indicates more number of free-volume/ nanovoids near the dielectric surface. 3.2.3. X-ray Reflectivity (XRR). Figure 3 shows the scattering length density (SLD) profiles obtained from XRR data fits for CuPc films deposited at different substrate temperatures on SiO2. The experimental XRR profiles data with the correspond-

Figure 3. SLD profile of CuPc films deposited a different substrate temperatures − RT,23 100, 150, and 225 °C. Fitted width of the interface is indicated for each film. E


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sweep than that in ON to OFF sweep. Such hysteresis is suggested in literature to be due to two possible mechanisms: a) electron trapping effect- filling of deep electron traps in the semiconductor or at dielectric/semiconductor interface during OFF state (positive gate voltage) at the beginning of gate voltage sweep induces more holes to neutralize these extra negative charges. This results in higher drain current in forward sweep shifting transfer characteristics towards positive gate voltage and hence positive threshold voltage.34,35 During reverse sweep, these trapped electrons are released resulting in reduced drain current and shift in threshold voltage towards negative gate voltage, b) hole trapping effect- long lifetime hole traps get filled during OFF to ON sweep36 resulting in reduced mobile hole density and hence lesser drain current during reverse (ON to OFF) sweep. Since both hole and electron trapping effect contribute to hysteresis,37 to distinguish between the individual contributions of electron and hole traps to hysteresis, as decided by growth conditions at the interface, transfer characteristics were also measured from −4 V to −50 V for all OFETs (Figure S4). Threshold voltage shift (ΔVT) for all the devices estimated from Figure 5 and from Figure S4 is shown in Table 2.

Presence of largely spaced islands above such continuous layers could be causing the abrupt change in electron density much farther from interface, resulting in significant increase in interface width. Therefore, in spite of lesser roughness, increase in interface width is a strong indication of the presence of huge islands. The above results show that XRR measurements also clearly imply improved molecular packing and island formation of CuPc films with substrate temperature, as also seen from AFM imaging and positron techniques. On the basis of the inferences on buried interface conditions provided by above verifications, the substrate temperaturedependent growth of CuPc molecules at dielectric/semiconductor interface can be well-described by the schematic as shown in Figure 4.

Table 2. Threshold Voltage Shift (ΔVT) for OFETs with CuPc Films Deposited at Different Substrate Temperatures; Results for CuPc Deposited at 28 °C Are included for Comparison37

Figure 4. Schematic of growth conditions of CuPc molecules on SiO2 surface deposited at (a) RT, (b) 100, (c) 150, and (d) 225 °C.

threshold voltage shift (ΔVT) (V)

3.3. Interface Growth Modes Influenced Hole and Electron Trap Concentrations of OFETs. Transfer characteristics of all OFETs in saturation region were measured by varying gate voltage between +20 V (OFF state) to −50 V (ON) and back to +20 V (Figure 5) with a step size of 2 V and drain voltage fixed at −50 V. Anticlockwise hysteresis in transfer characteristics shifting the threshold voltage VT (Supporting Information for estimation of VT) is observed with larger drain current |ID| in OFF to ON

substrate temp (°C)

start at −4 V

start at +20 V

28 (A) 100 (B) 150 (C) 225 (D)

3.0 2.0 6.5 9.0

8.0 6.0 9.5 14.0

trap concentration hole (Nth) (/cm2) 5 3.3 6.6 8.9

× × × ×

1011 1011 1011 1011

electron (Nte) (/cm2) 1.9 1.8 1.5 2.1

× × × ×

1012 1012 1012 1012

Increase in ΔVT for scans from +20 V indicate additional contribution from electron trapping. Though some electrons can get trapped even at low negative gate voltages, the extent of the same can be expected to be minimized compared to that for scans starting from positive gate voltage and hence ΔVT estimated for scans starting from −4 V can be expected to be majorly due to hole traps. In order to further confirm the hole and electron trap concentrations individually, transfer characteristics were measured from 0 to −50 V before and after stressing the devices at gate voltages of +20 V and −50 V for 3 min (Figure 6). Even if some electrons get trapped at 0 gate voltage during the start of the scan, stressing at −50 V would detrap those electrons and hence can be expected to result in estimation of mainly hole trap concentration. Corresponding plots of √ID as a function of gate voltage VG, from which VT is estimated, are shown in Figure S5. A plot of ΔVT shown in Figure S6 with time for stressing at −50 and +20 V confirms the validity of sampling stressing period of 3 min to compare hole and electron trap concentrations. Hole (Nth) and electron trap concentrations (Nte) shown in Table 2 were estimated from the observed shift in threshold voltage for stressing at −50 and +20 V respectively using eq 142 Figure 5. Transfer characteristics of OFETs with gate voltage starting from +20 V for CuPc films deposited at different substrate temperatures: (a) RT,37 (b) 100, (c) 150, and (d) 225 °C.

Nth , Nte = F

Δ|VT|C i q

(1) DOI: 10.1021/acsami.5b11349 ACS Appl. Mater. Interfaces XXXX, XXX, XXX−XXX

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interface, minimum hole trapping centers near the interface region results in reduced hole trapping effect. Device C shows deterioration in threshold voltage stability as compared to that of device B even though this device was reported earlier to exhibit higher charge carrier mobility inspite of islands observed in Figure 1c.13 Islands appear to be closer enough to allow charge carriers to be transported but induces severe bias stress effect and shift in threshold voltage under prolonged DC bias stressing which is further enhanced for device D. In the case of device D, even though charge carriers might be transported efficiently on their journey to drain electrode through the large grains which sometimes have continuous film formation up to the height corresponding to many monolayers (grain b in Figure 1d) they would face strong hindrance posed by huge voids present between the grains even at the first monolayer level. Easy diffusion of moisture through such large voids up to the dielectric/interface could enhance hole trap centers at the interface as well as increase dipole interaction at large number of grain boundaries offered by island formation. Due to the pyramid like structure in an island growth mode, the gap between the grains increases with increasing number of layers which prevents contribution to percolation pathways.46 This causes detrimental effect to transport of charge carriers at a few monolayers distance from the dielectric/semiconductor interface. Even though charge carriers are accumulated in a few monolayers close to dielectric/semiconductor interface, they can be extended into entire thickness of active layer where they can also get trapped. This leads to volume trapping effect under prolonged DC bias stressing, causing thickness and the nature of the film in the bulk to play a role.47 Increasing grain boundaries and gaps between grains in the bulk of the film thus could cause severe volume trapping effect, manifesting as a larger threshold voltage shift under DC bias stress (Figure 6 and Figure S7). Additionally, as mentioned before, coalescence of islands could be introducing defects within the large grains itself adding to further hole trapping effect. We have also shown in our earlier study on low operating voltage OFETs that 2D like growth mode in phenylhexyltrichlorosilane (PTS) SAM based devices resulted in much lesser bias stress effect13 than 3D growth mode of octyltrichlorosilane (OTS-8) SAM devices. Our earlier studies on octadecyltrichlorosilane (OTS-18) modified SiO2 dielectrics have also suggested detrimental effect of 3D like island growth mode at the interface to hole trap concentration.23,37 Some studies have compared bias stress stability of OFETs using various polymers with different functional groups as dielectric and have reported better bias stress stability for devices with fluoropolymers dielectric, even though these polymers were reported to be leading to 3D island growth of organic semiconductors.21,22,48 They have attributed better stability for such fluoropolymer devices to increased energy barrier for transfer of charge carriers from semiconductor to dielectric. In our study, even though water molecules and hydroxyl groups on the surface of SiO2 itself might cause traps, it can be said that since we have used the same dielectric for all the devices, difference in energy barrier does not arise. Therefore, hole trapping effect can be attributed to mainly the change in growth conditions at the interface with substrate temperature, which is the only difference between the devices. It should be pointed out at this juncture that efficient transport of charge carriers, in turn decided by the growth modes and presence of voids at the interface might additionally influence the transfer of charge carriers to the dielectric. Layer-by-layer growth modes with

Figure 6. Transfer characteristics before and after stressing at gate voltages of −50 and +20 V for all substrate temperatures: (a) RT,37 (b) 100, (c) 150, and (d) 225 °C.

Around 30 devices were tested for each substrate temperature, and about 85% of the devices in each case yielded results mentioned in Table 2. Hole trap concentration reduced to a minimum (Table 2) for device B (with near layer by layer growth of films deposited at 100 °C) and increased with further increase in substrate temperature, reaching highest for device D (for films with island formation at 225 °C). DC bias stressing of the devices for about 1 h, (Figure S7 and the details in Supporting Information) further support this conclusion. Electron trap concentration was also found to be highest for device D (225 °C) with huge islands and voids at the interface. Clear variations in hole and electron concentrations with substrate temperature indicate their dependence on the morphology and growth modes at the interface, which is discussed in the following section. 3.4. Mechanisms correlating hysteresis variation with change in growth modes at the interface. Lowest hysteresis and hole trap concentration for device B, highest for device D and high electron trap concentration for the latter, all these show that growth conditions at the interface have a strong influence which was also observed in our earlier study11 as well as by Zhang et al.10 Hole trapping is mostly known to occur at grain boundaries where moisture diffusing from ambient into the film causes dipole interaction with charge carriers adding to further structural deformation and hole trapping.43−45 Minimum hole trapping at 100 °C could be attributed to nearly layer by layer growth within the grains seen for this temperature. Even though grain sizes from the initial few monolayers are smaller compared to that at 150 °C, they are well-connected and no distinct islands offering large grain boundary density are present. Because of layer by layer formation within the grains, atleast for two monolayers in this case, and flipping of molecules to more upright standing condition with less defects, gap between grains up to the height of atleast two monolayers (in this case) is much less. This allows efficient transport of charge carriers between the grains even at a few monolayers distance from the interface. Additionally such closely spaced grains prevent easy diffusion of moisture up to the interface and minimizes dipole interaction at existing grain boundaries. Since a majority of the charge carriers accumulate close to the dielectric/semiconductor G


Research Article

ACS Applied Materials & Interfaces lesser gaps between the grains may cause charge carriers to flow more towards the drain electrode, thereby preventing transfer to the dielectric. Large gaps between the islands seen for 3D growth mode for substrate temperature of 225 °C might be allowing transfer of charge carriers into the dielectric, further enhancing hole trapping effect. We had shown in our previous study that photogeneration is the main source of electrons which get trapped mostly at dielectric/semiconductor interface under positive gate voltage, though grain boundaries could also be partly contributing to trapping them.37 Electron trap concentration was found to be lowest for device C and highest for device D. Well-connected grains with stronger molecular packing and increased grain size close to the dielectric surface could be efficiently covering the dielectric surface in the case of device C. This could be minimizing exposure of dielectric surface to moisture from ambient, which is known to attack the interface and enhance electron trap centers.5,9,35 In the case of 225 °C film (device D), easier diffusion of oxygen and moisture through the voids up to the interface and increased exposure of dielectric surface to moisture could cause significant increase in electron trapping centers. Even though large number of holes might be induced due to increased electron trapping effect, presence of huge voids might not allow these induced holes to easily flow as drain current thereby preventing large shift in transfer characteristics towards positive gate voltage that generally is taken as a measure of electron trapping effect. Such behavior was also observed in our previous studies on the effect of channel length and post deposition annealing conditions on hysteresis.49,50 In spite of this hindrance for hole transport, significant electron trap concentration is observed for 225 °C, implying that presence of voids seriously affects electron trapping in addition to hole trapping effect. Figure 6 and Table 2 clearly show distinct changes in threshold voltage shift and hole trap concentration and only moderate changes in electron trapping effect with substrate temperature. Even though the grain size was much higher for 225 °C film than that for 100 °C film, threshold voltage stability was much higher for the latter than for the former, unlike those mentioned in earlier studies.10,14,15 This shows that more than the grain size, growth mode plays a key role in deciding the threshold voltage stability. The study further indicates that island formation and 3D like growth of organic semiconductor at dielectric/semiconductor interface increases hole trapping and hence bias stress effect. The study also shows that PAS technique, complemented with XRR, can successfully reveal the growth modes at the buried interfaces correlating well with both charge carrier mobility23 (previous study) and with threshold voltage stability seen in the present study.

OFETs was studied. Hysteresis was found to be minimum for OFETs with CuPc film deposited at 100 °C and maximum for that at 225 °C. Further, influence of growth mode on individual contribution of holes and electrons to hysteresis was determined. It was noted that the change in growth conditions and the packing at the initial few monolayers was significantly affecting hole trapping effect which was minimum for films deposited at 100 °C and maximum for those at 225 °C. Electron trapping effect showed only moderate change, the highest for 225 °C films and lowest for devices with 150 °C film. Increase in hole trapping effect at higher substrate temperatures was attributed to island formation with large voids between the islands while minimum of the same at 100 °C was suggested to be due to nearly layer-by-layer growth mode. The study clearly reveals that more than the grain size, growth modes influenced threshold voltage stability and also had varying influence on hole and electron trapping effect. The study also shows that PAS technique, complemented with XRR, can be used to probe buried interfaces in OFETs, correlating well with threshold voltage stability.

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ASSOCIATED CONTENT

* Supporting Information S

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsami.5b11349. Details of experimental techniques−positron annihilation spectroscopy (PAS), X-ray reflectivity (XRR) to characterize dielectric/semiconductor interface, scanning electron microscopy (SEM) figures showing morphology of 30 nm thick CuPc films at different substrate temperatures, XRD patterns for structural characterization of CuPc films, transfer characteristics with gate voltage scan starting from −4 V, plots of √ID with respect to gate voltage before and after the stressing of OFETs with gate voltage at −50 and +20 V, threshold voltage shift measured intermittently at every 5 min, under DC bias stressing (PDF)

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AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS The authors thank IIT Bombay, for providing SiO2 wafers required for this work under INUP project.

4. CONCLUSIONS Influence of substrate temperature on the growth modes of CuPc film at the dielectric/semiconductor interface is investigated. AFM investigations revealed the change in growth pattern of CuPc from near layer by layer growth for films deposited at 100 °C to huge islands for 225 °C films. Buried dielectric/semiconductor interfaces were probed using positron annihilation and XRR techniques, which confirmed the changes in molecular packing with substrate temperature, i.e., lesser defects and closer packing at higher substrate temperatures, and indicated island formation at 225 °C. Influence of change in growth modes on hysteresis and threshold voltage stability of

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NOTE ADDED AFTER ASAP PUBLICATION This paper published ASAP on 1/27/16. A correction was made to Table 2 and the revised version was reposted on 1/28/ 16.

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Investigations on Substrate Temperature-Induced Growth Modes of

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