LETTER pubs.acs.org/NanoLett
Large-Scale Graphene Transistors with Enhanced Performance and Reliability Based on Interface Engineering by Phenylsilane Self-Assembled Monolayers Zihong Liu,* Ageeth A. Bol, and Wilfried Haensch IBM T. J. Watson Research Center, Yorktown Heights, New York 10598, United States ABSTRACT: In this letter, we report the dielectric/graphene interface physics and engineering of large-scale, chemical vapor deposited (CVD) graphene transistors by self-assembling a molecular-scale organosilane monolayer onto the dielectric surface. We show that phenyl-alkyl-terminated self-assembled monolayers (SAM) at the dielectric/graphene interface consistently improve the graphene device performance and reliability. The extrinsic field-effect mobility of large-scale CVD graphene transistors on the phenyl-SAM engineered dielectric is currently up to 2500 cm2/(V s) at room temperature, considerably higher than the counterparts without the SAM. In addition, significant reduction on the bias stress instability and hysteresis is achieved by the SAM-based interface engineering. Further analysis reveals that charge injection from graphene to the dielectric/graphene interface dominates the observed hysteresis behavior. For both graphene transistors with and without SAMs, the bias stress stability, that is, Dirac point shift under bias stress, is well described by the stretched exponential model with its fitting parameters clearly indicating different interface properties. KEYWORDS: Graphene, field-effect transistor (FET), interface engineering, organosilane, self-assembled monolayer (SAM), charge transport, reliability, hysteresis, bias stress, Dirac point shift
raphene, an atomically thin layer of 2D carbon film, has emerged as a promising candidate material for high-speed nanoelectronics due to its extraordinary electrical and optical properties.1-8 The intrinsic mobility of graphene is predicted to reach 200 ,000 cm2/(V s) at room temperature.9 Among many other applications, the graphene field-effect transistor (FET) is recognized to be a complement to the traditional silicon FET for the next generation of very large scale integration (VLSI) circuits4,5,7,8 and, particularly, radio frequency (RF) electronics.10-13 However, graphene transistors fabricated on dielectric substrates, for example, SiO2, typically exhibit a field-effect mobility being multiple orders of magnitude lower than the intrinsic graphene mobility.8,9 Also, unfavorable hysteresis behavior and electrical instability can always be found in these devices. Graphene FET performance and reliability can be dominated by the dielectric/graphene interface, where a variety of scattering and trapping effects have been identified.9,14-17 In addition to the intrinsic graphene acoustic phonon scattering, Coulomb impurities, surface roughness, and surface polar phonon scattering from the adjacent dielectric can all affect charge transport in the device. These scattering effects become especially pronounced for devices operated at room temperature. This is corroborated by the fact that suspended graphene does not suffer from extrinsic scatterings and thus, is ideal for studying intrinsic graphene properties.18-20 For device applications, nonpolar substrates have been suggested to be beneficial,9,14 yet finding such materials remains a challenge. Recent work using a
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r 2010 American Chemical Society
hydrophobic hexamethyldisilazane layer as the silicon oxide surface modifier,16 or using single crystal hexagonal boron nitride (h-BN) as the substrate21 has shown encouraging results. However, they are based on exfoliated graphene flakes, which are unsuitable for large-scale technological application. Also, the interface physics for the graphene transistor performance and reliability still requires further exploration. In this letter, we report the dielectric/graphene interface physics and interface engineering of bottom-gated, large-scale chemical vapor deposited (CVD) graphene transistors by applying molecular phenyl-terminated organosilane self-assembled monolayers (SAM) onto the dielectric surface. CVD graphene is utilized here due to its scalability and manufacturability for large-area device integration.22-24 We show that the phenylalkyl-SAM-based interface engineering consistently improves the CVD graphene FET mobility, hysteresis, and bias stress stability, making it promising for practical application. Through systematic measurements and model fitting for graphene transistors with and without the phenyl-SAM, we clarify the physical mechanisms responsible for the FET mobility, hysteresis, and bias stress behaviors. Figure 1a shows a general bottom-gated graphene transistor structure used for this study. In our experiments, a heavily doped Received: September 24, 2010 Revised: December 11, 2010 Published: December 20, 2010 523
dx.doi.org/10.1021/nl1033842 | Nano Lett. 2011, 11, 523–528
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Figure 1. (a) A general bottom-gated graphene FET structure with phenyl-SAM interface engineering. (b) Illustration of chemical bonding of the organosilane SAM to the hydroxyl group-enriched dielectric surface. (c) AFM image of a spin-coated ultrasmooth phenyl-SAM with surface roughness of 0.1-0.2 nm in rms. (d) Microscopy image of a large-area, uniform CVD graphene as patterned to various shapes on a phenyl-SAM engineered silicon oxide wafer (white square areas are metal contacts).
n-type (100) silicon wafer and a 300 nm, thermally grown silicon oxide serves as the gate electrode and dielectric, respectively. After cleaning the dielectric surface with copious amount of acetone, isopropanol, and DI water, the wafer is exposed to oxygen plasma at 100 W for 10 s. Oxygen plasma processing not only removes the residual organic contamination on the dielectric but also promotes the surface coverage by the hydroxyl group and facilitates the subsequent organosilane SAM growth.25 This step can be replaced by using UV ozone treatment.25 We then assemble a molecularly thin phenyl-terminated organosilane SAM on the hydroxyl-enriched dielectric surface by a recently developed spin-coating process.26,27 Briefly, 1-1.5:1000 phenyl-silane/anhydrous-toluene mixed solution is prepared in a N2 filled inert environment and then spin-coated on the dielectric surface at 3 Krpm for 1 min. The phenyl-silane reacts immediately with the hydroxyl group and is chemically bonded to the dielectric surface as illustrated in Figure 1b. To complete the SAM polymerization, the substrate is kept in a desiccator overnight and then sonicated in toluene, acetone, and isopropanol (each for 5 min) to remove residue from SAM deposition. Figure 1c shows an atomic force microscopy (AFM) image of 4-phenylbutyltrichlorosilane (PBTS)-based SAM28 on the silicon oxide with an ultrasmooth surface (roughness, 0.1-0.2 nm in rms). This densely packed monolayer has been confirmed by a high water contact angle of ∼85 and a film thickness of ∼8.3 Å as measured by ellipsometry/X-ray reflectivity,26,27 which is comparable to the calculated PBTS molecule length of ∼11 Å per the PM3/MOPAC9 model. Following the phenyl-SAM formation, large-scale CVD graphene is transferred onto the wafer. In this work, we prepared the graphene films by CVD growth on Cu foils. Specifically, a piece of Cu foil (25 μm thick, Sigma-Aldrich) was placed in a 1 in. diameter quartz furnace tube at low pressure (60 mTorr). Prior to processing, the system was flushed with 6 sccm of forming gas
(5% H2 in Ar) for two hours at a pressure of around 500 mTorr to remove any residual oxygen and water present in the system. The Cu foil was then heated to 875 C in forming gas (6 sccm, 500 mTorr) and kept at this temperature for 30 min to reduce native CuO and increase the Cu grain size. After reduction, the Cu foil was exposed to ethylene (6 sccm, 500 mTorr) at 875 C for 30 min. The sample was cooled down in forming gas (6 sccm, 500 mTorr). PMMA was spin-coated on top of the graphene layer formed on the Cu foil, and the Cu foil was then dissolved in 1 M iron chloride. The remaining graphene/PMMA layer was thoroughly washed with DI water and transferred to both substrates with and without the phenyl-SAM. Subsequently, the PMMA was dissolved in hot acetone (80 C) for one hour. The substrates with graphene were rinsed in methanol and dried in a stream of nitrogen. Figure 1d shows a microscopy image of the patterned CVD graphene on the phenyl-SAM engineered silicon oxide wafer, where a large-area, highly uniform graphene film can be clearly identified. The source and drain contacts for the graphene FET in Figure 1a are patterned by photolithography and 5 nm Ti/40 nm Pd/40 nm Au are deposited by sputtering. To complete the devices, another photolithography step is required to define the graphene channel. Reactive ion etching (RIE) in O2 plasma (100 W, 1 min) then removes the excess graphene outside of the active regions. The photoresist used to protect the graphene channel is finally striped off by hot acetone. Owing to the large size and good uniformity of the CVD graphene film, we are able to fabricate many identical devices on the same substrate for each specific device design. This also enables us to perform statistical analysis and consistent comparison for the device performance without bringing artifacts from discrete flakes. The graphene FETs are annealed in a rapid thermal annealing (RTA) tool (N2 gas) at 300 C for 10 min before being transferred to a vacuum chamber for room-temperature electrical measurement. The 524
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μ, can be written as
0
1-1 X 1 1 A μ ¼ @ þ μint i,ext μi,ext
ð2Þ
where μext represents mobility limited by extrinsic scattering from the Coulomb impurities (CI), the surface roughness (SR), and the dielectric surface polar phonon (SPP), and μint is the mobility limited by graphene intrinsic scattering such as the longitudinal acoustic phonon scattering and graphene defects. μint is presumably similar for both graphene FETs with and without the phenyl-SAM, considering they are built from the same CVD graphene source. Since the device measurement shows μ(SAM) > μ(no SAM), we can deduce (μCI-1 þ μSR-1 þ μSPP-1)SAM < (μCI-1 þ μSR-1 þ μSPP-1)no SAM, indicating that our densely packed, ultrasmooth phenyl-SAM reduces the interface impurities and/or interfacial polar phonon coupling. In addition to the device performance in terms of field-effect mobility, electrical reliability is another major concern for graphene transistors and circuits application. Figure 2 shows significant improvement of the hysteresis has been achieved by the phenyl-SAM interface engineering. It is worthy noting that the hysteresis direction is always clockwise on the electron conduction side while counterclockwise on the hole conduction side. This phenomenon can also be found in the exfoliated graphene FETs fabricated on the SiO2 substrate.30 As illustrated in Figure 3, there are various mechanisms that may cause the hysteresis26,27 in graphene FETs, including (i) charge injection from graphene to the dielectric interface, (ii) charge injection from gate electrode to the dielectric and to the interface, either by trap-assisted tunneling or thermionic emission, (iii) reorientation of residual dipoles such as -OH groups in the bulk dielectric,31 and (iv) moving of mobile ions and charged impurities inside the dielectric. When the applied gate voltage, Vgs, is negative with respect to the Dirac point as shown in the energy band diagram in Figure 3a, holes are injected from graphene to the interface, causing a change of the surface charge density by ΔQs > 0. In the meantime, corresponding to the foregoing mechanisms (ii-iv), electrons are injected from the gate to the dielectric, residual dipoles inside the dielectric get reoriented, and mobile ions are redistributed across the dielectric. The consequence is that more electrons and negative charges inside the dielectric accumulate closer to the dielectric/graphene interface under the applied gate electric filed. This yields mathematically R Tox ΔFox ðxÞx dx
