Light-Triggered Ternary Device and Inverter Based on Heterojunction of van der Waals Materials Jaewoo Shim,†,‡ Seo-Hyeon Jo,† Minwoo Kim,§ Young Jae Song,§ Jeehwan Kim,‡,∥ and Jin-Hong Park*,†,§ †
School of Electronic and Electrical Engineering and §SKKU Advanced Institute of Nanotechnology (SAINT), Sungkyunkwan University, Suwon 440-746, Korea ‡ Department of Mechanical Engineering and ∥Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, United States S Supporting Information *
ABSTRACT: Multivalued logic (MVL) devices/circuits have received considerable attention because the binary logic used in current Si complementary metaloxide-semiconductor (CMOS) technology cannot handle the predicted information throughputs and energy demands of the future. To realize MVL, the conventional transistor platform needs to be redesigned to have two or more distinctive threshold voltages (VTHs). Here, we report a finding: the photoinduced drain current in graphene/WSe2 heterojunction transistors unusually decreases with increasing gate voltage under illumination, which we refer to as the lightinduced negative differential transconductance (L-NDT) phenomenon. We also prove that such L-NDT phenomenon in specific bias ranges originates from a variable potential barrier at a graphene/WSe2 junction due to a gate-controllable graphene electrode. This finding allows us to conceive graphene/WSe2-based MVL logic circuits by using the ID−VG characteristics with two distinctive VTHs. Based on this finding, we further demonstrate a light-triggered ternary inverter circuit with three stable logical states (ΔVout of each state 22 V. When a low VIN (below 10 V) was applied, a higher drain current was measured in the WSe2 TFT as compared to the heterojunction device. Thus, the WSe2 TFT provided a lowresistance path between the VDD and output terminal, exhibiting a high VOUT (logic state “1”). In contrast, when a high VIN (above 22 V) was applied, because the drain current of the heterojunction device was higher than that of the WSe2 TFT (a low-resistance path formed between output terminal and ground), a low voltage value (logic state “0”) was measured at the output terminal. Thus, under dark conditions (VIN1 was applied, and LIN was not supplied), the circuit in which the heterojunction and TFT devices were connected in series operated as a binary inverter. Figure 4e shows the voltage-transfer characteristics of the inverter circuit under two light-power conditions (VIN1 and LIN were applied), where VDD = −4 V, λ = 520 nm, and P = 200 μW (black-dashed line) and 50 μW (red-dashed line). Here, an intermediate value (logic state “1”) as well as high (logic state “2”) and low (logic state “0”) voltage values were obtained when VIN is between −12 and 10 V (at P = 200 μW) or between 6 and 13 V (at P = 50 μW). For reference, Figure S6 in the Supporting Information shows the ID−VG curves corresponding to the graphene/WSe2 heterojunction device and WSe2 TFT. However, the intermediate state of this circuit was unstable, showing small fluctuations between 2.1 and 2.6 V (at P = 200 μW) and between 0.6 and 0.7 V (at P = 50 μW). This is because the resistances of the graphene/WSe2 heterojunction device and WSe2 TFT constantly varied with the applied VIN in the intermediate input-voltage ranges. The two following conditions must be satisfied for the ternary
potential barrier formed between WSe2 and graphene is likely to suppress the collection of photoexcited electron carriers by the source electrode (panel I in Figure 3i). However, a negatively high VDS reduces the WSe2−graphene (channel− source) potential barrier; thus, the source electrode collects the photoexcited electron carriers more efficiently (panel II in Figure 3i). Therefore, the change in VDS from −2 to −6 V shifts the peak voltage to the negative gate-voltage direction (from 11.4 to 0.6 V). Regarding the peak current, more photoexcited hole carriers collect at the drain Pt electrode at a negatively higher VDS. This higher VDS induces a larger electric field at the drain Pt/WSe2 junction, consequently increasing the peak current, as shown in Figure 3i. For reference, we also performed I D −V G measurements of five different graphene/WSe 2 heterojunction devices with various WSe2 thicknesses to investigate the influence of the WSe2 thickness on the LNDT phenomenon (Figure S5, Supporting Information). Regardless of the WSe2 thickness (no dependence of the LNDT phenomenon on the flake thickness), similar ID−VG peaks were observed in the heterojunction devices with different WSe2 thicknesses. Finally, we developed a light-triggered ternary inverter comprising a graphene/WSe2 heterojunction device and a WSe2 p-channel TFT (Figure 4a shows the schematic). The WSe2 TFT and graphene/WSe2 heterojunction devices were connected in series, as shown in Figure 4b,c. The input voltage (VIN) was applied to the common Si back gate. The heterojunction device and WSe2 TFT were then irradiated with the input light signal (LIN). The supply voltage (VDD) was connected to the source electrode of the WSe2 TFT, and the source electrode (graphene) in the heterojunction device was grounded (VSS). The output voltage (VOUT) according to the input light signal (LIN) was measured in the middle drain electrode, which is shared by the heterojunction device and WSe2 TFT. Figure 4d shows the voltage-transfer characteristics of the inverter circuit under dark conditions (LIN was not 6324
DOI: 10.1021/acsnano.7b02635 ACS Nano 2017, 11, 6319−6327
Article
ACS Nano inverter to have stable three logic states: in the voltage range, where the current of the NDT device increases toward its peak with increasing the gate voltage in the negative voltage direction, (i) the I−V slope (ΔID/ΔVG) of the NDT device must coincide with that of the load transistor, and (ii) the resistance ratio of the NDT device and the load transistor should be 1:1. This ensures that the logic state “1” (intermediate state) is stably measured at the output terminal of the ternary inverter. Thus, the position and the height of the current peak in the NDT device should be optimized according to the operating characteristics of the load transistor. We controlled the peak voltage and peak current by adjusting the incident-light power to optimize the ternary inverter characteristic, thereby achieving three stable logic states, as shown in Figure 4f. The states are as follows: (i) 3.7 V < VOUT < 3.8 V (state “2”) for VIN < −12 V, (ii) 1.8 V < VOUT < 1.9 V (state “1”) for −5 V < VIN < 7.6 V, and (iii) 0.2 V < VOUT < 0.3 V (state “0”) for VIN > 12 V. To understand the operating principles of this circuit, we investigated the ID−VG characteristics corresponding to the heterojunction device (green-dashed line) and WSe2 TFT (black-dashed line) for VDS = −4 V, λ = 520 nm, and P = 110 μW (Figure 4g). In the negatively high VGS region (−30 V < VGS < −12 V), a low resistance path was formed between VDD and output terminal because the drain photocurrent flowing in the WSe2 TFT was high. Thus, a high voltage value (logic state “2”) close to VDD was measured at the output terminal. In the intermediate VGS region (−5 V < VGS < 7.6 V), the heterojunction device and WSe2 TFT have similar drain photocurrents, equally dividing the VDD. In particular, the intermediate state (logic state “1”) corresponding to half of VDD was stable because the difference in the photocurrents of the devices was similar in the bias region. Finally, in the positively high VGS region (12 V < VGS < 30 V), a much lower drain photocurrent was measured in the WSe2 TFT, resulting in a low resistance path between the output terminal and ground. This consequently resulted in a low voltage value (logic state “0”) at the output terminal.
junction. This barrier prevents the source electrode from collecting the photoelectron carriers, thereby decreasing the drain photocurrent in a specific bias region. In addition, the LNDT phenomenon could be controlled by adjusting the power and wavelength of the incident light and the applied drain voltage. Overall, the peak voltage shifted to the negative gatebias direction, and the peak current increased because of the increase in the incident-light power (from 17 μW to 360 μW), decrease in the wavelength (from 785 to 520 nm), or increase in the drain voltage in the negative direction (from −2 V to −6 V). The experimental results obtained in this study regarding the L-NDT-based ternary device and inverter prove the discovery of a next-generation device, setting the device and circuit standards for future MVL systems.
METHODS Fabrication of Graphene/WSe2 Heterojunction NDT Devices. Monolayer graphene grown on a Cu foil with the help of the CVD technique was transferred onto a highly p-doped Si substrate capped with a thermally grown SiO2 layer of thickness 90 nm using a conventional wet-transfer method. The transferred graphene was then patterned using photolithography and oxygen plasma etching processes. Next, a WSe2 flake was exfoliated on a poly(methyl methacrylate) (PMMA)/poly(vinyl alcohol) (PVA)/Si substrate using an adhesive tape (224SPV, Nitto). The sample was then dipped in deionized water (DI water). The PVA layer was dissolved, resulting in a WSe2/PMMA layer floating on the surface of DI water. The floating WSe2/PMMA layer was transferred to a metal slide and, subsequently, transferred onto the patterned graphene through a mechanical-transfer process. The sample was then dipped in acetone overnight to remove the PMMA layer. Finally, Pt/Pd (10/30 nm) layers were deposited on the graphene and WSe2 using an electron-beam evaporator. Implementation of Light-Triggered Ternary Inverter. First, using the mechanical-transfer method, a WSe2 flake was stacked onto the patterned graphene layer, and the heterojunction structure was transferred onto a SiO2/Si substrate of thickness 90 nm. Pt/Pd (10/30 nm) layers were deposited using an e-beam evaporator to form contacts on graphene and WSe2, followed by a lift-off process in acetone. To implement the light-triggered ternary inverter circuit, the graphene/WSe2 NDT device and WSe2 TFT were connected in series, the VDD was applied to the source electrode of the WSe2 TFT, and the graphene source of the NDT device was grounded (VSS). The common Si back gate of the WSe2 TFT and graphene/WSe2 NDT devices served as the input terminal (VIN). The output voltage (VOUT) was measured at the drain electrode shared by the graphene/WSe2 NDT device and WSe2 TFT. Characterization of Graphene/WSe2 Heterojunctions. AFM analysis was conducted using an XE-150 (Park Systems Corp.) system, and optical images were captured using a BX51 M microscope (Olympus Corp.). Raman spectroscopy analysis was performed using a WITec micro-Raman spectrometer system with a frequency-doubled Nd:YAG laser beam (532 nm laser excitation). KPFM measurements were performed using a NTEGRA Spectra (NT-MDT). Electrical measurements were conducted at room temperature using a Keysight B2912A under dark and illuminated conditions. A dot laser with wavelengths 520, 655, and 785 nm served as the light source with a spot size of approximately 660 μm2. The temperature-dependent electrical characteristics were investigated in a vacuum chamber (below 10−4 Torr) using a Keithley 4200 semiconductor parameter analyzer. UV−vis absorption spectra were obtained using a V-670 spectrophotometer (Jasco Inc.). Extraction of Barrier Height Values between Graphene and WSe2. Based on the thermionic emission theory, thermionic emission current is defined as follows:
CONCLUSIONS In conclusion, we reported the L-NDT phenomenon where the photoinduced drain current in an MVL device unusually decreases with increasing gate voltage under illumination. This peculiar phenomenon has not been observed in conventional transistor devices. Because of the unusual ID−VG characteristic with two VTH based on the L-NDT phenomenon, we were able to implement a ternary inverter circuit with three stable logical states (ΔVout of each state
