Liquid-Gated Two-Layer Silicon Nanowire FETs: Evidence of

Letter Cite This: Nano Lett. XXXX, XXX, XXX−XXX

pubs.acs.org/NanoLett

Liquid-Gated Two-Layer Silicon Nanowire FETs: Evidence of Controlling Single-Trap Dynamic Processes Yurii Kutovyi,† Ihor Zadorozhnyi,† Volodymyr Handziuk,† Hanna Hlukhova,† Nazarii Boichuk,† Mykhaylo Petrychuk,†,‡ and Svetlana Vitusevich*,† †

Bioelectronics (ICS-8), Forschungszentrum Jülich, 52428 Jülich, Germany Faculty of Radiophysics, Electronics and Computer Systems, Taras Shevchenko National University of Kyiv, 03127 Kyiv, Ukraine

‡

Nano Lett. Downloaded from pubs.acs.org by NEWCASTLE UNIV on 10/26/18. For personal use only.

S Supporting Information *

ABSTRACT: We fabricate two-layer (TL) silicon nanowires (NW) field-effect transistors (FETs) with a liquid gate. The NW devices show advanced characteristics, which reflect reliable single-electron phenomena. A strong modulation effect of channel conductivity with effectively tuned parameters is revealed. The effect opens up prospects for applications in several research fields including bioelectronics and sensing applications. Our results shed light on the nature of single trap dynamics which parameters can be fine-tuned to enhance the sensitivity of liquid-gated TL silicon nanowire FETs.

KEYWORDS: Silicon nanowire, modulation effect, single electron phenomena, gate coupling effect, noise spectroscopy, random telegraph signal noise

T

based memory devices. It also transpires that the RTS phenomenon might be very promising for biosensing applications.12−15 In particular, the positive outcome of this effect for biosensing with liquid-gated silicon nanowire fieldeffect transistors (NW FETs) was recently demonstrated.15,16 It was shown that the characteristic capture time of single-trap switching kinetics is highly sensitive to the surface potential determined by the different pH values of the gating solutions. According to the classical Shockley−Read−Hall (SRH) model for an active single trap, this parameter depends linearly on the concentration of free carriers near the Si/SiO2 interface, for example on the drain current.1,7,11 However, it has been shown experimentally that the capture time characteristic behaves like the power function of drain current9,15−19

he drain current switching events between two or more distinct states, known as random telegraph signal (RTS) noise, become more pronounced and almost unavoidable for scaled transistor devices. Usually, such drain current behavior is attributed to the trapping/detrapping of the single-charge carrier, which is caused by a single interface trap or defect near the Si/SiO2 interface.1−6 In general, the RTS noise is considered an undesirable process, because it causes the dynamic variability of electric devices and particularly affects the reliability, productivity, and quality of scaled complementary metal-oxide semiconductor (CMOS) transistors. Therefore, much effort has been made to suppress this phenomenon. However, it transpires that the RTS phenomenon obtained in CMOS devices is of fundamental importance. In particular, the investigation of RTS noise offers the opportunity to study electrically active single traps.6−11 For instance, a detailed investigation of RTS not only enables us to obtain the physical characteristics of the single trap, such as energy level and capture cross-section but also allows us to determine the location of the trap with high spatial resolution.11 Moreover, the RTS phenomenon provides a significant opportunity for practical applications, which is of interest for the modern electronics and sensors industry. In particular, it is expected to be a promising and reliable signal source due to the discrete nature of the phenomenon. Indeed, as a single-charge carrier process, the RTS phenomenon opens up prospects for future nanotechnologies, including the development of single-trap electrical switches, innovative logic elements, or even novel approaches for charge-trap© XXXX American Chemical Society

τc ∼

1 IDγ

(1)

where τc is the average capture time of the single electron, ID is the drain current in the Si NW FET, and γ is an order of the power function (γ ≥ 1). In the case of SRH model, the parameter γ is equal to one. Usually, this parameter acquires different values from 1 to 5 for typical nanowire FETs12,14,15,19 and depends on the carrier concentration in the channel.14 In comparison with the standard biosensing approach, which is based on monitoring Received: August 29, 2018 Revised: October 12, 2018 Published: October 22, 2018 A

DOI: 10.1021/acs.nanolett.8b03508 Nano Lett. XXXX, XXX, XXX−XXX

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Figure 1. (A) Doping profile of two-layer silicon nanowire (schematic). (B) High-resolution SEM image of fabricated Si NW FET. (C) Transfer characteristics of a 200 nm long and 100 nm wide Si NW FET measured in liquid-gate and back-gate configurations at a constant drain-source bias of 100 mV (left axis, linear scale; right axis, semilogarithmic scale). The back-gate electrode was floating while measurements with a liquid gate were performed and vice versa. (D) Transfer curves of the same liquid-gated FET measured at a drain-source voltage of 100 mV, which corresponds to the linear working regime of the transistor (inset: I−V curves on a semilogarithmic scale) and different back-gate voltages that were varied in the range from 0 to 7 V with a step size of 0.5 V.

allows for the sensitivity of the sensor to be fine-tuned and is also promising for overcoming the thermal limit.20 We thus demonstrate the positive role of single-trap phenomena for biosensing applications. The revealed effect is of major significance for the development of highly sensitive biosensors. Experimental Details. The structures being investigated were liquid-gated Si TL NW FETs fabricated by applying the complementary metal-oxide semiconductor (CMOS) compatible top-down approach to p-type ⟨100⟩-oriented SOI wafers with a 50 nm thick active silicon layer and a 145 nm thick buried oxide layer (BOX). The steps involved in the process of fabricating silicon nanowire devices are depicted in Figure S2 of the Supporting Information. A 55 nm thick heavily doped p-type silicon layer with a boron concentration of 1017 cm−3 was epitaxially grown using the chemical vapor deposition method on top of the 50 nm thick active silicon layer of SOI wafers with a boron concentration of 1015 cm−3. The impurity distribution as a function of the distance from the Si/SiO2 interface is schematically shown in Figure 1A. After epitaxy, a 20 nm thick SiO2 layer was formed on top of the SOI wafers by means of dry thermal oxidation. Nanowire structures were then written by electron-beam lithography in the poly(methyl methacrylate) (PMMA) resist. After development in the AR 600-55 developer solution, the structures were transferred to the silicon oxide mask using the reactive ion etching technique. In order to define the nanowires with a smooth surface and reduced defect density, anisotropic wet etching was subsequently performed at 80 °C in a 5%-tetramethylammonium hydroxide (TMAH) solution. After removing the oxide mask, source and drain contacts were highly implanted with arsenic dopants followed by a rapid thermal annealing process carried

drain current changes, the efficiency of this new approach strongly depends on the order of the power function γ. Therefore, in order to investigate whether single-trap capture time might depend on the carrier concentration in the channel with a higher order of the power law so that enhanced biosensor sensitivity can be obtained, we designed and fabricated silicon two-layer (TL) NW structures with different doping concentrations. Nanowires consist of two silicon layers: the first layer is the top active silicon layer of the silicon-oninsulator (SOI) wafer with a doping concentration of 1015 cm−3, whereas the second layer consists of heavily doped silicon with a doping concentration of 1017 cm−3, which was epitaxially grown on the top of the first silicon layer. As will be described below, fabricated nanowires demonstrate pronounced RTS noise with advanced characteristics favorable to a new sensing approach based on single-trap phenomena. Moreover, in order to establish the optimal regime of operation and therefore to enhance a single-trap kinetic, we applied voltage to both liquid-gate and back-gate electrodes simultaneously. A schematic illustration of the measurement configuration of the liquid-gated Si NW FET is depicted in Figure S1 of the Supporting Information. Analysis of experimentally obtained data using existing RTS noise behavior models has shown significant improvement of single-trap dynamics in Si TL NW FETs with respect to biosensing applications. The influence of the strong coupling effect between the liquid gate and the back gate in the fabricated NW structures allows the parameters of the single trap, that is, characteristic time constants, to be modified in a controlled way without any mechanical or chemical treatment. The observed effect for liquid-gated Si NW FETs has not yet been reported in the literature. Our results show that this effect B


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Figure 2. (A) Carrier distribution in two-layer Si NW FETs with rectangular cross section (obtained using TCAD software) at front-gate-voltage of 0.8 V and various applied back-gate voltages. The black line depicts the conditional boundary between the heavily doped and low-doped silicon layers. (B) The normalized transconductance curves obtained by 3D electrical simulations using TCAD software for 100 nm wide and 200 nm long Si nanowire at a constant drain-source bias of 100 mV when the back-gate bias is varied from 0 to 7 V in stages of 0.5 V. (C) Experimental normalized transconductance curves obtained from transfer characteristics depicted in Figure 1D.

out at 950 °C for 30 s to activate the dopants. An 8 nm thick SiO2 gate dielectric layer was then thermally grown by lowtemperature dry oxidation. As a result, the entire thickness of the top active silicon was about 90 nm after all oxidation processes. Then, in order to apply voltage to the substrate, for example, to the back-gate electrode, regions for back-gate contacts were etched through the buried oxide by immersing the sample in buffered oxide etch for 2 min. Low-resistive 10 nm/200 nm thick chromium/gold contact leads were subsequently formed by thermal evaporation followed by a lift-off process and annealing at 370 °C for 20 min to achieve ohmic contact. Finally, to prevent a current flow between contact pads and electrolyte during measurements, the polyimide layer was spin-coated as a passivation layer. Windows in the passivation layer allowing only liquid to access the nanowire area were opened by photolithography. In order to provide better working stability while operating in a liquid environment, nanowire structures were additionally passivated with a 10 nm Al2O3 layer deposited using the atomic layer deposition technique. After fabrication, the wafers were cut into single chips, wire-bonded, and encapsulated for liquid measurements. A typical, high-resolution scanning electron microscope (SEM) image of a well-defined nanowire structure is presented in Figure 1B. The current−voltage and low-frequency noise characteristics were measured in a custom-built Faraday cage to shield against any unwanted external electromagnetic radiation. Current− voltage characteristics were acquired using Keithley 2400 and 2430 current/voltage measurement units. For the noise measurements, the in-house ultralow noise measurement setup was employed. The required gate-source and drain-

source biases were applied to the sample using a rechargeable battery and a variable resistor. After the potentiometer, the voltage was additionally stabilized with a large capacitor of 5 mF. The drain-source voltage fluctuations were amplified to the measurable range using an in-house-fabricated ultralow noise preamplifier and then amplified by an Ithaco 1201 lownoise voltage amplifier. The acquisition of the amplified data in time domain was subsequently completed using the Agilent U2542A simultaneous data acquisition module. Finally, the obtained noise data were then transferred via a high-speed USB 2.0 interface to a PC, where the fast Fourier transform was performed on the time domain signal to frequency domain, yielding a voltage noise power spectral density (SV) in the 1 Hz to 100 kHz range after adjusting for amplifier gain. In order to achieve stable noise spectra, the number of averages was set at 100. Results and Discussion. A. Electric Properties of Si TL NW FET. The fabricated liquid-gated NW-based sensors exhibit typical behavior for metal-oxide semiconductor FETs at room temperature and can be operated by applying voltage either to the Ag/AgCl reference electrode immersed in the solution, which acts as a liquid gate, or to the substrate, which acts as a back gate, or by applying voltages to both gates simultaneously. Typical transfer characteristics of 100 nm wide and 200 nm long single silicon TL nanowire measured using either a liquid gate or a back gate are shown in Figure 1C. The drain−source bias was kept constant at 100 mV, and phosphate-buffered saline (PBS) with pH = 7.4 was used as a liquid-gate solution. As can be seen in Figure 1C, the drain currents in the liquidgated Si TL NW FET are higher than those measured in the same structure operated via back-gate voltage. This indicates C


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Figure 3. (A) Drain voltage PSD measured for a liquid-gated 100 nm wide and 200 nm long Si NW FET at different liquid-gate voltages and at a constant drain−source bias of 100 mV. The back-gate electrode is grounded. (B) Typical RTS drain current fluctuations registered in the same liquid-gated Si NW FET. (C) Histograms of the RTS noise obtained from the data in Figure 3B at VBG = 0 V. Solid lines show the best fit to twoGaussian distributions. (D) Time constants of the RTS noise plotted versus drain current. The dashed red line with slope (−6.16) reflects a stronger dependence of the capture characteristic time in comparison to the one predicted by the SRH model with slope (−1).

channel of the nanowire is observed in the heavily doped silicon layer when VFG = 0.8 V and the back-gate electrode is set to 0 V potential or VBG < 0 V. In contrast, an increase of inversion charge density is observed in the low-doped region of the NW when applying a positive back-gate voltage (VBG > 0 V), leading to the formation of a back inversion channel which, in turn, results in an increase of the overall conductivity of the nanowire due to the increased number of free electrons. Moreover, the application of the positive back-gate voltage for fabricated devices results in the shifting of the inversion-charge centroid position away from the front interface and closer to the low-doped part of the nanowire. The formation of a back inversion channel is clearly shown in Figure 2B, presenting the simulated transconductance behavior (gm) as a function of the front-gate voltage for different back-gate bias conditions in an n-channel inversion-mode transistor. Three-dimensional numerical simulations were performed for a 100 nm wide and 200 nm long Si TL nanowire similar to the one used in the experiment. The transconductance values presented in Figure 2B,C are normalized by their maximum values. Figure 2B clearly shows that at V BG = 0 V, the transconductance curve reveals a single peak corresponding to the front channel. As the back-gate bias is increased (VBG > 0 V), the additional peak in the transconductance starts to appear, confirming the formation of the back conductive channel. The position of the second transconductance peak is shifted significantly by back bias, reflecting the strong influence of back bias on the electrical and transport properties of the TL nanowire transistor. Figure 2C shows the experimental normalized transconductance curves obtained from the transfer characteristics depicted in Figure 1D. It should be noted that

that the liquid gate has a stronger influence on the transport properties of the Si NW structure due to thinner front-gate dielectric in comparison to the 145 nm thick BOX layer. It should be noted that the leakage current was negligible (below 100 pA) through both the front-gate dielectric and buried oxide during measurements. Figure 1D illustrates the measurement results of the drain current for the same 100 nm wide and 200 nm long Si nanowire at a constant drain-source bias of 100 mV and different values of liquid-gate and back-gate voltages. A schematic of the current−voltage measurements utilizing both gate electrodes is presented in Figure S1 of the Supporting Information. As can be seen from Figure 1D, applying a negative (opening) back-gate voltage results in a lateral shift of the I−V curve in the negative voltage direction, which reflects a decrease in the threshold voltage of the Si TL NW FET due to capacitive coupling between the liquid gate and the back gate.21,22 The effect is shown more clearly in the inset of Figure 1D, demonstrating drain current dependence on liquid-gate voltage in a semilogarithmic scale for different back-gate bias conditions. To investigate the influence of back-gate bias on inversion charge distribution in the Si TL NW FETs, we performed three-dimensional simulation using technology computer-aided design (TCAD) software. Figure 2A shows electron current density distribution in Si TL NW FETs in a rectangular cross section with a front-gate bias of VFG = 0.8 V and different applied back-gate voltages, VBG. It can be clearly seen that the back-gate bias strongly affects carrier distribution in the Si TL NW structures. In particular, a high-concentration region that corresponds to the front D


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of the time domain and the frequency domain analysis. The frequency domain analysis for the measured spectra can be performed by fitting eq 2 to the data in order to determine the corner roll-off frequency fc. At the same time, time domain analysis can be performed using the statistical histogram method.26 Corresponding amplitude histograms of the drain current time traces are shown in Figure 3C. Two Gaussian peaks are well-resolved, demonstrating the two-state switching kinetic of the drain current between two distinct levels: the low current level, which corresponds to the state when a carrier is captured by a trap, and the high current level, which corresponds to the empty state of the single trap. The height of each peak shows the probability of finding the system in a certain corresponding state. Therefore, the ratio between two Gaussian peaks corresponds to the relation between capture and emission characteristic times. Despite the partial overlap of the amplitude histograms associated with each telegraph level, the height of each peak can be determined with a high level of accuracy by fitting a histogram to two Gaussian distributions. The capture and emission time constants can then be estimated using the occupancy ratio τc/τe obtained from histograms together with the value of the corner frequency obtained from fitting the corresponding noise spectrum. The results of the analysis of the RTS noise are depicted in Figure 3D. The data demonstrate a weak dependence of emission time τe on the drain current, for example, the concentration of free electrons in the channel, while capture time τc depends on the drain current with a power law equal to −6.16. Such behavior of the characteristic times indicates an acceptor-type trap,27,28 for example, a repulsive center for nchannel enhancement mode Si TL NW FET, which is negatively charged when it captures an electron and becomes neutral after its emission back to the channel. It is also interesting to note that the strong dependence of capture time (γ = 6.16) clearly deviates from the one predicted by the SRH model and is explained within the Coulomb blockade concept,17−19,24,29,30 taking into account the trap screening due to the additional Coulomb interaction of the main carriers (electrons) with image charges. It should be emphasized that a similar behavior of RTS noise was observed for TL nanowires with different lengths and widths fabricated in the same technological run. The measured samples yielded the capture time τc dependence on the current with slope around (−6), reflecting a positive contribution of the highly doped layer to registered strengthening the dependence of capture time against drain current. This result is of major significance for the development of biosensors with high sensitivity, because it reflects a very strong relation between any surface potential changes caused by chemical or biological events that can be registered with enhanced sensitivity by monitoring changes in capture time as a characteristic of a single trap. C. Single-Electron Characteristic Times: Tuning Effect Revealed. As shown above, the capture time τc in the fabricated structures demonstrates a strong dependence on the drain current tuned by the liquid-gate voltage. However, the current through the fabricated nanowires can also be modulated by applying voltage to the substrate, which was used as a back-gate electrode (see schematic in Figure S1 of the Supporting Information). We utilized noise spectroscopy as a powerful nondestructive tool in the investigation of device performance. We were thus able to analyze the influence of the

the transconductance of the measured nanowire transistor exhibits behavior very similar to the simulation results depicted in Figure 2B. In particular, the additional peak in the transconductance curves was also observed when applying positive back-gate bias to the substrate, which was used as a back-gate electrode. The data therefore demonstrate that the application of back-gate bias for fabricated devices enables the inversion-charge carrier concentration distribution to be changed and reveal that the simultaneous utilization of both the liquid gate and the back gate can be effectively used for the precise tuning of the transport properties of fabricated Si TL NW FET devices. Under these conditions, single-electron tuning effect is revealed, as will be shown below. B. Single-Carrier Dynamics in Liquid-Gated Si TL NW FETs. In general, RTS noise in Si NW FETs is attributed to trapping/detrapping of a single carrier to/from individual point defect or trap in the oxide layer.12,14,23,24 Typical density of oxide traps for high-quality thermally grown oxide is of the order of 1010 cm−2 per energy window of kT (0.026 eV at 300 K).23 Using this value of trap density the gate area of the transistor containing a single trap is estimated to be approximately 0.1 × 0.1 μm2. This value is in a good agreement with experimental data obtained for fabricated TL NW structures. Figure 3A presents the typical drain voltage power spectral density (PSD) of a nanowire transistor with a single nanowire (width, 100 nm; length, 200 nm) measured in a PBS solution with pH = 7.4 at a constant drain-source bias of 100 mV and different liquid-gate voltages VLG. A low drain−source bias of 100 mV was applied to ensure a linear regime of operation of the transistor for the entire range of liquid-gate voltages applied, and the back-gate electrode was grounded during all noise measurements in this case. The noise spectra of the Si TL NW FET reflect a Lorentzian-shaped noise PSD with a characteristic frequency fc that shifts to higher frequencies with increasing liquid-gate voltage. Such noise behavior suggests the presence of an electrically active single trap located in the topgate dielectric layer, which is responsible for the RTS fluctuation processes. Indeed, two-level RTS noise with high amplitude was registered on time traces of the drain current. The drain current fluctuations in time domain experimentally recorded for different liquid-gate voltages are shown in Figure 3B. RTS noise demonstrates a strong dependence on the liquid-gate voltage. According to the Machlup’s derivation,3,25 the low-frequency PSD of a single two-level RTS noise for the interface between a uniformly doped semiconductor and a dielectric layer can be characterized by the average capture τc and emission τe times and by the RTS amplitude ΔI SI = 4(ΔI )2

(τcτe)2

1 (τc + τe) 1 + (f /fc )2 3

(2)

where fc is the corner roll-off frequency, which depends on both characteristic times as fc =

1 1 ijj 1 1 yz = jj + zzz j 2πτ 2π k τc τe z{

(3)

The emission time shows how long the system spends in the state when a carrier is captured by a trap, while the capture time corresponds to the period of time when the trap is empty. Both characteristic times can be obtained using a combination E


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Figure 4. (A) Drain voltage noise spectral density of Si NW FET multiplied by frequency f, measured at VLG = 1.75 V, VDS = 0.1 V and at different back-gate voltages VBG. (B) Histograms of the corresponding RTS drain current fluctuations. (C) Calculated τc/τe ratio as a function of overdrive liquid-gate voltage. The dashed lines represent a visual aid. (D) The RTS noise amplitude dependence on the liquid-gate voltage at different backgate voltages.

remains unchanged when applying back-gate voltage. This also demonstrates that RTS noise is caused by the single trap located in the top SiO2 layer. The calculated values of capture time as a characteristic time parameter of the single active trap is plotted versus drain current in Figure 5A. As can be seen from Figure 5A, the slope for the single-trap capture time as a function of drain current increases with increasing back-gate voltage, which also controls very effectively the channel current and carrier distribution in two layer nanowire structure. It should be noted that this effect was not previously reported in the literature for liquid-gated nanowire transistors. We modified the distribution of main carriers (electrons) along the thickness of the nanowire by applying back-gate voltage. Figure 5B reveals the linear dependence of characteristic slope (corresponding to the order of the power function in eq 1) on the back-gate potential for the range of the applied back-gate voltages. To demonstrate that the revealed effect is important for the development of new types of sensors, whose sensing principle is based on single-trap phenomena, we performed the following experiment. We measured the response of the TL NW sensors to the change of ionic strengths of the sodiumbased buffer solution. Electrolyte buffers with various ionic strengths were prepared by diluting of sodium-based stock solution (with ionic strength of 0.18 M) using deionized water. The composition of stock solution was the following: 0.14 M NaCl, 0.0027 M KCl, and 0.01 M PO43−. The pH value of all prepared solutions was 7.4. Sensing experiment was performed using both standard approach (by monitoring changes in drain current at definite working point) and single trap approach (by monitoring changes in capture time as characteristic parameter

back-gate potential on the single-trap parameters controlled by the liquid gate. Noise spectra measured for the Si TL NW FET (100 nm width; 200 nm length) at a constant liquid-gate voltage of 1.75 V and different back-gate voltages are depicted in Figure 4A in the form of drain voltage PSD multiplied by frequency f in order to compensate the 1/f flicker noise and provide better resolution of the RTS noise component. On such a coordinate scale, the value of the corner frequency fc corresponds to the maximum of noise PSD. Amplitude histograms of corresponding time traces are presented in Figure 4B. As can be seen in Figure 4A, the characteristic corner frequency fc demonstrates a weak dependence on the back-gate voltage. In contrast, significant changes in the τ c /τ e ratio obtained from corresponding histograms (see Figure 4B) were registered. The relation between capture and emission time as a function of overdrive liquid-gate voltage at different applied back-gate voltages is shown in Figure 4C. As liquid-gate voltage is increased, trap occupancy increases, meaning that the system spends more time in the state when the trap is full (negatively charged by captured electron). Therefore, the τc/τe ratio decreases with increasing liquid-gate voltage. Such trap reflects characteristic behavior for an acceptor-trap type in transistors with an inversion channel.28,31 It should also be noted that the applied back-gate voltage does not change the behavior (slope) of the τc/τe ratio. We can thus conclude that the RTS noise registered at different back-gate voltages was induced by one active trap situated in the top dielectric layer. The RTS amplitude ΔI calculated as a distance between two fitted Gaussian peaks,19,26 which correspond to two distinct RTS levels, is plotted versus liquid-gate voltage in Figure 4D. It can be seen that the amplitude of the RTS noise almost F


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Figure 5. (A) Capture time as a function of drain current measured at different back-gate voltages, VBG (V): 0; 1; 2, 3. (B) The characteristic slope γ corresponding to order of the power function in (eq 1) as a function of the applied back-gate voltage. (C) Sensor response to the change of ionic strength of the electrolyte solution in term of sensitivity extracted for standard approach ID/Imin D shown as dashed lines, 1 − VBG = 0 V; 2 − VBG = 3 V and for single trap approach τmax c /τc shown as solid lines, 3 − VBG = 0 V; 4 − VBG = 3 V. Single trap approach (lines 3 and 4) demonstrates pronounced fine-tuning effect enabling sensitivity enhancement compared to the standard approach.

utilization of single trap approach with fine adjustment of the parameters (see Figure 5A) for sensing applications. Thus, the revealed effect reflects the dynamic processes in the channel with significant tuning of capture time by applying back-gate potential. The observed phenomenon is extremely important for the development of new types of biosensors based on single-trap phenomena. The key aspect is that we are able to tune the sensitivity of the sensor, whose sensing principle is based on the single-trap phenomena. In turn, this may enable the real-time modification of the dynamic sensing range, which opens up new prospects for biosensing with novel operation principles and improved sensitivity. Therefore, the individual trap located near the interface between silicon and its oxide offers the opportunity for real-time and label-free biomolecule detection even at single-molecule-level sensitivity using fabricated silicon TL nanowires as transducers of chemical and biological events. To summarize, high-quality silicon TL NW FETs with characteristic sizes below 100 nm were fabricated and studied. The coupling-gate effect on carrier distribution and the electrical properties of designed and fabricated structures was investigated using both experimental results and numerical simulations. Liquid-gated devices demonstrated pronounced RTS noise with advanced characteristics that are favorable for many fields of research including biosensing. We investigated the impact of back-gate bias on the transport and noise properties of the Si TL NW FETs operated in liquid-gate configuration. We demonstrated that the utilization of the back-gate electrode enables the density of the carriers in the

of single trap). Obtained experimental results are presented in the Figure 5C. The decrease of the transistor’s drain current measured at VLG = 2 V and VBG = 0 V with decreasing of ionic strength of the gating solution (see line 1 in the Figure 5C) was registered. Such a behavior of drain current is the result of adsorption of negative ions (chloride Cl− and phosphate PO43− ions) on the nanowire surface. This causes the shift of threshold voltage in the positive voltage direction. The results are in a good agreement with literature.32 When we increased back-gate voltage to VBG = 3 V, a slight increase of sensors sensitivity (see line 2 in the Figure 5C) was observed. This also shows the positive role of dual-gate configuration for the sensing. At the same time, as can be seen in the Figure 5C (line 3) characteristic capture time changes more strongly in response to change of ionic strength compared to the changes of drain current (line 1 in the Figure 5C). It should be emphasized that slope of line 3 that corresponds to the sensing approach based on single trap phenomenon is considerably larger (approximately 5 times) than slope of the line 1 reflecting standard sensing approach when drain current is used as a sensing parameter. This fact demonstrates that changes of surface potential caused by changes of solution ionic strength is registered with enhanced sensitivity by monitoring changes in capture time as a characteristic of a single trap. Moreover, by applying back-gate voltage (VBG = 3 V) the slope considerably increases (see line 4 in the Figure 5C) reflecting a new effect which allows for the fine-tuning of the Si TL NW FET sensitivity. This result is a direct proof of the principle for G


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channel and carrier distribution to be modified. Under these conditions, a novel effect in silicon TL nanowire FETs is revealed and the nature of the effect is studied. The effect allows obtaining an enhanced single-trap kinetic with characteristic time behavior that can be fine-tuned. The back-gate bias can therefore be effectively utilized for fundamental studies of single-electron phenomena and applied research toward the fine-tuning of single-trap characteristics, which is very promising for biosensing applications in particular.

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REFERENCES

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ASSOCIATED CONTENT

S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.8b03508. (Figure S1) Schematic illustration of the liquid-gated Si two-layer nanowire FET. The schematic demonstrates the dual-gate measurement configuration when the backgate voltage VBG is applied to the Si substrate while the liquid gate VLG is applied via a Ag/AgCl reference electrode immersed into the solution. (Figure S2) Process flow for fabrication of Si TL NW FETs. Nanowire devices were fabricated at the Helmholtz Nanoelectronic Facility of Forschungszentrum Jülich (Germany) using top-down approach applied to 4-in. SOI wafers (PDF)

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Letter

AUTHOR INFORMATION

Corresponding Author

*Email: [email protected]. ORCID

Volodymyr Handziuk: 0000-0002-4344-0052 Svetlana Vitusevich: 0000-0003-3968-0149 Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS Y.K. greatly appreciates a research grant from the German Academic Exchange Service (DAAD). The authors would also like to thank Dr. Mihail Lepsa for his assistance with atomic layer deposition and Nils von den Driesch for his help with the epitaxy process. The authors are also grateful to all the technical staff of the Helmholtz Nano Facility (HNF) of Forschungszentrum Jülich for their assistance with device fabrication. Authors would like to express their sincere gratitude to the Innovation Award of RWTH Aachen University as part of RWTH transparent 2016.

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ABBREVIATIONS TL, two-layer; Si NW, silicon nanowire; FET, field-effect transistor; RTS, random telegraph signal; CMOS, scaled complementary metal-oxide semiconductor; SOI, silicon-oninsulator; TMAH, tetramethylammonium hydroxide; BOX, buried oxide; SEM, scanning electron microscope; TCAD, technology computer-aided design; PSD, power spectral density; SRH, Shockley−Read−Hall. H


Letter

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Liquid-Gated Two-Layer Silicon Nanowire FETs: Evidence of

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