NANO LETTERS
Low Operating Voltage Single ZnO Nanowire Field-Effect Transistors Enabled by Self-Assembled Organic Gate Nanodielectrics
2005 Vol. 5, No. 11 2281-2286
Sanghyun Ju, Kangho Lee, and David B. Janes* School of Electrical and Computer Engineering, Purdue UniVersity, West Lafayette, Indiana 47907
Myung-Han Yoon, Antonio Facchetti, and Tobin J. Marks* Department of Chemistry and the Materials Research Center, Northwestern UniVersity, EVanston, Illinois 60208-3113 Received August 20, 2005; Revised Manuscript Received October 4, 2005
ABSTRACT The development of nanowire transistors enabled by appropriate dielectrics is of great interest for flexible electronic and display applications. In this study, nanowire field-effect transistors (NW-FETs) composed of individual ZnO nanowires are fabricated using a self-assembled superlattice (SAS) as the gate insulator. The 15-nm SAS film used in this study consists of four interlinked layer-by-layer self-assembled organic monolayers and exhibits excellent insulating properties with a large specific capacitance, 180 nF/cm2, and a low leakage current density, 1 × 10-8 A/cm2. SAS-based ZnO NW-FETs display excellent drain current saturation at Vds ) 0.5 V, a threshold voltage (Vth) of −0.4 V, a channel mobility of ∼196 cm2/V s, an on−off current ratio of ∼104, and a subthreshold slope of 400 mV/dec. For comparison, ZnO NW-FETs are also fabricated using 70-nm SiO2 as the gate insulator. Implementation of the SAS gate dielectric reduces the NW-FET operating voltage dramatically with more than 1 order of magnitude enhancement of the on-current. These results strongly indicate that SAS-based ZnO NW-FETs are promising candidates for future flexible display and logic technologies.
Introduction. There is great current interest in fabricating nanowire-based field effect transistors (NW-FETs), with particular focus on approaches that can be employed with flexible substrates and inexpensive processing techniques. Conventional amorphous silicon thin-film transistors (aTFTs) and polysilicon thin-film transistors (poly-TFTs) have limitations such as low mobility, opacity, and incompatibility with plastic substrates.1-8 For example, the opacity of a-TFTs and poly-TFTs leads to inefficiency in active matrix array aperture ratios and increased power consumption in active matrix organic lighting-emitting diode (AMOLED) displays. For numerous electronic and optoelectronic device applications, the use of semiconducting nanowires offers the attraction of well-controlled device channels without the need for high-resolution lithography and with minimal process complexity. If suitable device and gate dielectric structures could be realized, then nanowire-based devices would also provide the means to achieve flexible electronic circuits and displays. ZnO nanowires are attractive as the active channel * Corresponding authors. E-mail:
[email protected]; t-marks@ northwestern.edu. 10.1021/nl051658j CCC: $30.25 Published on Web 10/19/2005
© 2005 American Chemical Society
material for flexible displays because of their excellent transparency and mechanical flexibility. Indeed, bulk ZnO is a promising material for many photonic and electronic applications because of its wide band gap (3.37 eV) and high exciton binding energy (60 meV). With these unique material properties in addition to the fundamental advantages of quasione-dimensionality, ZnO NW-FETs have attracted much interest, with recent demonstrations including sensors, transducers, solar cells, and optoelectronic devices.9-13 However, in addition to mechanical flexibility, reducing power consumption is a key issue in the developing flexible displays, and current levels of device performance, especially in terms of power consumption efficiency, indicate that significant improvements will be required for truly viable technologies. There are several key challenges that must be addressed in order to render NW-FETs suitable for low power applications, and to enable configurations such as flexible electronics. In addition to issues related to the integration of nanowires into device structures with high yields and wellcontrolled contacts, development of compatible gate dielectrics is a significant issue in realizing devices with high
Figure 1. (a) Cross-sectional view of the SAS-based ZnO NW-FET device structure (b) Type-III SAS structure and component building blocks: (i) R,ω-difunctionalized hydrocarbon chain, (ii) stilbazolium π-electron layer, and (iii) octachlorotrisiloxane capping layer.
performance and low operating voltages. Most nanowire transistors reported to date have utilized gate dielectrics consisting of either (i) a thermally grown oxide layer on a doped Si substrate, which requires high temperature processing and does not generally provide individually addressable devices or (ii) dielectric films deposited by sputtering or chemical vapor deposition, which can provide more arbitrary device connections, but have limitations associated with high temperature processing and control of interface states. The use of relatively thick thermal oxides also results in relatively low device currents in NW-FETs. One of the prerequisites to realizing flexible ZnO NWFETs with low power consumption would be a flexible gate insulator with high capacitance. Such an insulator is essential for efficient gate modulation in order to achieve low operating voltages and low-power consumption. A promising material that satisfies these requirements is a new class of nanoscopic self-assembled superlattices (SASs) that has been described recently.14 In this Letter, we report the realization of ZnO NW-FETs employing this organic gate insulator and demonstrate substantial performance enhancements over devices having conventional thick SiO2 dielectrics. Compared to ZnO NW-FETs with 70-nm SiO2 gate dielectrics, SASbased NW-FETs exhibit a reduction in operating voltage from 2.5 V to less than 1.5 V with comparable on-off current ratios and a greater than 1 order of magnitude increase in on-current (∼2.5 µA for SAS and ∼0.16 µA for SiO2 when VGS - VT ) 1 V). The measured transconductance and calculated mobility are also increased significantly. Other device metrics such as the on-off current ratio and subthreshold slope are ∼104 and 400 mV/dec. 2282
Experimental Details. ZnO NW-FETs devices using the SAS as gate insulators were fabricated on heavily doped n-type Si substrates (F ≈ 0.01 Ω cm). The device structure is a typical bottom-gate configuration as shown in cross section in Figure 1a. The SAS films used in this study consist of layer-by-layer self-assembled organic monolayers (“(Type III)3” multilayers) and were deposited on cleaned, heavily doped n-type Si substrates using procedures described elsewhere.14 The SAS dielectric material is composed of selfassembled multilayers that include the following building blocks (Figure 1b): (i) R,ω-difunctionalized hydrocarbon chains that block charge transport due to transverse crosslinking efficiently; (ii) highly polarizable stilbazolium layers that stabilize charge carriers in the channel with oriented π-electron dipoles; and (iii) glassy siloxane polymer layers that planarize the surface and enhance structural robustness by cross-linking and filling pinholes. Although the present study used doped Si as the gate, SAS materials can also be deposited on other surfaces, such as flexible plastics.15 Powdered ZnO nanowires (Nanolab Inc.)16-18 with 80 nm average diameter and 5 µm average length were used as the channel regions in the NW-FETs. The ZnO nanowires were dispersed in VLSI grade 2-propanol, and the dispersion was transferred onto the SAS-coated Si wafers. Aluminum metal for source-drain electrodes was next deposited by electron beam evaporation at ∼5 × 10-7 Torr with a thickness of 150 nm (deposition rate ) 0.1 Å /s), and the contacts were defined by conventional photolithography and lift-off processes. For comparison, devices were also fabricated using 70 nm thick SiO2 as the gate insulator. A field oxide (100 nm thickness) was employed under the probe pads in the Nano Lett., Vol. 5, No. 11, 2005
Figure 2. (a) Leakage current density and breakdown characteristics of an Al/SAS/Si structure. (b) Capacitance-voltage characteristics of an Au/SAS/Si structure. The inset shows the capacitance model.
SiO2-based devices to minimize leakage current, whereas low-leakage operation was obtained in the SAS-based devices without the use of a field oxide (Figure 2a). The small leakage current through relatively large area contact pads indicates that the SAS layer has a very low pinhole density as well as small leakage through the bulk layer. Individual ZnO nanowires were contacted with source and drain metal patterns, and devices containing single nanowires were imaged using field-emission (FE) SEM. Prior to device electrical characterization using a probe station with an HP 4156A precision semiconductor parameter analyzer, all NWFETs were electrically aged (Vgs ) 1.2 V and Vds ) 1.2 V for 10 s) to stabilize the I-V characteristics. Capacitancevoltage (C-V) measurements were performed on these metal-insulator-semiconductor (MIS) structures using an HP 4284A precision LCR Parameter analyzer. Results and Discussion.Prior to ZnO NW-FET fabrication, the leakage current, breakdown, and C-V characteristics of micrometer-scale metal/insulator/semiconductor (MIS) structures of evaporated Al/SAS/Si were investigated to Nano Lett., Vol. 5, No. 11, 2005
verify the properties of the SAS dielectric and its compatibility with the present photolithography and e-beam evaporation methodology, two common microelectronic fabrication processes. As shown in Figure 2a, the measured leakage current and breakdown field for the MIS structure are ∼1 × 10-8 A/cm2 at 1 V and 6-7 MV/cm, respectively. The C-V data in Figure 2b exhibit the typical high-frequency characteristics of n-type MIS capacitors, verifying that depletion and accumulation can be achieved in the semiconductor and that the SAS gate dielectric is completely compatible with standard lithography processes. As the dc bias is changed from negative to positive, the capacitance increases from a minimum (depletion/inversion) to a maximum value, with Ci ) 180 nF/cm2 (accumulation). In addition, note that the gate insulator consists of a ∼1-nm native SiO2 layer and a ∼15-nm organic multilayer. The calculated MIS effective dielectric constant, keff ) Ci × d/0, is therefore 3.0. Figure 3 shows a field-emission scanning electron microscope (FE-SEM) image of a ZnO NW-FET. The diameter and length of this ZnO nanowire is 130 nm and 2.1 µm, respectively. The drain current (Ids) versus drain-source voltage (Vds) characteristics of this device are shown in Figure 4a, exhibiting typical Ids-Vds characteristics of an n-type field-effect transistor. Ids increases linearly at low Vds and begins to saturate at higher Vds, whereas application of positive Vgs induces the accumulation of electrons near the nanowire-SAS interface, increasing the channel conductivity. The striking features of this ZnO NW-FET are its low operating voltages (∼1.5 V) and relatively high on-current (∼2.0 µA per ZnO NW at Vds ) 0.5 V, Vgs ) 0.5 V), which are essential for low-power applications. In contrast, a ZnO NW-FET device (NW diameter and length of 120 nm and 2.2 µm, respectively) using 70-nm SiO2 as the gate insulator (Figure 4b) has a high operating voltage (∼2.5 V) and low on-current (∼0.35 µA per ZnO NW at Vds ) 1.0 V, Vgs ) 1.2 V). These results clearly illustrate the excellent performance of ZnO NW-FETs fabricated with SAS gate dielectrics. The threshold voltage extracted from the Ids-Vgs plot (Figure 5a) by linear extrapolation is -0.4 V. This threshold voltage shift is believed to be due to the native SiO2 and inherent fixed positive charges in the SAS. Below the threshold voltage, Ids decreases exponentially as shown in a log Ids versus Vgs plot (inset in Figure 5a), with an on-off current ratio of ∼104, comparable to or smaller than that of ZnO NW-FETs reported previously.19-20 Another important device performance metric for high-speed and low-power operation is the subthreshold slope S ) dVgs/d log Ids (mV/ dec). A steep subthreshold slope, that is, smaller S, is desirable for ease of switching the transistor to an off-state. The theoretical limit of the subthreshold slope is ∼60 mV/ dec at room temperature, and subthreshold slopes of modern Si-based FETs approach this limit. The subthreshold slope extracted from the linear portion of the log Ids versus Vgs plot (Figure 5a) is ∼400 mV/dec. Finally, Figure 5b shows the transconductance, gm ) dIds/dVgs in the linear triode region (Vds ) 0.1 V), which peaks at ∼1.25 µS. The mechanisms responsible for the off-current and subthreshold slope can also be addressed. The relatively high 2283
Figure 3. FE-SEM image of a ZnO NW-FET (130 nm diameter; scale bar is 2 µm). The inset shows a top view of a fabricated device (scale bar is 200 µm).
off-current (∼1 nA) of the SAS-based ZnO NW-FETs is not due to the gate leakage current, which is measured to be ∼20 pA at 1 V, even in the absence of field oxide. A current turnover around -1.4 V, as shown in the inset of Figure 5a, is observed in many of the ZnO NW-FETs. Although the specific mechanism responsible for the high off-current is not known, possible mechanisms likely include the effects of nanowire-SAS interface states, which should be comparable to the effects of interface states in MOSFETs.21 High subthreshold slopes are usually due to either the existence of surface trap states, leakage current components that are not exponentially dependent on Vgs, or incomplete gating effects due to the cylindrical geometry of the nanowire. In conventional metal-oxide-semiconductor FETs, it has been shown that surface treatments on the SiO2 gate insulator, including HF, application of a plasma, hydrogenation, or annealing in N2 and H2 can reduce the density of interface traps and mobile charges and improve the subthreshold slope.22,23 To investigate the off-current and subthreshold behavior, SAS-based ZnO NW-FETs were exposed to 2-min ozone treatments, which are thought to increase the doping density via creation of oxygen vacancies24-27 and may reduce surface trap charge densities. The UV light used to generate the ozone was shielded to prevent possible degradation of the SAS. Following the ozone treatment, the devices exhibited a positive Vth (0.2 V), reduced off-current (∼0.1 pA) with an on-off ratio of ∼108, and an improved subthreshold slope of ∼150 mV/dec. The enhancement in overall device performance is attributed to modified electrostatic behavior due to changes in NW doping density and 2284
improved nanowire-SAS interfaces. Optimization of various surface treatments and annealing processes is currently in progress. The electron mobility of fabricated ZnO NW-FETs can be estimated from an Ids-Vgs plot (Figure 5a). There are several ways to extract the mobility of a nanowire device from the I-V characteristics.20,28 In this case, the mobility model for a planar metal-oxide-semiconductor FET, using an effective width to account for the cylindrical geometry, was used to extract the mobility of the ZnO NW-FET devices because the nanowire diameter is relatively large compared to the thickness of the gate insulator. The inversion layer will be formed only in the bottom 2-3 nm region near the SAS dielectric, and the bulk of the current flows through this region. Hence, a bulk device approximation can be utilized to calculate the mobility (eq 1). µ)
dID 1 L tox 1 dVG VD W m
(1)
Here keff ) 3.0 is the effective dielectric constant of the SAS and native SiO2 layers connected in series, tox ≈ 16 nm is the thickness of the gate insulator, L ≈ 2 µm is the ZnO NW channel length, and r ) 65 nm is radius of the ZnO NW. The geometry of the nanowire is approximated as a square cross-section with an area equal to that of the circular wire, resulting in an effective width of xπR2 ) 115 nm. In eq 1, m ) 6.67 (∼400/60; 400 mV/dec is the subthreshold slope for the ZnO NW-FET, and 60 mV/dec is the ideal minimum subthreshold slope). The subthreshold slope of Nano Lett., Vol. 5, No. 11, 2005
Figure 4. (a) Drain current (Ids) versus drain-source voltage (Vds) characteristics for a NW-FET with a SAS gate nanodielectric. (b) Drain current (Ids) versus drain-source voltage (Vds) characteristics for a NW-FET with a 70-nm SiO2 gate dielectric.
typical nanowire devices degrades because of interface traps present in the wire-insulator interface. This introduces an interface trap capacitance in addition to the oxide capacitance. Here, CIT ) (m - 1) Cox, and the mobility of the nanowire device is reduced by a factor of m because of the additional capacitance due to interface traps. The estimated electron mobility for the present ZnO NWFET device is ∼196 cm2/V s, which is far greater than the recently reported values for devices using thicker SiO2 dielectrics (8-18 cm2/V s).20,28 Other ZnO/SAS NW-FET devices exhibited comparable behavior, with performance varying with nanowire characteristics, such as diameter and channel length, as expected. The mobilities of other SAS NW-FETs are ∼164 cm2/V s for a device with a 160 nm diameter wire and 2.1 µm channel length and ∼181 cm2/V s for a device with a 140 nm diameter wire and 1.9 µm channel length. In contrast, the calculated mobility for the SiO2 NW-FET of Figure 4b is ∼54 cm2/V s. Extraction of channel mobility is complicated by the fact that it is not possible to independently determine channel carrier density and mobility exclusively from I-V data on individual devices. However, the high mobilities correspond to high Nano Lett., Vol. 5, No. 11, 2005
Figure 5. (a) Drain current (Ids) versus gate-source voltage (Vgs) for a NW-FET with a SAS gate nanodielectric. The inset shows log Ids versus Vgs. (b) Transconductance (gm) versus Vgs for a NWFET with a SAS gate nanodielectric.
on-currents observed in the SAS devices which cannot be fully explained simply by the higher gate capacitance per unit area of the SAS structure, which is ∼3.7 times that of the 70 nm SiO2 layer. In comparison, at the same normal electric field across the gate dielectric, the on-current of the devices having the SAS dielectric is about an order of magnitude greater than that in devices with a 70 nm thick SiO2 gate insulator. In calculating the gate electric field, it is assumed that the field is uniform throughout the thickness of the dielectric. Therefore, it is speculated that interfacial properties at the ZnO-NW/SAS juncture or the SAS piezoelectric properties may play an important role in the high on-current, either by stabilizing greater electron density in the ZnO-NW or by increasing the mobility in the channel. Experiments and electrostatic modeling to investigate these unique SAS gate dielectric properties are in progress. Conclusions. Single ZnO NW-FETs were fabricated using nanoscopic self-assembled superlattices (SASs) as gate insulators. From C-V and leakage current measurements, the compatibility of the SAS with conventional photolithography as well as its performance as a gate insulator are 2285
verified. To the best of our knowledge, this is the first report on the use of nanoscopic self-assembled dielectric materials as gate insulators for nanowire devices. Furthermore, because of the ∼15 nm thickness, the SAS gate dielectrics afford substantially reduced device operating voltages (∼1.5 V) and increased mobilities (∼196 cm2/V s). Therefore, it is expected that SAS gate dielectrics will enable low power consumption as well as mechanical flexibility for future display electronics. However, threshold voltage shifts and relatively low subthreshold slopes compared to conventional MOSFETs are observed because of inherent fixed positive charges in the SAS and the existence of native SiO2 between the SAS layer and the Si substrate. These effects should be addressed readily by optimizing annealing and surface treatment processes for SAS-based devices. The realization of lowvoltage, low-leakage devices and the potential compatibility with flexible and/or transparent substrates make the ZnO NW-FET devices excellent candidates for future flexible display and electronics applications. Acknowledgment. We thank the NASA Institute for Nanaoelectronics and Computing (NCC2-1363) and DARPA/ ARO (W911NF-05-1-0187, DAAD19-03-1-0138) for support of this research. We thank Prof. A. Alam and V. P. Ninad for helpful discussions. References (1) Ohya, Y.; Niwa, T.; Ban, T.; Takahashi, Y. Jpn. J. Appl. Phys. 2001, 40, 297-298. (2) Kwon, Y.; Li, Y.; Heo, Y. W.; Jones, M.; Holloway, P. H.; Norton, D. P.; Park, Z. V.; Li, S. Appl. Phys. Lett. 2004, 84, 2685-2687. (3) Hoffman, R. L.; Norris, B. J.; Wager, J. F. J. Appl. Phys. 2003, 82, 733-735. (4) Carcia, P. F.; McLean, R. S.; Reilly, M. H.; Nunes, G., Jr. Appl. Phys. Lett. 2003, 82, 1117-1119. (5) Nomura, K.; Ohta, H.; Ueda, K.; Kamiya, T.; Hirano, M.; Hosono, H. Science 2003, 300, 1269-1272. (6) McAlpine, M. C.; Friedman, R. S.; Jin, S.; Lin, K.-h.; Wang, W. U.; Lieber, C. M. Nano Lett. 2003, 3, 1531-1535.
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