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Low-Temperature Conformal Atomic Layer Etching of Si with a Damage-Free Surface for Next-Generation Atomic-Scale Electronics Po-Hsien Cheng,† Chin-I. Wang,† Chen-Hsiang Ling,† Chen-Hsuan Lu,† Yu-Tung Yin,† and Miin-Jang Chen*,†,‡ †
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Department of Materials Science and Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Road, Taipei, 10617, Taiwan, R.O.C. ‡ Graduate Institute of Electronics Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Road, Taipei, 10617, Taiwan, R.O.C. S Supporting Information *
ABSTRACT: Conformal atomic layer etching (cALE) of Si is realized on the basis of layer-by-layer self-limiting deposition and self-stop etching processes at low temperatures. In each cALE cycle, a conformal oxide layer was prepared by atomic layer deposition (ALD) on Si, resulting in the formation of an ultrathin SiOx interfacial layer between the oxide and Si. Afterward, the oxide and interfacial layers are removed by self-stop wet chemical etching, leading to the cALE of Si. The etching depth exhibits high linearity with respect to the applied cALE cycles, revealing a precise etching rate of a few angstroms per cALE cycle. The AFM measurement shows a low surface roughness after the cALE process as compared with other etching methods. Moreover, the evidence of conformal etching of cALE is provided by the TEM images of fin/trench structures. Also, the high-resolution TEM image demonstrates a smooth and damage-free Si surface after the cALE process. This layer-by-layer, conformal, self-limiting, self-stop, and damage-free cALE technique is highly beneficial to advanced semiconductor fabrication technology for next-generation atomic-scale electronics. KEYWORDS: atomic layer deposition, atomic layer etching, conformal etching, layer-by-layer etching, surface damage-free etching
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mechanisms.1−10,23 Therefore, both ALD and ALE are critical technologies to achieve atomic-scale f idelity in sub-10 nm semiconductor technology nodes.1−10 The ALE technique has been typically accomplished on the basis of the adsorption of halogens on surfaces, followed by ion bombardment of noble gases to remove a few layers of surface species.1,4−6,8−10,24−28 The positively charged ions are accelerated by the plasma self-bias or substrate bias, resulting in the directional (anisotropic) etching of plasma-based ALE.8,29,30 However, it is difficult to control the plasma bias precisely, and so the bombardment of overenergetic ions might result in surface damages.31,32 In addition, both isotropic and anisotropic etching techniques are important for the fabrication of complicated 3D structures in nanodevices.3,33,34 Therefore, the ALE technique capable of isotropic, conformal etching characteristics and free of plasma-induced damages is needed for high-quality atomic-scale electronics. In fact, the plasma-free Si ALE had been realized using chlorine adsorption at low temperatures and subsequent thermal desorption of SiCl2 over 650 °C.35,36 This etching process is basically isotropic(conformal) because both the chlorination and the
INTRODUCTION With the rapid evolution of Moore’s law down to sub-10 nm technology nodes, semiconductor technology has shifted from micro/nanoelectronics in the 1980s/2000s to atomic-scale electronics today.1−10 The critical dimension (CD) of devices and materials will soon reach less than a few nanometers, and the acceptable CD variation of Si < 5 Å is required.1,5,8 Hence, advanced semiconductor fabrication technology with atomic scale f idelity is crucial to achieve excellent materials and CD control of angstrom-scale accuracy.1,2,8 Scanning probe lithography has been used for high-precision material removal and modification.11−13 Although the scanning probe is capable of high spatial resolution, it is time-consuming to achieve largearea processing. Atomic layer deposition (ALD) has been an attractive technique to enable the deposition of atomic-scale materials.14−22 The self-limiting chemical reactions and the layer-by-layer process in ALD give a stable and wide window of process parameters, leading to a variety of benefits including accurate thickness control with angstrom-scale precision, excellent conformality, and step coverage on high-aspect-ratio structures, low defect densities, high uniformity over a large area, and low deposition temperatures.14−22 On the other hand, the counterpart of ALD is atomic layer etching (ALE), which is capable of removing a thin layer of materials with atomic accuracy because of sequential steps of self-limiting © 2019 American Chemical Society
Received: May 18, 2019 Accepted: June 14, 2019 Published: June 14, 2019 4578
DOI: 10.1021/acsanm.9b00944 ACS Appl. Nano Mater. 2019, 2, 4578−4583
Article
ACS Applied Nano Materials thermal desorption are independent of directions. However, the processing temperatures over 650 °C are detrimental to semiconductor process integration. Moreover, high-temperature processes give rise to the difficulty in process control and integration, such as the distortion of the fin shape and the metal degradation. For instance, the thermal oxidation rate of Si is lower at the convex/concave corners than that at the flat surface.37 The stresses at the corners are responsible for the retardation of thermal SiO2 growth. As a result, the nonuniform oxidation leads to distortion of the shape of Si fins fabricated by thermal oxidation and HF dip.38 Besides, TiN and TaN are used in the metal gate in advanced semiconductor technology nodes. The high-temperature processes above 600 °C result in severe degradation of TiN and TaN electrodes.39 Therefore, a conformal ALE technique at a lower processing temperature is highly demanded.3,40,41 In this study, we propose a novel low-temperature (≤300 °C), conformal ALE (cALE) approach based on etching away of the interfacial layer (IL) between the oxide and Si. Each cALE cycle comprises the IL formation and removal steps. First, ALD is used to deposit a conformal oxide layer upon Si 3D structures. Between the oxide and Si, an ultrathin SiOx IL is formed to meet the requirement of thermodynamic equilibrium.42,43 Afterward, the oxide and the IL are removed by wet chemical etching. Because Si is consumed by the formation of IL, etching away of the conformal IL leads to cALE of Si with self-limiting and self-stop characteristics. An accurate etching rate of a few angstroms per cALE cycle is achieved together with a high linearity between the etching depth and the applied cALE cycles. In addition, the wet chemical etching is free of plasma bombardment, resulting in a smooth and damage-free Si surface as revealed by atomic force microscopy (AFM) and high-resolution transmission electron microscopy (HRTEM) characterizations. The cALE of Si trench/fin structures shrinks the fin width while keeping the fin height, indicating the conformal feature of the cALE technique. As compared with conventional dry etching processes, the cALE technique can be applied to precisely tailor the channel width of Fin-FET(fieldeffect transistor) and the channel diameter of gate-all-around (GAA) transistors with atomic scale f idelity. Another advantage of cALE is the large-area capability that is due to the high uniformity of thin films prepared by ALD, which is essential to semiconductor manufacture.
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Figure 1. Schematic of one cycle of the cALE process: (a) An Al2O3 layer is deposited by ALD on a SOI substrate. (b) The Al2O3 and the interfacial layer (IL) are removed by a BOE solution. BOE with an immersion time of 20 s, measuring the thickness of the remaining top Si layer by a spectroscopic ellipsometer, and then putting the samples back into the ALD chamber for the next cycle of cALE process. The thickness of the remaining top Si layer of the SOI wafer after each cycle of the cALE process was obtained by the spectroscopic ellipsometer (Elli-SE, Ellipso Technology). Figure 2 shows the pseudo delta (Δ) and psi (Ψ) of the etched SOI wafer measured by the spectroscopic ellipsometer, along with the curve fitting to the data points using a three-layer optical model of the Si/SiO2/Si structure. It is seen that the fitting curves are in good agreement with the data points, and so the thickness of the top Si layer can be extracted precisely with an error sigma smaller than 2%. Supporting Information (Section 3) demonstrates that spectroscopic ellipsometry is sufficiently sensitive to probe the thickness variation of the material under test. The surface roughness was evaluated by the atomic force microscopy (AFM, NT-MDT Solver P47, SP-47). The samples for cross-sectional transmission electron microscopy (TEM) observation of the Si trench/fin structure were fabricated by the focused ion beam (FIB, Helios NanoLab 600i, FEI) system. Structural analysis of the Si trench/fin structure was carried out by the TEM (Tecnai G2 F20, FEI) with an acceleration voltage of 200 kV. The chemical bonding at the oxide/Si nterface was measured by XPS in a PHI VersaProbe scanning microprobe with standard Al Kα radiation at 1486.6 eV.
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RESULTS AND DISCUSSION Figure 3 shows the etching depth of Si versus the applied cALE cycles, where the etching depth was obtained by the thickness of the initial top Si layer minus that of the remaining one after the cALE process. The ALD process in each cALE cycle was performed with 10 and 50 ALD cycles at different temperatures of 200, 250, and 300 °C, respectively. As 10 ALD cycles were applied in each cALE cycle in the IL formation step, the etching depths were approximately identical for different ALD temperatures as shown in Figure 3a. During the initial stage of film deposition with a few ALD cycles, the oxide nucleates only at specific sites and so follows the island-like growth mode.44−46 In addition, because the physical thickness of the Al2O3 layer prepared with only 10 ALD cycle is less than 1 nm, oxygen in the atmosphere would diffuse across the Al2O3 layer toward the interface, resulting in the formation of IL after the sample was carried out of the ALD chamber. Therefore, the IL thickness is mainly determined by the ambient oxygen, leading to almost the same IL thickness. Thus, the etching depths are almost independent of the deposition temperature of ALD in each cALE cycle. On the other hand, Figure 3b shows the etching depth as a function of the cALE cycle with the IL formation step of 50 ALD cycles. A high linearity is seen between the etching depth and the applied cALE cycles. The
MATERIALS AND METHODS
Figure 1 shows the schematic process steps of the cALE cycle. In this study, the substrate is a silicon-on-insulator (SOI) wafer with a 150 nm buried oxide and a 70 nm top Si layer. The cALE cycle consists of the following processes: (a) The self-limiting IL formation step: An Al2O3 layer was deposited by thermal-mode ALD (Savannah, Cambridge Nanotech) on a SOI substrate. The precursor and reactant of aluminum and oxygen were trimethylaluminum (TMA) and H2O vapor, respectively. The pulse times of TMA and H2O were 0.04 and 0.01 s, respectively, and the purge times after the TMA and H2O pulses were 15 s. The self-limiting chemical reactions in ALD give rise to a uniform deposition/formation of the Al2O3 layer and the IL upon Si. The formation of the SiOx IL was confirmed by X-ray photoelectron spectroscopy (XPS) (Supporting Information, Section 1). (b) The self-stop IL removal step: The buffer oxide etching (BOE, 6 parts of 40% NH4F and 1 part of 49% HF) solution was used to remove the Al2O3 layer and the IL. The high selectivity of BOE between oxides and Si leads to the self-stop etching of the cALE process, as demonstrated in Supporting Information (Section 2). It took ∼10 min to perform the experimental procedures including taking the samples out of the ALD chamber, removing the oxide by 4579
DOI: 10.1021/acsanm.9b00944 ACS Appl. Nano Mater. 2019, 2, 4578−4583
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Figure 2. Ellipsometric data points and fitting curves of the SOI wafer using the Si/SiO2/Si three-layer structure: (a) Pseudo delta (Δ) and (b) pseudo psi (Ψ) as a function of the photon energy.
Figure 3. Si etching depth versus the applied cALE cycles, in which (a) 10 and (b) 50 ALD cycles were performed in the IL formation step at 200, 250, and 300 °C, respectively. (c) The etching rates per cALE cycle as a function of the deposition temperature of ALD, in which 10 and 50 ALD cycles were applied in the IL formation step, respectively.
etching depth increases with the ALD temperature from 200 to 300 °C, which can be explained by the increase of the IL thickness with the deposition temperature of ALD.47,48 A higher ALD temperature facilitates the dehydroxylation of surface −OH groups,44:49 −2OH → −O + H 2O
(1)
which results in a decrease of the density of surface −OH groups and provides oxygen at the surface.49 The diffusion of surface oxygen toward the interface contributes to the formation of a SiOx IL, producing a thicker IL and thus a higher etching rate at the ALD temperature of 300 °C. Figure 3c shows the etching rates per cALE cycle versus the ALD temperature, with 10 and 50 ALD cycles performed in the IL formation step, respectively. As the ALD temperature is below 250 °C, the etching rate of the cALE process with 10 ALD cycles is higher than that with 50 ALD cycles. This is attributed to the formation of a thicker IL due to the diffusion of ambient oxygen through the island-like oxide (10 ALD cycles) toward the interface. When the ALD temperature increases to 300 °C, dehydroxylation of surface −OH groups in the cALE process with 50 ALD cycles dominates over the diffusion from atmosphere oxygen in that with 10 ALD cycles. For the cALE process carried out with 50 ALD cycles at 300 °C, the etching rate is ∼0.95 nm per cALE cycle, which is in good agreement with the thickness of the IL between Al2O3 and Si reported in the literature.44 Figure 4 shows the Si etching depth as a function of the applied cALE cycles, in which the ALD process in each cALE
Figure 4. Si etching depth versus the applied cALE cycles, in which 10, 50, 75, and 100 ALD cycles, respectively, were performed in the IL formation step at 250 °C. As the ALD cycles are greater than 75, the etching depths/rates are almost identical, which can be understood from the saturation of the IL thickness due to the blocking of oxygen diffusion from the atmosphere by a thick Al2O3 layer.
cycle was performed with 10, 50, 75, and 100 ALD cycles, respectively, at a temperature of 250 °C. The etching depth/ rate decreases with an increase of the ALD cycles from 10 to 75, and then saturates as the ALD cycles is greater than 75 (the etching depths/rates are nearly identical for the ALD cycles of 75 and 100). When the Al2O3 thickness increases, the diffusion of ambient oxygen through the oxide toward the interface is suppressed. Hence the IL thickness decreases with an increase of the Al2O3 thickness, leading to a decrease of the etching rate of the cALE process. The almost identical etching depths/rates 4580
DOI: 10.1021/acsanm.9b00944 ACS Appl. Nano Mater. 2019, 2, 4578−4583
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ACS Applied Nano Materials might be ascribed to the saturation of the IL thickness as the ALD cycles are greater than 75, as a result of the blocking of oxygen diffusion from atmosphere by a thick Al2O3 layer. The suppression of oxygen diffusion by a thick oxide layer renders the cALE process independent of available oxygen from ambient air, leading to a self-limited process of the IL formation. A control experiment with “0 ALD cycle” (i.e., the ALD process was not performed in each cALE cycle) was also conducted to demonstrate the impact of native oxide (Supporting Information, Section 4). The result reveals that Si is hard to be consumed by the BOE dip without the ALD process for the IL formation. The very low but nonzero Si etching rate of the “0 ALD cycle” process might result from the formation of native surface oxide during exposure to atmosphere. Figure 5 shows the AFM morphologies of the Si surface after 1, 2, 5, and 8 cycles of the cALE process, in which 50 ALD
Table 1. Surface Roughness of Si Extracted from the AFM Morphologiesa sample/method 1 cycle of cALE 2 cycles of cALE 5 cycles of cALE 8 cycles of cALE RIE OX/BOE bare Si wafer
surface roughness (nm) 0.21 0.20 0.30 0.24 0.63 2.75 0.17
± ± ± ± ± ± ±
0.034 0.013 0.084 0.048 0.128 0.161 0.046
a
The tapping mode of the AFM operation was used to measure the root-mean-square surface roughness of the Si surface. The scanning area was 10 μm × 10 μm, and all of the samples were measured under the same operating conditions.
Figure 6. (a) Schematic of the cALE process of the Si fin/trench structure. (b) The cross-sectional TEM image of the Si fin/trench structure before the cALE process. (c) The cross-sectional TEM image of the Si fin/trench structure after the 6-cycle cALE process. (d) The high-resolution TEM image of the bottom corner of the Si fin after the 6-cycle cALE process. Clear crystal lattices near the Si surface indicates that the self-stop wet etching leads to the almost damagefree cALE process. The appearance of residues on the left/top side of fins might originate from the preparation of the carbon protective layer using electron-beam-induced deposition in the FIB system. The fluctuation (overshooting) of electron beam current at the initial (turn-on) stage may result in the damage of the carbon protective layer. Because the electron gun was tilted at 54 degrees with respect to the normal of the sample surface, the residues were present on the left/top side of fins.
Figure 5. AFM images of the Si surface after 1, 2, 5, and 8 cycles of the cALE process, in which 50 ALD cycles were carried out at 300 °C.
cycles were carried out at 300 °C. We also performed the Si etching process using the reactive ion etching (RIE, using CF4 gas at a radio frequency power of 50 W and a working pressure of 13.3 Pa for 1 min) and the BOE dip after the thermal dry oxidation of Si at 800 °C (abbreviated as the OX/BOE method) for a comparison. The roughness of the Si surfaces after the cALE, RIE, and OX/BOE processes are shown in Table 1. As compared with the cALE process, the Si surface roughness is much higher for the etching process performed by the RIE and OX/BOE methods. The Si surface roughness keeps a low value of only 0.212, 0.202, 0.304, and 0.239 nm after 1, 2, 5, and 8 cycles of the cALE process. The increase of the applied cALE cycles does not cause a significant increase of the surface roughness. The variation of the surface roughness might result from environmental instability of the cALE process when the sample was carried out of the ALD chamber and exposed to the air atmosphere. The low roughness of Si surfaces treated by the cALE process is ascribed to the selflimiting IL formation and self-stop IL removal steps in each cALE cycle. The conformal etching characteristics of the cALE technique are clearly demonstrated in Figure 6. Figure 6a illustrates a schematic diagram of the cALE process of a Si fin/trench
structure. Figure 6b shows the cross-sectional TEM image of the Si fin/trench structure before the cALE process, where the width and the height of fins were 72.40 and 78.73 nm, respectively. After 6 cycles of the cALE process (50 ALD cycles, 300 °C), the fin width was reduced from 72.40 to 60.88 nm, while the fin height remained the same of about 79.19 nm, as shown in Figure 6c. Also, it is seen that the aspect ratio of fins was increased by the cALE process. The result clearly reveals the conformal etching feature of cALE, attributed to excellent 3D conformality of ALD used for the IL formation step in each cALE cycle. Supporting Information (Section 5) schematically illustrates the conformal ALE process of a Si fin/ trench structure. Compared with the cALE technique, the OX/ BOE method tends to be anisotropic etching because of different oxidation rates at the smooth surface and at the convex/concave corners of Si fin structures.50 Thus, the nonuniform oxidation results in distortion of the shape of Si fins fabricated by the OX/BOE method. The high-resolution TEM image of the bottom corner of the Si fin after the 6-cycle cALE process is shown in Figure 6d. Well-defined and clear 4581
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crystal lattices are observed near the Si surface, demonstrating that the cALE process is almost free of damage due to the selfstop wet etching using the BOE solution, without plasma damage caused by the ion bombardment used in typical ALE methods. The distinguishing features of cALE are beneficial to the accurate control of critical dimension in Fin-FETs and GAA transistors.
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CONCLUSIONS The ALE of Si is realized using alternating procedures of the self-limiting IL formation and self-stop IL removal steps, giving rise to the conformal and layer-by-layer etching as revealed by the TEM and ellipsometric observations. The cALE technique possesses a precise etching rate of angstrom scale per cALE cycle and a high linearity between the etching depth and the applied cALE cycles. Because of the self-limiting deposition and the self-stop wet etching, the cALE process leaves behind a smooth and damage-free surface, which was confirmed by the AFM and HRTEM analysis. The cALE technique is a promising method to reach precise atomic scale f idelity for next-generation atomic-scale electronics.
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ASSOCIATED CONTENT
S Supporting Information *
The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsanm.9b00944. Si 2p XPS spectra of the samples after Al2O3 deposition and BOE dip, self-stop etching of Si by BOE, ellipsometric spectra of pseudo delta (Δ) and psi (Ψ) parameters of the sample after the IL formation step and after the IL removal step, a control experiment with “0 ALD cycle” to elaborate the impact of native oxide, and illustration of conformal ALE process of the Si fin/ trench structure (PDF)
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AUTHOR INFORMATION
Corresponding Author
*E-mail:
[email protected]. ORCID
Po-Hsien Cheng: 0000-0002-0897-3531 Author Contributions
M.J.C. conceived the idea and coordinated the project. P.H.C., C.I.W., C.H.L., and C.H.L. optimized the cALE process. Y.T.Y., and P.H.C. conducted the TEM characterization. M.J.C. and P.H.C. wrote the paper. All authors discussed the results and commented on the manuscript. Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS The authors acknowledge the partially financial support in part by Taiwan Semiconductor Manufacturing Company (TSMC) and the Ministry of Science and Technology, Taiwan (MOST 108-2218-E-002-028).
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REFERENCES
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DOI: 10.1021/acsanm.9b00944 ACS Appl. Nano Mater. 2019, 2, 4578−4583
