Low-Voltage and High-Performance Multilayer MoS2 Field-Effect

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Low-Voltage and High Performance Multilayer MoS Field-effect Transistors with Graphene Electrodes Arun Kumar Singh, Chanyong Hwang, and Jonghwa Eom

ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.6b12217 • Publication Date (Web): 29 Nov 2016 Downloaded from http://pubs.acs.org on December 4, 2016

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ACS Applied Materials & Interfaces

Low-Voltage and High Performance Multilayer MoS2 Field-effect Transistors with Graphene Electrodes Arun Kumar Singh1,2*, Chanyong Hwang 3 and Jonghwa Eom1 1

Department of Physics and Graphene Research Institute, Sejong University, Seoul 143-747,

Korea. 2

Department of Physics, Motilal Nehru National Institute of Technology, Allahabad-211004,

India. 3

Center for Nanometrology, Korea Research Institute of Standards and Science, Daejeon 305-

340, Korea. *Corresponding Author E.mail: [email protected]

ABSTRACT Atomically thin 2D materials are attractive because they have excellent material properties and channel length scalability. Fabrication of complex structures from these materials is also relatively easy. Accordingly, 2D such as molybdenum disulfide (MoS2) has been intensively studied because of their novel properties for advanced electronics and optoelectronics. This study realizes the low-voltage and high performance field-effect transistors with chemical vapor deposition-grown single layer graphene employed as the thinnest electrode and semiconducting multilayer (ML) MoS2 utilized as a channel material. The two terminal mobility of graphenecontacted ML MoS2 using 15 nm Al2O3 as the top-gate dielectric layer is 131.2 cm2/Vs at room temperature, which is higher than that of the previously reported metal/graphene-contacted MoS2. The result demonstrates that van der Waals bonding at the graphene–MoS2 interfaces and high-k dielectric provides an important step toward the realization of high-performance and lowvoltage thin-film transistors.

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KEYWORDS: molybdenum disulfide (MoS2), graphene, top gated field-effect transistor, mobility, transparent electrodes, low-voltage.


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INTRODUCTION Recent advances in nanoscale material characterization and device fabrication have opened up new opportunities for researchers all over the world to explore new semiconductors as an alternative to silicon, inorganic oxide semiconductors, and organic semiconductors in the manufacture of electronic and optoelectronic devices.1,2 Recently, two-dimensional (2D) materials have attracted significant interest for their unique electrical, optical, mechanical, and thermal properties. 1–3 The fascinating electrical and optical properties makes them attractive for their use in next-generation electronic and optoelectronic devices.1–3 Many 2D materials, including metallic graphene, semiconducting transition metal dichalcogenides (e.g., MoS2, MoSe2, WS2, and WSe2), and insulating boron nitride, have already been explored and used to make electronic devices, such as thin-film field-effect and tunnel transistors, sensors and biosensors, electroluminescent and photovoltaic devices.4–11 Furthermore, 2D materials offer optical transparency, excellent mechanical flexibility, and transport properties. These materials have attracted great interest for the realization of transparent and flexible electronic devices that can be placed on a wide variety of substrates.

MoS2 has sub-nanometer thickness and excellent switching current ratios, and it shows stability in air, no short-channel effect, absence of dangling bonds, and mobility, which is comparable to that of Si.6,12–14 One of the most common and promising applications of MoS2 is its use as a field-effect transistor (FET). Depending on the dielectric environment, FET that uses a single layer (SL) or bi-layer (BL) MoS2 on the SiO2 substrate has shown a room temperature mobility ranging from 0.1 to 60 cm2 V−1 s−1 using back-gated geometry and these value may improved using top-gated geometry.15–16 These transistor features may be attractive as next generation



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electronic switches for high-resolution liquid crystal and organic light-emitting diode (OLED) displays. Electronic switches have a critical need for field-effect mobility (>40 cm2 V−1 s−1) and on/off ratio (>103).13,

17

Nowadays, the multilayer (ML) MoS2 is more attractive for FET

applications than the SL and BL MoS2 because the SL MoS2 synthesis followed by deposition of an additional high-k dielectric layer may not be well suited for commercial fabrication processes. Furthermore, ML MoS2 synthesis using the chemical vapor deposition (CVD) technique is much easier than synthesizing SL MoS2 for large-area electronics.13 The density of the states of the ML MoS2 is three times that of the SL MoS2, which will lead to considerably high drive currents in the ballistic limit and comparably high mobility.13 The ML MoS2 also offers a wider spectral response from ultraviolet to near-infrared wavelengths than the SL MoS2, which may be advantageous in a variety of photodetector applications.18,19 Several reports have studied the properties of ML MoS2.12-14 However, the application of the ML MoS2 in electronic devices especially in dual or top gated based transistor with high-k dielectrics have not yet been well explored.

One of the most promising applications of graphene is its use as a transparent and conducting electrode material. Accordingly, graphene has high electrical conductivity, optical transparency, and flexibility.20,21 Large-area, high-quality graphene growth and easy transfer to any of the desired substrate are also some advantages of graphene. Graphene goes beyond conventional circuits because of its optical transparency and flexibility, which enable its use in flexible and transparent electronics, optoelectronics, sensors, electromechanical systems, and energy technologies.22–24 Transparent conducting electrodes have recently become an essential part of modern commercial electronic products.25 CVD-grown graphene-based source–drain electrodes


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have already been used for organic semiconductors and carbon nanotube transistors.26–28 These transistors perform much better than those that were previously made using metal electrodes (e.g., Au, Ag, and Cu) because of the low-contact resistance between graphene and organic materials.26–28 A flexible and transparent MoS2 transistor has also been made recently using graphene as source–drain electrodes.29 Y. T. Lee et al. have compared the graphene versus metals source/drain contact for MoS2 transistors and found that mobility is higher in case of graphene contacted MoS2 in comparison to metal contacted MoS2.30 Das et al. reported that all 2D flexible, transparent, and thinnest thin-film transistors of WSe2 have a mobility of 45 cm2/Vs.31 Recently, FETs have also been demonstrated by T. Roy et al. using 2D materials for all components, including MoS2 as channel material, hexagonal BN as top gated dielectric and graphene as electrodes.32 They have observed n-type behavior with electron mobility 33 cm2/Vs of this transistor.32 Nowadays, heterostructure devices are being made using different 2D materials. This development opens opportunities for memory applications, photodetectors, and tunnel and vertical transistors.32–36

Here we demonstrate the low-voltage and high performance dual gated transistors of ML MoS2 using the CVD-grown single-layer graphene (SLG) as source–drain electrodes. Large-area, highquality CVD-grown SLG and mechanically exfoliated ML MoS2 are employed as source–drain electrode and channel material, respectively. The CVD-grown SLG-contacted ML MoS2 exhibits n-type characteristics. The ML MoS2 transistor covered by 15 nm Al2O3 film shows high mobility of 131.2 cm2/Vs with a current on/off ratio of ~106 at room temperature. The graphenecontacted ML MoS2 show good two-terminal transport behavior than that of the previously reported metal/graphene-contacted MoS2.



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RESULTS AND DISCUSSION To fabricate the FET based on ML MoS2 as channel materials and graphene as source–drain electrode, the ML MoS2 flakes are mechanically exfoliated from bulk MoS2 crystals using Scotch tape. These flakes are subsequently transferred to SiO2 substrate with underlying highly p-doped silicon. The optical image of the ML MoS2 flakes is illustrated in Figure 1a. The ML MoS2 layers are identified through an optical microscope and Raman spectroscopy. The thickness of the MoS2 flakes measured using an atomic force microscope (AFM) is in the 7–8 nm range (Figure S1, Supporting Information). The CVD-grown SLG is transferred to the ML MoS2/SiO2/Si samples. Synthesizing the SLG using the CVD technique is discussed in the Methods. The samples were baked at 85 °C for 5 min to improve graphene adhesion. The CVD-grown graphene on the ML MoS2/SiO2/Si substrate is kept in acetone for 1 day to remove the polymethyl methacrylate (PMMA) layer from the graphene surface. Graphene is then rinsed in isopropanol. We also measured the thickness of CVD grown graphene by AFM and found to be 0.38 nm (Figure S2, Supporting Information), which reveals monolayer graphene. The large patterned electrodes (Cr/Au of 6/30 nm) are made through photolithography near the selected ML MoS2 same as discussed in our pervious paper.12,22,40 The CVD-grown SLG is made as a source–drain electrode by combining electron beam lithography and oxygen plasma etching. Graphene is a single-atom ultrathin material that is highly uniform, and defect free, which makes it a promising material for use as electrode.24 Furthermore, the inert chemical character of graphene minimizes the interfacial reaction and provides well-defined interfaces. The optical image of the fabricated device is presented in Figure 1b. A strip of the CVD-grown SLG was clearly distinguished through optical contrast (grayish purple) and indicated by white border lines in the figure. The graphene electrodes are connected to large patterned electrodes (Cr/Au of


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6/30 nm) at both ends to minimize the contact resistance and ensure a uniform potential landscape across the entire graphene contact.

The Raman spectra of the ML MoS2, CVD-grown SLG, and CVD-grown SLG on the ML MoS2 are demonstrated in Figure 1c. The Raman spectra of the ML MoS2 layers showed strong signals from both in-plane E12g and out-of-plane A1g vibrations that appear around 382.7 and 408.5 cm−1, respectively. The frequency differences between these two Raman modes, ∆, allowed for the quantification of the number of the MoS2 layers, ∆ was about 25 cm−1, which indicated the ML MoS2.12 The pristine SLG in the Raman spectrum had two characteristic peaks, namely, G and 2D peaks, which appeared around 1580 and 2690 cm−1, respectively. The G and 2D peaks appeared around 1590 and 2690 cm−1, respectively, for the pristine CVD-grown SLG. This result is similar to the values reported by other studies.37 The very small peak around 1347 cm−1 in the pristine CVD-grown graphene is the D peak or defect peak. The D peak is due to the A1g mode breathing vibrations of six-membered sp2 carbon rings, which are absent in defect-free graphene. The very small D peak intensity indicated the high quality of the CVD-grown SLG samples. The peaks of both the MoS2 and the SLG are observed in an overlapped (SLG/MoS2) region. The characteristic peaks of the MoS2 or the SLG did not significantly change when their Raman spectra are recorded in the overlapped (SLG/MoS2) region (Figure 1c; blue line). This result revealed that the electronic structure of graphene is not influenced by the underlying ML MoS2. The results of this study are consistent with data previously reported by other studies. [38] The Raman spectra in the channel region showed only peaks of the ML MoS2. No characteristic peaks of the SLG are observed. This finding confirmed that the SLG was absent in the channel region (Figure 1c; green line).



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A schematic depiction of the device is presented in Figure 2a. The performance of the graphenecontacted MoS2 back-gated FETs in vacuum at room temperature is first examined. The transport measurement devices are annealed before hand at 200 °C for 4 h in a flow of 100 sccm Ar and 10 sccm H2 to remove the residue and contamination. The drain current versus the drain–source voltage (IDS–VDS) and the drain current versus the back-gate voltage (IDS–Vbg) characteristics of the FET with the ML MoS2 flake as the channel material and the CVD-grown SLG graphene as the source–drain contact electrode are presented in Figure 2b and 2c, respectively. The IDS–VDS curve at various gate voltages, which ranged from −3 V to +3 V in 1 V steps, is illustrated in Figure 2b. The drain current of the graphene-contacted device is much higher than those of the previously reported Au-contacted ML MoS2 transistors in a particular voltage range.1,12 The drain current also reached saturation at a higher drain–source voltage. The same behavior is observed in many of the devices. Accordingly, other studies has reported the similar characteristics.29,32 This result is also a good sign from the transistors because the current saturation in a transistor is a vital characteristic for the real applications in OLED displays operated in the saturation region.13

The drain current is measured as a function of the applied Vbg at two different VDS = 10 mV and 20 mV (Figure 2c). The ML MoS2 transistor with graphene contacts exhibited a clear n-type characteristic with the current on/off ratio at ~104, which is similar to that of the metal source– drain contact electrodes. The IDS–VDS curve at various back-gate voltages in a small VDS voltage (i.e., from −0.5 V to +0.5 V) exhibited linear characteristics (inset, Figure 2c). The linear drain IDS–VDS characteristic of the devices showed good ohmic-like contact with the graphene source– drain electrodes. This result is consistent with previously reported results.30,39 Two terminal field-


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effect mobility of the graphene-contacted ML MoS2 (i.e., 71 cm2/Vs) is calculated from the transfer characteristics. The plot of IDS–Vbg at VDS = 0.01 V for the back-gated transistor is presented in Figure 2d. The field-effect mobility of the samples is extracted using the following relation:

µ=  ∂I where  DS  ∂V  bg

L C gWVDS

 ∂I DS   ∂V  bg

 ,  

(1)

  is the slope of the transfer characteristic of the device; L and W are the channel  

length and width, respectively; Cg is the gate capacitance of ~115 aF/µm2 for our Si/SiO2 substrate; and VDS = 0.01 V. The mobility of the graphene-contacted ML MoS2 is higher than that of the previously reported metal-contacted MoS2. The mobility of the graphene-contacted ML MoS2 is also higher than that of the other graphene-contacted MoS2 transistors.29–32  ∂I Transconductance ( g m ) =  DS  ∂V  g

  versus Vbg at VDS = 0.01 V is illustrated in the inset of Figure 

2d. The transistor mobility (i.e., 86.97 cm2/Vs) can be also extracted using the relation,

µ=

gm L , where the maximum value of gm is used. We have also calculated mobility of our C gWVDS

CVD grown SLG samples. The variation of resistivity as a function of gate voltage (Vg) of our CVD grown SLG is given in Figure S2 of supporting information. The Dirac point (charge neutrality point) of our CVD grown graphene is found around Vg = 6.8 V and the charge neutrality point close to zero gate voltage indicates the high quality of our sample.22,40 The    mobility of CVD grown SLG was estimated using relation µ =  1  ∂σ  , where σ is the ∂ C V g  g 



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conductivity of samples and Vg is the gate voltage. The electrons and holes mobility of CVD grown SLG was found to be 1233 cm2/Vs and 1381 cm2/Vs, respectively.

The high performance of the ML MoS2 transistors with the CVD-grown SLG source–drain contact has been demonstrated. This high performance of the graphene-contacted ML MoS2 is explained by the charge transport between graphene and ML MoS2. The energy band diagram of Si/SiO2/MoS2/graphene is shown in Figure 3. The pristine ML MoS2 is essentially an n-type semiconductor with an indirect bandgap of 1.2 eV. The SL MoS2 has a direct bandgap of 1.8 eV. By contrast, the CVD-grown graphene is a p-type (i.e., electron depleted). The electrons from the MoS2 conduction band move into graphene to align the Fermi levels of both graphene and MoS2 when the CVD-grown graphene make contact to MoS2. The work function of the CVD-grown graphene on the SiO2 substrate is 4.5 eV.41,30 The electron affinity of the MoS2 is about 4.0 eV. The lower work function of graphene compared with that of other electrode metals [e.g., Au (5.4 eV), Pt (5.9 eV), and Ni (5.0 eV)] provides a better charge injection because of the lower barrier formed at the graphene–MoS2 channel interface. The linear IDS–VDS characteristic of the devices shows good ohmic-like contact with the graphene source–drain electrodes in a low voltage regime. This finding supports the current study’s explanation. Ultrathin, highly uniform, defect free and the inert chemical character of graphene minimizes the interfacial reaction and provides well-defined interfaces with MoS2. Graphene is very much compatible to MoS2 and undamaged van der Walls bond provides atomically sharp and clean interface between MoS2 and graphene. The atomically thin and clean interface between MoS2 and graphene minimizes the defects and interface charge trapping states and prevents Fermi level pinning. However, these factors dominate in metal-contacted MoS2 system.

Another advantage of graphene as an


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electrode is that the Fermi level of graphene can be modulated by applying a back-gate voltage. Graphene becomes more electron-doped if a positive back-gate voltage is applied, which results in a lower or nearly zero barrier for the charge carrier and enhances the drain current as represented in Figure 3b. By contrast, graphene becomes more hole-doped if a negative backgate voltage is applied, which results in a higher barrier for the charge carrier as shown in Figure 3c. This finding may be one of the reasons why the graphene-contacted ML MoS2 FET has a higher current than those of the reported metal-contacted MoS2 devices.1,12,42 Therefore, the CVD-grown SLG provided a potentially unique feature over metal contacts.

Semiconductors are known for their use in fabricating logic/integrated circuits. One of the crucial requirements for building a logic/integrated circuit based on 2D materials is the ability to control the charge density in a local manner independent of a global back gate. Accordingly, top-gated transistors are fabricated. The ML MoS2 flake channel is covered with 15-nm-thick Al2O3 as the top-gate dielectric and Cr/Au (6/80 nm) as the top-gate electrodes. Previously W. Yang et al reported that the direct deposition of Al2O3 on MoS2 surface is not feasible. However, uniform and thin deposition of Al2O3 on MoS2 layer is possible by applying oxygen plasma pretreatment prior to atomic layer deposition (ALD).43 We have also exposed our ML MoS2 samples by oxygen plasma before deposition of 15 nm Al2O3 by ALD technique. The performance of the top-gated ML MoS2 transistors is plotted in Figure 4. The measurement devices were annealed again before hand at 200 °C for 4 h in a flow of 100 sccm Ar and 10 sccm H2 to remove the resist residue and contamination. The cross-sectional view and the optical image of the top-gated ML MoS2 transistor are presented in Figures 4a and 4b, respectively.



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The electrical characteristics of the top-gated transistors in vacuum at room temperature are measured. These transistors are characterized by applying drain–source voltage and measuring the current at different back-gated voltages after Al2O3 deposition as an insulating layer (Figure 4c), during this measurement top gate was grounded. The current is slightly higher than that of the back-gated transistors. However, the saturation characteristics are not significantly affected. The transfer characteristics of the top-gated ML MoS2 at two different VDS (i.e., 10 and 20 mV) with are demonstrated in Figure 4d. In this condition back gate was grounded. The device exhibited the current on/off ratio of 106. The maximum on-current is 3.5 µA at VDS = 20 mV for +5 V of Vtg. The IDS–VDS characteristics at low drain bias voltages (0.5 V) with different top-gate voltages Vtg are also measured. The result indicated that graphene made ohmic-like contact with the ML MoS2.The inset of Figure 4d reveals the large degree of current control in the device when the local gate voltage is applied.

The plot of IDS–Vbg at VDS = 0.02 V of the ML MoS2 transistor after Al2O3 deposition is presented in Figure 4e. The device is measured by sweeping the back gate voltage with top gated disconnected and in this situation effective gate capacitance is top gate capacitance as suggested by M.S. Fuhrer et al. 44 The device mobility (i.e., 131.2 cm2/Vs) is significantly increased after 15-nm-thick Al2O3 deposition. Mobility is estimated using above relations with considering top gate capacitance per unit area Ctg , which is calculated using the relation Ctg = ε 0ε r / d , where ɛr is dielectric constant (ɛr= 6.4) and d is the thickness of Al2O3 . The high and effective fieldeffect mobility may be due to the suppression of Coulomb scattering in the high k dielectric environment. 6 The inset of Figure 4e shows gm versus Vbg at VDS = 0.02 V of the ML MoS2 transistor after Al2O3 deposition. The transistor mobility (i.e., 142.9 cm2/Vs) can be also


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calculated using transconductance data following the preceding relation, µ =

gm L ,where the CtgWVDS

maximum value of gm was utilized. We have also measured the mobility of other devices (device S#2) by using same method and found to be 122.6 cm2/Vs (see Figures S3 of supporting information). The performance (i.e., high output current, on-current, high mobility and low operation voltage) of the CVD-grown SLG-contacted ML MoS2 transistors is better than that of the metal-contacted MoS2 transistors. The high carrier mobility is due to dielectric mismatch between nanoscale semiconducting material and surrounding environment. Higher dielectric constants of surrounding environment generally suppress the Coulomb scattering and surface roughness in nanoscale material (below 10 nm thickness). The transistor mobility is higher than that of the other 2D nanomaterials (e.g., WS2, WSe2, and MoSe2).1,2 The device mobility is also much higher than that of the transistors based on low-dimensional Si, CdS, and organic semiconductors.28,45,46 Charge carrier mobility is an important parameter for determining the power dissipation and switching speed of the devices.

CONCLUSIONS This study realizes the use of FETs with mechanically exfoliated ML MoS2 as the conducting channel and high-quality CVD-grown SLG as the source–drain electrodes. The charge transport characteristics exhibit an n-type conduction in the CVD-grown SLG-contacted ML MoS2. Moreover, the two terminal field-effect mobility of the ML MoS2 nanoflake is 71 cm2/Vs and can be boosted up to 131.2 cm2/Vs using 15 nm Al2O3 as the top-gate dielectric environment. The mobility of the graphene-contacted ML MoS2 is higher than that previously reported for metal-contacted MoS2, low-dimensional silicon, WS2, ZnO, CdS, and organic semiconductors. This result demonstrates that van der Waals bonding at the graphene–MoS2 interfaces provides 13 ACS Paragon Plus Environment


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an important step toward the realization of high-performance and low-power thin-film transistors. The combination of 2D materials (i.e., graphene and MoS2) has a great potential in shaping future electronic devices. This work would also attract new interest in large-area nanoelectronic and optoelectronic devices based on CVD-grown graphene and MoS2.

METHODS Sample preparation. The ML MoS2 films were obtained using micromechanical exfoliation.

These films were subsequently transferred to the MoS2 layers onto a silicon substrate with 300 nm oxide layer following the discussion in our previous paper.12 The Si/SiO2 wafer was treated with piranha solution (3:1 sulfuric acid to hydrogen peroxide) for 30 min to remove the residual organic contaminants before transferring the MoS2 layers. The thickness of the ML MoS2 was measured using an atomic force microscopy. The ML MoS2 had ~10 mono layers. The large-area, high-quality SLG film (99.8% pure) was grown through thermal CVD on 25 µm thick mechanically polished and electropolished copper foils from Alfa Aesar. The CVD chamber was evacuated to ~10−4 Torr. The temperature rose to 1010 °C with H2 gas flow (~10−2 Torr). Both 20 sccm CH4 and 5 sccm H2 were injected into the furnace for 8 min to synthesize graphene after the temperature stabilized at 1010 °C. The sample was cooled down to room temperature at a 50 °C/min rate. The Raman spectra were collected at room temperature using a Renishaw micro-spectrometer with a laser wavelength of 514 nm.

Device fabrication and measurements. The large patterned electrodes with 6/30 nm Cr/Au

thickness for the ML MoS2 films were made using standard photolithography. The CVD-grown SLG was transferred to the Si/SiO2/ML MoS2 samples using the same method discussed in our previous report.22 The source–drain electrodes were patterned by employing e-beam lithography 14 ACS Paragon Plus Environment

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and oxygen plasma etching. The channel length indicated by the black lines in Figure 1b and width are ~1.5 and ~3 µm, respectively. Unwanted graphene was removed using oxygen plasma etching. The 15-nm-thick layer of Al2O3 was deposited using atomic layer deposition (ALD). The Lucida™ D series NCD water-based ALD with trimethyl aluminum precursor was used to grow the Al2O3 film. The chamber pressure and the substrate temperature were kept at 1.3 Torr and 120 °C, respectively, during the Al2O3 film growth. ML MoS2 samples were exposed by oxygen plasma for 60 second before deposition of Al2O3 layer by ALD technique. The top-gated electrodes were patterned by employing e-beam lithography and evaporation of Cr/Au (6/80 nm).The contact resistance of the devices was minimized after fabrication by annealing the devices in a tube furnace at a temperature of 200 °C in a flow of 100 sccm Ar and 10 sccm H2 for 4 h. The devices were electrically characterized using Keithley 2400 source meter and Keithley 6485 picoammeter at room temperature in vacuum. All electrical measurements were performed in vacuum at room temperature.

Conflict of Interest: The authors declare no competing financial interest.



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Acknowledgments-

This research was supported by the Nano-Material Technology Development Program (2012M3A7B4049888) through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT, and Future Planning. This research was also supported by the Priority Research Center Program (2010-0020207) and the Basic Science Research Program (2013R1A1A2061396) through the NRF funded by the Ministry of Education. Dr A. K. Singh also acknowledges to Department of Science and Technology (DST), India for support.

Supporting Information Available

The Supporting Information is available free of charge on the ACS Publications website or from the author.


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Figure captions Figure 1. a) Optical image of the mechanically exfoliated ML MoS2 (indicated by white arrow line) on the SiO2/Si substrate. b) Optical image of the fabricated device, CVD-grown SLG as the source–drain electrode, and ML MoS2as the channel material. c) Raman spectra of the CVDgrown SLG and ML MoS2.Color black denotes the Raman spectra of the pristine ML MoS2 before the CVD-grown SLG is transferred. Color red denotes the Raman spectra of the CVDgrown SLG on the SiO2/Si substrate. Color blue denotes the Raman spectra of the CVD-grown SLG on the ML MoS2.Color green represents the Raman spectra collected in the channel region.

Figure 2. a) Cross-sectional view of the graphene-contacted MoS2 transistor. b) Plot of the drain current versus the drain–source voltage (IDS–VDS) of the ML MoS2 transistor at different Vbg ranging from −3 V to +3 V in 1 V steps. c) Plot of IDS–Vbg of the ML MoS2 transistor at two different VDS (0.01 and 0.02 V). The inset shows a plot of IDS–VDS at different Vbg ranging from −3 V to +3 V in 1 V steps in a VDS range of −0.5 to +0.5 V. d) Plot of IDS–Vbg of the ML MoS2 transistor before Al2O3 deposition. The inset shows transconductance (gm) versus Vbg at VDS = 0.01 V. The maximum value of gm is used to estimate mobility.

Figure 3. (a) Schematic band profile of Si/SiO2/MoS2/graphene system before contact, (b) schematic band diagrams of Si/SiO2/MoS2/graphene with gate voltage Vg > 0 and (c) schematic band diagrams of Si/SiO2/MoS2/graphene with gate voltage Vg < 0. Figure 4. a) Cross-sectional view of the top-gated ML MoS2 transistor. b) Optical image of the fabricated top-gated ML MoS2 transistor. The device comprises CVD-grown SLG as the source– drain electrodes. The ML MoS2 is covered with 15 nm of ALD-deposited Al2O3 acting as a gate dielectric and Cr/Au with 5/80 nm for the top-gated electrodes. c) Plot of IDS–VDS of the top-


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gated ML MoS2 transistor at different Vbg ranging from −3 V to +3 V in 1 V steps. d) Plot of IDS– Vtg of the ML MoS2 transistor at two different VDS (0.01 and 0.02 V). The inset shows a plot of IDS–VDS at different Vtg ranging from −3 V to +3 V in 1 V steps in a VDS range of −0.5 to +0.5 V.

e) Plot of IDS–Vbg of the ML MoS2 transistor after Al2O3 deposition. The inset shows gm versus Vbg at VDS = 0.02 V. The peak value of gm is used to estimate mobility.



Pristine ML MoS2

(c)

CVD grown SLG SLG on MoS2 Channel region

Intensity (a.u.)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

360 390 420 1200 1800 2400 3000 -1

Raman Shift (cm )

Figure1


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30 (b) -6

IDS (10 A)

(a)

Vbg = -3V to +3V

20 10 0 0

0.10 (d)

-10

10

4

4

Vbg = -3V to +3V

-6

-6

IDS (10 A)

8

0 -4 -8 -0.6 -0.3

-6 -4 -2 0 2 Vbg (V)

0.0 0.3 VDS (V)

4

0.6

2.0

0.08

VDS= 0.01 V

1.5

-8

VDS= 0.02 V

-8

-9

2 3 VDS (V)

VDS= 0.01 V

10 10

1

gm (10 S)

(c)

IDS (10 Amp)

-7

10 IDS (A)

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0.06

1.0 0.5 0.0 -6 -4 -2 0 2 Vbg (V)

0.04 0.02

4

6

VDS= 0.01 V

0.00

6

-6

Figure 2


-4

-2

0

2 Vbg (V)

4

6


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Figure-3


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Figure 4



Table of Content

-5

10

-7

10 IDS (A)

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-9

10

-11

10

VDS= 0.01 V

-13

10

-6

-4


-2

0 2 Vtg (V)

4

6

Low-Voltage and High-Performance Multilayer MoS2 Field-Effect

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