Low-Voltage-Operating Transistors and Logic Circuits Based on a

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Low-Voltage-Operating Transistors and Logic Circuits Based on Water-Driven ZrGdOx Dielectric with Low Cost ZnSnO Bing Yang, Gang He, Li Zhu, Chong Zhang, Yongchun Zhang, Yufeng Xia, Fakhari Alam, and Zhaoqi Sun ACS Appl. Electron. Mater., Just Accepted Manuscript • DOI: 10.1021/acsaelm.9b00110 • Publication Date (Web): 22 Mar 2019 Downloaded from http://pubs.acs.org on March 26, 2019

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ACS Applied Electronic Materials

Low-Voltage-Operating Transistors and Logic Circuits Based on Water-Driven ZrGdOx Dielectric with Low Cost ZnSnO Bing Yang,†§ Gang He,* †‡ Li Zhu,† Chong Zhang,† Yongchun Zhang,† Yufeng Xia,† Fakhari Alam,† and Zhaoqi Sun† †School

of Physics and Materials Science, Radiation Detection Materials & Devices

Lab, Anhui University, Hefei 230601, P. R. China ‡Institute

of Physical Science and Information Technology, Anhui University, Hefei

230601, P. R. China §School

of Mechanical Engineering, Anhui Vocational and Technical College, Hefei

230011, P. R. China

ABSTRACT ： In current work, the nontoxic eco-friendly water-induced (WI) gadolinium doped zirconium oxide (ZrGdOx) gate dielectrics have been integrated with low cost spin-coating-driven ZnSnO films for thin film transistors (TFTs) and logic circuits with superior performance for the first time. High transmittance over 90% and the formation of the metastable cubic phase of Zr2O have qualified its potential application in transparent electronics. 430oC-annealed ZnSnO films integrated with ZrGdOx films demonstrate remarkable electrical properties and low voltage operation (2 V), including high current on/off ratio of ~1.1×106, large saturation carrier mobility of ~3.1 cm2V-1S-1, extreme low leakage current density of 6×10-10 A cm-2 and a slight shift in threshold voltage of 0.26 V for bias stability, respectively. To verify the practicability in logic circuits, the resistor-loaded inverters are built by using ZrGdOx/ZnSnO TFTs. This work firstly put forward and verify the 1

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WI gate dielectrics can be well favorable to heterogeneous clean interface with solution-derived ZnSnO channel layer, which takes an important step towards low operating voltage and eco-friendly flexible integrated circuit. KEYWORDS: high-k gate dielectrics; thin film transistor; electrical properties; inverter; spin-coating

1. INTRODUCTION Amorphous metal oxide (AMO) thin film transistors (AMOTFTs) have attracted great interests as a pixel switching for transparent flexible electronics, which possess superior

optical transparency, outstanding carrier mobility as well as fine

environmental

stability.1 Nowadays the In-based TFTs built by some simple

processes, such as dip-coating, ink jet printing, spin-coating, and spray pyrolysis, have gained notable achievement on electrical properties.2 However, expensive price and rare content in the earth for In-based AMOTFT restrict its application in industry. Sn-based metal oxide semiconductors, which have the similar electronic configuration with In-based oxides, may become the potential candidates.3 Previous experiments have proved that the low cost ZnSnO (ZTO) TFTs have demonstrated the optimized electrical performance after annealing processing with the temperature exceeding 500oC, which is a limitation for flexible electronic devices.4,5 Therefore, various innovation approaches have emerged to reduce the annealing temperature, such as solution self-combustion,6 redox chloride elimination reaction,7 photochemical activation,8 and annealing in O2/N2/O3.9 Shan et al introduced perchloric acid (HClO4) to clear away the chlorine ion in precursor by the redox chloride elimination reaction, 2


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the ZTO/ HfO2 TFTs treated by HClO4 exhibit mobility of 13.2 cm2V-1S-1 at the annealing temperature of 350oC, which is the reported highest saturation mobility for ZTO/HfO2 TFTs by far.7 However, it not only needs complicated chemical reaction, but also some new impurity elements have been induced. Compared with the traditional vacuum-based fabrication method, the advantage of solution spin-coating approach lie in its low cost and easy controlling, which has became a convenient way to explore optimal process conditions. In comparison with the TFTs integrated on conventional SiO2/SiNx gate dielectrics, recent achievements have demonstrated that oxide-based high-k dielectrics and their mixtures,10-19 have conspicuous effect to reduce the operating voltage due to the enhanced capacity coupling between the channel layers and gate dielectric layers. Among these high-k materials, ZrOx has attracted more attention due to its appropriate band alignment and high dielectric constant of 22. Currently, some researchers have been enthusiastic about improving ZrOx-based or GdOx-based TFTs and gained obvious progress by spinning coating.20-23 Liu et al even fabricated ZnO/Gd2O3 TFTs at room temperature via pulse laser deposition.24 By combining ZrO2 and Gd2O3 together, it is possible to design a kind of excellent ternary gadolinium zirconium oxide dielectric film with respective advantages. As mentioned references above, some toxic material such as 2-methoxyethanol (2ME) are often used as organic solvent to obtain these high-k gate dielectric films. There is no doubt that the additional additives may result in environmental pollution and enhanced manufacturing cost. Consequently, the eco-friendly water-induced (WI) 3



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method can undoubtedly accelerate industrialization process. it can be noted that some researchers have been fanatical about WI In-based and various dielectric films recently.

25,26

Unfortunately, when water is decanted into ZnSnO solution, Sn(OH)Cl

white precipitate may generate while the SnCl2 precursor solution occurs hydrolysis. That’s why no one pays attention to the full WI ZnSnO TFTs by far. However, Huang et al successfully fabricated ZnSnO/Al2O3 TFTs based on a small amount addition-water-driven ZnSnO and 2ME -derived Al2O3 and proves that the interface between organic solvent and water can be effectively regulated.

27,28

From another

perspective, it can be speculated that the WI high-k dielectric is compatible well with 2ME-ZnSnO channel layer. Thus this innovative investigation based on the 2ME-ZnSnO/WI-ZrGdOx TFTs can reduce environmental pollution to some extent compared with fully organic solvent solution. Meanwhile, the reported devices based on fully organic solvent solution are always fabricated at high annealing temperature more than 500oC, which limits its application on flexible integrated circuit. However, the water induced gate dielectric thin films are easy to form heterogeneous clean interface, which is beneficial

to the rapid transmission of electrons. Therefore, the

ZnSnO/WI-ZrGdOx TFTs may be prepared at a lower annealing temperature. In current work, 2ME-induced ZnSnO films annealed at 430oC with the employment of eco-friendly WI ZrGdOx dielectric layer are creatively integrated as TFTs. The integrated ZrGdOx/ZnSnO TFTs demonstrate outstanding electrical properties, containing high saturation carrier mobility (μsat) of 3.1~2.9 cm2V-1S-1, high high current on/off ratio (Ion/Ioff) of 3.3×105~1.1×106, respectively. Low leakage 4


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current value of 6×10-10 A cm-2 and a slight shift in threshold voltage (△VTH = 0.26 V) for bias stability has been detected. Finally, the resistor-loaded unipolar inverters based on ZrGdOx/ZnSnO TFTs are built. Acceptable maximum gain of 7.3 has been obtained for 560oC-annealed TFTs, which surpasses those of In-based TFTs.26

2.EXPERIMENTALS DETAILS 2.1 Preparation and Characterization of Precursor Solution. The 0.2 M ZnSnO precursor solution was prepared by dissolving a mixture of tin chloride dihydrate （SnCl2•2H2O）and zinc acetate dihydrate (Zn(CH3COO)2•2H2O) in 2-ME, and the molar ratio of Zn/Sn was 1:1. The WI ZrGdOx precursor (0.1M) solution was dissolving by gadolinium nitrate hexahydrate (Gd2(NO3)3·6H2O) and zirconium chloride octahydrate (ZrOCl2·8H2O) in deionized (DI) water, with high molar ratio (10:1) for Zr/Gd. By magnetic stirring for 6 h, the transparent solutions were obtained at room temperature. All the solutions were kept in the moister buster cabinet for at least 24 h before spin coating. Then, the thermogravimetric analysis (TGA) was used to explore the thermal behaviors of the ZnSnO and ZrGdOx solution. 2.2. Film Spin-coating and Characteristics. Firstly, the heavily-doped p++ Si wafers were cut into pieces of 12mm × 12mm for gate electrodes and substrates of TFTs, these wafers experienced RCA process of cleaning, the homogeneous WI ZrGdOx solution was spin-coated on the hydrophilic wafers at 3000 rpm for 20 s. Then the samples were baked on a hot plate at 180oC for 10 min. The same operating procedure was repeated for two times to achieve suitable thickness. After treating the samples in a UV oven for 40 min to accelerate the evaporation of organic solvent in 5



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the films, the samples were respectively annealed at 460oC, 510oC, 560oC, 610oC in air atmosphere for 1h. The relative important parameters, including thickness, transmittance spectra, microstructure, and the chemical compositions of the ZrGdOx annealed at different annealing temperatures were obtained by spectroscopy ellipsometry, ultraviolet visible spectroscopy (UV–vis), X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), respectively. 2.3. Device Integration and Characterization. The 2ME-driven ZnSnO films were spin-coated at 6500 rpm for 15s on the as-prepared ZrGdOx samples, the control-variable method was adopted to choose the optimum annealing temperature of ZnSnO layer among 380oC,430oC,480oC. Subsequently, the thermal evaporation was used to define the drain and source aluminum electrodes on samples with channel width (W) and length (L) of 1000 and 100 μm by a shadow mask. The integrated capacitors and TFT devices were explored by the impedance analyzer (Keithley E4990A) and semiconductor device analyzer (Keithley 2636B and Agilent B1500A), respectively. For comparison, various dielectric layers such as SiO2, 2M-ZrGdOx , WI-ZrO2 have been prepared at the same experiment condition and characterized. The saturation carrier mobility (μSat) were extracted by the following formula,

sat 

2 L  I DS 2 ( ) WCi VGS

(1)

where VGS represents the voltage adding between source and gate electrodes. IDS represents measured saturation current. The Ci represents the measured areal

6


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capacitance in MOS capacitors. The L and the W represent the channel length and the width, respectively. The interface state density (NSmax) was obtained by the formula below, SS 

kTln10  e 2 max  1  N s  e  ci 

(2)

where SS represents the subthreshold swing, it equal to inverse of slope which can be obtained by the VGS with increasing IDS, the e represents charge of electron ,the k represents the Boltzmann constant.

3. RESULTS AND DISCUSSION 3.1. ZnSnO and ZrGdOx Precursor Solution Characterization In general, most metal ions will undergo dissolution, hydrolysis and condensation in organic solvent or water solution. To explore the thermal decomposition properties of ZnSnO and ZrGdOx samples, TGA was proceeded and demonstrated in Figure 1. For ZnSnO xerogel, the initial decrease in weight below 150oC can be attributed to the evaporation of residual solvent.29 The continued reduction in weight between 150°C to 360°C can be ascribed to the dihydroxylation.30 No significant weight loss can be noted above 360oC, suggesting that the xerogel is fully transformed into ZnSnO metal oxide. So the minimal annealing temperature is supposed to start from 380oC in current work. Different with ZnSnO, the weight of ZrGdOx xerogel keeps reducing due to the dehydroxylation with the increased annealing temperature.31 The transformation of the ZrGdOx solution to Zr-Gd-O oxide slowed down at 460°C, implying that the optimal annealing temperature for ZrGdOx gel can start from 460oC.

3.2. Optical Properties and Microstructure Analysis 7



To explore the potential applications in transparent displays, the water-induced ZrGdOx was spun on quartz and the transmittance spectra is demonstrated in Figure 2. It can be observed that all the films demonstrate high transmittance of ~90% in the range of visible wavelength and indicate possible application in transparent electronic devices. With the increase of the annealing temperature, the slight increase from 5.08 to 5.26 eV in the band gap has been observed as shown in the inset of Figure 2. When annealing the samples at 460oC, the defects in the samples may generate an abundance of localized state and lead to the reduced band gap. When the annealing temperature has been increased to 560oC, the eliminated oxygen vacancies may reduce the localized states related defects in the films and the increased band gap can be obtained, further verified by following XPS and NSmax results. To explore the crystallization process related with the annealing conditions accurately, XRD measurements were implemented and demonstrated in Figure 3. It can be noted that there is no apparent peak for the ZrGdOx sample annealed at 410oC, demonstrating the formation of the amorphous nature of ZrGdOx films. However, for the 460oC-annealed sample, three obvious peaks attributed to (111), (220), and (311) plane of Zr2O have been observed. It can be concluded that 460oC is the critical point of crystallization transformation for ZrGdOx thin films. The intensities for all the peaks has enhanced with increasing the annealing temperature. Generally speaking, with the increased annealing temperature, the crystal phase of ZrO2 ranges from baddeleyite to tetragonal ZrO2 (P42/nmc), and finally stabilizes at cubic phase of ZrO2 (Fm3m).32,33 This is a reversible phase transition and the metastable phase Zr2O 8


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is only stable in some special cases.34 However, the doping of Gd3+ can replace Zr4+ to combine with oxygen and form substitutional solid solution. As a result , the reducing oxygen is benefit to get the metastable phase Zr2O not stable ZrO2. Nevertheless, the incorporation of Gd is too less to detect by XRD. Zhang et al observed the existence of stable R31m-Zr2O phase structure and explored the excellent elastic properties and the higher hardness. The better mechanical properties of Zr2O than ZrO2 can be explained by crystal orbital Hamilton population.35 The formation of cubic phase Zr2O with better mechanical behavior in ZrGdOx thin films guarantee its potential application in flexible electronics.

3.3. Chemical Bonding States Analysis XPS measurements were used to further explore the relationship between chemical bonding states and annealing temperature.36 The peak located at 284.8 eV of C 1s was used to as the reference to calibrate the experimental results. The atomic ratio of the samples annealed at 460, 510, and 560oC can be respectively expressed as ZrGd0.096O2.08, ZrGd0.092O2.26, and ZrGd0.1O2.35 via quantitative calculation. As shown in Figure 4a, three fitting peaks located at 530.1, 531.2, and 532.2 eV can be separately attributed to oxygen in oxide lattices, the oxygen vacancy , and hydroxide species on the surface (OI, OII, OIII represent respectively the percentages of each component).25 With the increase in the annealing temperature from 460 to 560oC, the percentages of OI increase, while the fraction of OII and OIII decreases, suggesting that rising processing temperature is conducive to eliminate hydroxide species and the oxygen vacancy, and help to enhance metal-oxygen lattice as demonstrated in Figure 9



4b. 37 As we know, the percentages of oxygen vacancy in dielectric layer should be as less as possible on account that it usually generate defect states in the forbidden band, which results in the poor leakage current capacity and the deteriorate integrated devices performance.38 For the reported pure ZrO2 sample, the Zr 3d3/2 and Zr 3d5/2 are centered at binding energies of 184.6 and 182.2 eV.37 However, the corresponding peaks shift to lower binding energy of 184.4 and 182.0 eV for 460oC-annealed WI ZrGdOx films as displayed in Figure 4c. which is attributed to the donating electrons from Zr-O to Gd-O bonds.26 The Zr 3d peaks shift towards lower binding energy with the annealing temperature changing from 460 to 560oC, which is due to the formation of the metastable phase of Zr2O and the reduced coordinate number in films.38 Figure 4d indicates that the Gd element is successfully incorporated into ZrO2 films. The slight shift of Gd 3d XPS spectra towards the higher binding energies sides has been detected at higher temperature, which can be explained by the decreased Gd2O3 and the formation of ternary compound ZrGdOx.39,40

3.4. Dielectric Properties and Leakage Behavior To investigate the dielectric properties and leakage behavior of WI ZrGdOx dielectric layers at various annealing temperatures, the Al/ZrGdOx/Si gate stack capacitors were prepared.41 Figure 5a demonstrates the frequency dependent areal capacitance and Figure 5b demonstrates the corresponding dielectric constant dispersion. The areal capacitance of ZrGdOx samples annealed at 460oC, 510oC, 560oC, and 610oC are calculated to be 360, 515, 532, and 280 nF/m2 at 20 Hz, as shown in Figure 5a, 10


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respectively. As a reference, the areal capacitance of WI-ZrO2 and 2ME-ZrGdOx thin films annealed at 560oC are calculated to be 600 and 517 nF/m2 respectively. In low frequency region, the increased areal capacitance of ZrGdOx samples annealed from 460 to 560oC can be ascribed to thermally induced dehydroxylation and the larger capacitance of the metal oxide in comparison to metal hydroxide.42,43 Nevertheless, when the increasing temperature arrive at 610oC, an apparent reduction in the areal capacitance has been found, which results from the formed low-k silicates in interface region.44 The thickness of ZrGdOx samples annealed at 460oC, 510oC, 560oC, 610oC are measured as 13, 16.1, 18.1, 25.1 nm, The thickness of WI-ZrO2 and 2M-ZrGdOx thin films annealed at 560oC are measured as 17.3 and 16.8 nm. Based on Figure 5b, the corresponding constants (k) as a function of annealing temperature have been calculated to be 5.39, 9.37, 10.96, and 7.74. In low annealing temperature, the increased k value can be attributed to the reduction of metal hydroxide with low capacitance.43 The dielectric constants (k) of WI-ZrO2 and 2ME-ZrGdOx samples are calculated to be 11.7 and 9.73, respectively. The leakage current density and electric field characteristics of the Al/ZrGdOx/Si MOS capacitors are investigated to explore the leakage behavior, which is shown in Figure 6. For the sample annealed at 460oC, the leakage current density is as high as 5.7×10-4 A/cm2 at 1 MV/cm, implying the existent amounts of leakage current paths, which results from partial decomposition of hydroxyl groups.45 The leakage current density of samples annealed at 510 and 560oC have reduced to 1.8×10-8 A cm-2 and 6×10-10A cm-2 respectively, which may arise from the complete decomposition of 11



hydroxyl groups. However, as the annealing temperature increases to 610oC the increased leakage current of 3.3×10-7A cm-2 has been dramatically observed, which can be caused by the formation of the crystallization-induced grain boundaries.46 Consequently, the 510-560oC annealed ZrGdOx dielectrics behave excellent leakage current property and may benefit to build the high-performance TFTs. Additionally, it also can be noted that the poor leakage current density of the 560oC annealed 2ME-ZrGdOx and WI-ZrO2 dielectrics are 2.1×10-8 A cm-2 and 7.4×10-9A cm-2 . For the 2ME-ZrGdOx gate dielectric layer, an abundance of interface defects generating from organic solute may restrain the electronic transmission and degrade the electrical properties. For WI-ZrGdOx dielectric layer, little defects generate from the organic-free solute and the electronic-clean interface are formed. For WI-ZrO2 gate dielectric layer, the observable WI-ZrO2 films is very poor and covered with pores. Dramatically, the uniform WI-ZrGdOx films with high-performance can be fabricated at the same experiment conditions. Except that it contributes to form a stable Zr2O phase aforementioned, the doping of Gd3+ can effectively increase the break electric field from 2 MV/cm to 7 MV/cm, this is due to the fact that the incorporation of Gd3+ can change the size and shape of the oxygen ion migration channel in the substitution process, which is benefit to reduce the lattice defects and improve the electronic transmission. 42

3.5. Electrical Performance of Integrated TFTs Based on previous investigation, the WI ZrGdOx samples with good leakage behavior and excellent dielectric properties are chosen as the gate dielectric of the 12


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ZrGdOx/ZnSnO TFTs, as shown in the inset of Figure 7a. To pursue the optimized annealing temperature parameters for 2ME-derived ZnSnO channel layer and WI-ZrGdOx dielectric layer, the controllable variable method has been adopted. For the 2ME-derived ZnSnO channel layer, based on TGA results, the starting annealing temperature of 380oC is selected. The output characteristics of ZrGdOx/ZnSnO TFTs with a low VGS of 2 V are observed in Figure 7a. Meanwhile, obvious current saturation and pinch-off voltage imply the as-fabricated TFTs with typical n-type. For 380oC-annealed ZrGdOx/ZnSnO TFTs, a low saturation current has been detected, which is attributed to the fact that the chloride groups have not decomposed fully. The increased saturation current at 430oC and 480oC-annealed ZrGdOx/ZnSnO TFTs is ascribed to the complete dehydroxylation reaction and the increased formation of Zn-Sn-O metal oxide. Figure 7b displays the typical double-sweep transfer characteristics of ZrGdOx/ZnSnO TFTs with an drain voltage (VDS) of 1.5 V . Additionally, the extracted critical parameters containing the μsat, Ion/Ioff, the threshold voltage (VTH), the subthreshold swing (SS), and calculated NSmax are listed in Table 1. It is noted that the increase in μsat and Ion/Ioff values and reduction in SS , VTH , NSmax values with the increase of the annealing temperature from 380 to 430oC. The higher temperature is beneficial to decomposition of hydroxyl groups and the formation of thermally-activated metal oxides framework. Meanwhile, it can annihilate defects located at bulk and interface region. So the ionized carrier electronics can transform rapidly and the improved performance can be observed. However, increasing the annealing temperature from 430 to 480oC, it is noticed that the decrease in μsat and 13



Ion/Ioff values and increase in SS, VTH , NSmax values. The amorphous ZTO undergoes the crystallization transformation at higher annealing temperature simultaneously,28 the larger amount of interface trap states resulting from grain boundary inhibit the transmission of induced electronics and degrade the device electrical performance.47 Consequently, the annealing temperature of 430oC can be selected as the optimized annealing temperature for ZnSnO channel layer, which overcomes the main bottleneck that the ZnSnO films need higher annealing temperature more than 500oC. Taking the chosen 430oC-derived ZnSnO films as the channel layer, the ZrGdOx/ZnSnO TFTs have been fabricated with the annealing temperature for ZrGdOx layer changing from 460 to 560oC and the extracted TFTs parameters are also summarized in Table 1. It is noted that the Ion/Ioff has markedly increased when the annealing temperature of ZrGdOx increases from 460 to 560oC. For 460oC-processed TFTs, the higher mobility of 3.4 cm2V-1S-1 is obtained at the expense of the low areal capacitance (360 nF/m2). The poor Ion/Ioff of 5.3×103 and large NSmax imply the existed undecomposed hydroxide and nitrate groups in interface region. These defects may result in an unavoidable static power consumption as well as device performance degradation. When the annealing temperature increases from 510 to 560oC, the μsat has experienced a slight decrease from 3.1 to 2.9 cm2V-1S-1, while the Ion/Ioff value increase from 3.3×105 to 1.1×106 simultaneously. The increased Ion/Ioff can be attributed to the reduced off-state current and the formation of dense metal oxide films. As we know, the small SS value imply the low trap defects generated in interface. The lower SS value (91 and 92 mVdec−1) for 510 and 14


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560oC-annealed ZrGdOx/ZnSnO TFTs is closing to our previous reported value (80 mVdec−1),26 which closely approximates the theoretic limit (60 mVdec-1). In consequence, with a wide annealing temperature window ranging from 510 to 560oC for WI ZrGdOx, the integrated ZrGdOx/ZnSnO TFTs will get further exploration. Based on all the measurements from ZrGdOx/ZnSnO TFTs, it can be concluded that the improvement in μsat for ZrGdOx/ZnSnO TFTs is mainly determined by the annealing temperature of the channel layer. When the annealing temperature is above 430oC, the μsat exceeding 2 cm2V-1S-1 can be obtained. While for the value of Ion/Ioff, it is not only determined by the annealing temperature of high-k gate dielectrics, but also influenced by the annealing temperature of the channel layer. Only the annealing temperature for dielectrics surpassing 510oC, the higher Ion/Ioff more than 105 can be observed. As a reference, the measured transfer and output curves of 2ME-derived 430oC ZnSnO/SiO2 TFTs are displayed in Figure S1(Supporting Information). Some important electrical parameters from ZnSnO/SiO2 TFTs have been extracted and shown in Figure S1b. In spite of the acceptable Ion/Ioff value of 1.4×106, the calculated μsat is as low as 0.98 cm2V-1S-1 at high voltages of 40 V by employing the low dielectric constant of SiO2, which inhibits the achievements of low power consumption and high-performance devices. By replacing SiO2 with the ZrGdOx dielectric, the μsat has obtained a remarkable improvement from 0.98 to 3.1 cm2V-1S-1, which can be ascribed to the thermally-activated high area capacitance of ZrGdOx sample and WI electronic-clean interface. As far as we know, such a mobility exceeds the reported highest values for 15



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solution-based ZnSnO-based TFTs (indicated in Table 2). According to the multiple-trap-and release model, Lee et al confirmed the larger carrier mobility can be attributed to the higher capacitance of high-k gate dielectrics.48 According to variable range-hopping (VRH) percolation model, the overlapping of the spherical s-orbitals in ZnSnO channel layer provides an efficient transport path for transporting carrier.49 However, a mass of localized states located at the forbidden band may hinder the transmitting of electronics, the induced electrons have to fill the localized states between the energy gaps before participating in the conducting transport. The higher annealing temperature is benefit to eliminate the related localized states. Meanwhile, the thermally-activated electron can easily liberate from the constraints of neighboring cation ions. Hence, the enormous electric field-induced electrons quickly fill the lower-lying localized states. Then, the extra excited electrons will take up the upper-lying localized states. As a consequence, the transporting electrons can easily hop to the neighboring conducting along the percolating–conduction path and lead to the enhanced electron mobility.50 For the 2ME-derived high-k gate dielectric layer (Figure 8a and Figure 8c), a abundant of interface defects generating from organic solute may restrain the electronic transmission and degrade the electrical properties, which is marked in black. For WI ZrGdOx

dielectric layer

(Figure 8b and Figure 8d), little defects generate from the organic-free solute and the electronic-clean interface are formed. The mass of induced electrons can rapidly fill in the lower localized states, so the extra electron can occupy the higher localized states. Consequently the formed percolating-conduction path can be shorten by 16


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rapid transmission of electrons, which leads to the enhanced μsat. On the other hand the heterogeneous clean interface is benefit to the rapid transmission of electrons, so the ZnSnO/WI-ZrGdOx TFTs with a lower operating voltage of 2 V can be prepared at a lower annealing temperature of 430oC in comparison to previous reports (indicated in Table 2). As a reference, 2ME-derived 430oC ZnSnO integrated 560oC 2ME-ZrGdOx and 560oC-derived WI-ZrO2 as TFTs have been constructed and the measured transfer and output curves of the TFTs are shown in Figure S2. Some important electrical parameters have been extracted and shown in Table 3. Obviously, the ZnSnO/WI-ZrGdOx TFTs process the optimized electrical properties among them. It also can be noted that the non-negligible hysteresis and the low Ion/Ioff of 2×104 for WI-ZrO2 TFTs have been found, which is caused by degraded leakage performance of WI- ZrO2 with amounts of pores. For 2ME-ZrGdOx TFTs, a large number of carriers can be captured by interface defects and change the electric field, thus an apparent larger VTH can be observed, which is in accord with the above-mentioned explanation.37

3.6. Bias Stability Characterization As the main building of integrated circuits, the stability of TFTs is crucial to the backplane electronics for active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs). To explore the stability of the ZrGdOx/ZnSnO TFTs, the positive bias stress (PBS) measurements were carried out by applying a constant gate bias of 1.5 V for 5400 s in air ambient, as demonstrated 17



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in Figure 9a. The relationship between extracted △VTH and stress time is revealed in Figure 9b. It has been noticed that 560oC-driven ZrGdOx/ZnSnO TFTs demonstrates an outstanding performance, including a slight △ VTH of 0.26 V, the almost unchanged SS and parallel VTH shift. These excellent stability can be attributed to the less defects located at the interface, which is verified by previous low NSmax value. Beside, a high Ion/Ioff of 108 observed demonstrate the superior electrical performance of TFTs. There are four suggested origins of PBS instability including defect creation model,51 charge injection model,52 charge trapping model,53 oxygen adsorption model.54-56

The fourth model is usually used to explain the origin of the △ VTH.

Based on Bae's reports, it can be seen that the escaped precursor during annealing is prone to generate amounts of porous matrix structures, which tends to adsorb oxygen in the ambient.57 So electrons in the exposed back-channel can be captured by oxygen or oxygen-related molecules when PBS is carried out, which can be written as: O2+e-→O2-

(3)

Therefore, the positive gate voltage can speed up the reaction. Consequently, the O2 in the ambient can deplete electron carriers in the ZnSnO layer and lead to a positive shift of ΔVTH.58,59 Charge trapping model is often used to explore the correlation between stress time(t) and ΔVTH . The relationship between them follows the stretched exponential model,60

18


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ΔVTH

t     ΔVTH 0 1  e  τ   

β

   

(4)

where β is the stretched exponent. τ represents the characteristic trapping time . For the fitting, ΔVTH0 was set directly to be equal to Vstress–VTH0, where VTH0 is equal to the VTH at t = 0 s.61 The well matched exponential model for 560oC-drived ZrGdOx/ZnSnO TFTs has been detected and shown in Figure 9b, indicating that electronic trapping assumption is the decisive mechanism for increasing ΔVTH. For comparison, the PBS test for 510oC-annealed ZrGdOx/ZnSnO TFTs has also been carried out ( Figure S3 in the Supporting Information). Obviously, the degraded electrical properties has been observed. Compared to that of 560oC-processed ZrGdOx/ZnSnO TFTs, the increased △VTH of 0.95 V indicates the existence of more defect states located at the interface.

3.7. Resistor-Loaded Inverter Based on the previous measurements and analyses, it can be concluded that the current ZrGdOx/ZnSnO TFTs demonstrate improved electrical performance, including the increased mobility and the lower operating voltage of 2 V. In spite of the excellent electrical properties, the possible industrial applications for complicated integrated circuits are always ignored in earlier publications.37As the fundamental switching unit of integrated circuits (ICs), the resistor-loaded inverter integrated by ZrGdOx/ZnSnO TFTs has been fabricated and investigated. Figure 10a displays the representative voltage transfer characteristic (VTC) curves. The detected output high voltage (VOH) and output low voltage (VOL) approaches the VDD and 0 V, respectively. Therefore, it can be concluded that the resistor-loaded inverter 19



demonstrates the full swing characteristics. From Figure10b, it can be noted that the monotonous increase in the voltage gain (−∂Vout/∂Vin) has been found with the increased VDD. As the key parameter of inverter, the maximum voltage gain of ∼7.3 has been obtained for VDD at 2.5 V, which is sufficient to drive the next stage component in a logic circuit.62 Another key index is noise margin which is always used to evaluate the reliability of multistage circuits. The low and high state noise margins (NML, NMH, for short) are respectively obtained from NML = VIL-VOL and NMH = VOH-VIH, where V1L and VIH define as input low and high voltage while ∂VOUT/∂VIN = −1;VOL and VOH define as output low and high voltage in the same condition. The calculated NML and NMH are 1.01V and 0.86V at VDD of 2.5 V, indicating that the inverter can be used

multistage digital circuits.[52]. In addition to

the linear relationship between gain and VDD, the VDD and extracted transition width (VIH–VIL) are also linear as demonstrated in Figure 10c. The expected narrow transition width can enhance the response properties of circuits. The calculated maximum transition width (~0.61 V) is smaller than the reported InZnO-based TFTs (~1.1 V) TFTs.63 To evaluate the alternative current (AC) properties, the dynamic behavior at 1 Hz for AC square wave signal was investigated and demonstrated in Figure 10d. As a result, it can be concluded that the inverter based on 560oC-driven ZrGdOx/ZnSnO TFTs behave excellent logic inversion action and well dynamic behavior, indicating the promising alternative in pixels control circuits for AMOLEDs 64and other complicated electron devices, including ring oscillators, new pattern sense devices and detectors .65,66 20


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As a reference, the inverter based on 510oC-driven ZrGdOx/ZnSnO samples in a series connection with a 2MΩ resistor is also constructed and shown in Figure S4. The approaches of electrical test are shown in Figure S5. Although the larger voltage gain of 9.4 has been achieved, the degraded electrical properties have been observed, including the deviated output low voltage of 0 V. Therefore, it can be concluded that the TFTs can not meet the full swing characteristic of the inverter. In addition, the extracted transition widths and voltage gain don't keep linear relationship with the adding VDD, indicating the degraded electrical properties. The reduction in performance can be attributed to the fact that the 510oC-processed ZrGdOx samples are not as dense as the 560oC-driven ZrGdOx films and the existence of more interface defects. Hence, it can be concluded that the optimized 560oC-driven ZrGdOx/ZnSnO TFTs can be integrated into high-performance resistor-loaded inverter. The high gain and sufficient switching speed demonstrate its potential application in large-scale integrated circuits.

4. Conclusions In this report, the 2ME-deriven ZnSnO films are integrated with eco-friendly WI ZrGdOx films to fabricate TFTs. Annealing temperature dependent structural, composition, optical, and electrical properties of WI ZrGdOx films were studied by different characterizations. High transmittance over 90% and the formation of the metastable phase of Zr2O for WI ZrGdOx films have been observed. A high areal capacitance of 532 nFcm-2 at 20Hz and low leakage current of 6×10-10A cm-2 have been found in 560oC-annealed ZrGdOx samples. The optimized 430oC-annealed 21



Page 22 of 44

ZrGdOx/ZnSnO TFTs with operating voltage of 2 V demonstrate remarkable electrical properties, such as the high Ion/Ioff of ~1.1×106 and the high μsat of ~3.1 cm2V-1S-1. To further explore possible applications for complicated logic circuits, the resistor-loaded

unipolar

inverters

have

been

built

based

on

430oC-ZnSnO/560oC-ZrGdOx TFTs and a high gain of 7.3 has been obtained. As a result, it can be inferred that the ZnSnO/ZrGdOx TFTs have the potential application for low-power consumption, environmentally friendly oxide flexible electronics .

■ ASSOCIATED CONTENT Supporting Information Output characteristics and Transfer characteristics of the 430oC-derived ZnSnO/SiO2 TFTs; Output characteristics and Transfer characteristics of the 430oC-derived ZnSnO-based TFTs with different method derived ZrO2-based high-k gate dielectrics layer (WI-ZrO2, WI-ZrGdOx ,2ME-ZrGdOx); the PBS tests for 430oC ZnSnO/510oC ZrGdOx TFT and VTH shift; the resistor-loaded inverter tests for 430oC ZnSnO/510oC ZrGdOx TFT. The fabricated TFTs photographs, the C-F and I-V test of ZrGdOx MOS capacitors, the transform and output test for ZrGdOx/ZnSnO TFTs. (PDF)

AUTHOR INFORMATION Corresponding Author Email: [email protected]

Author Contributions G. H. conceived the plan and guided the project; B. Y. accomplished the experiments and relative measurements; B.Y, L. Z, and Y. C. Z. collected and analyzed the data; Y. 22


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C. Z. offered assistance in implementing experiments; Y. F. X. and F. A. gave improvement suggestions for the process of the experiments; Z.Q. S. participated in the mechanism analysis. All authors revised the manuscript.

Notes The authors declare no competing financial interest.

ACKNOWLEDGMENTS The authors acknowledge the support from National Natural Science Foundation of China (11774001, 51572002), open fund for Discipline Construction, Institute of Physical Science and Information Technology, Anhui University (S01003101), and Natural Science Research Project of Colleges and Universities in Anhui Province (KJ2018ZD060).

23



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Tang, C. Q.; Liu, P.; Peng, H. S.; and Fang, X. S. A Real-Time Wearable UV-Radiation Monitor based on a High-Performance p-CuZnS/n-TiO2 Photodetector Adv. Mater. 2018, 30, 1803165.

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Figures and Tables Caption Figure 1 TG results of ZnSnO and ZrGdOx xerogel, measured at a heating rate of 5 °C/min. Figure 2 Optical transmittances of WI ZrGdOx thin films annealed at different temperatures. The inset shows the Tauc plots of the corresponding WI ZrGdOx thin films. Figure 3 XRD patterns of the WI ZrGdOx thin films as a function of annealing temperature. Figure 4 XPS spectra of a) O1s, c) Zr 3d, and d) Gd 3d peaks for WI ZrGdOx thin films as a function of annealing temperature. b) Semiquantitative analyses of the oxygen component for the corresponding ZrGdOx thin films. Figure 5 a) Areal capacitance of the WI ZrGdOx, WI ZrO2, and 2ME-ZrGdOx thin films annealed at different temperatures. b) Annealing temperature and frequency dependent dielectric constant of the WI ZrGdOx, WI ZrO2, and 2ME-ZrGdOx thin films. Figure 6 Leakage current density of the WI ZrGdOx thin films annealed at various temperatures. Figure 7 a) Output characteristics of the ZrGdOx/ZnSnO TFTs as a function of annealing temperature of ZnSnO layer. b) Transfer characteristics of the ZrGdOx/ZnSnO TFTs as a function of annealing temperature of ZnSnO layer. c) Output characteristics of the ZrGdOx/ZnSnO TFTs as a function of annealing 34


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temperature of ZrGdOx films. d) Transfer characteristics of the ZrGdOx/ZnSnO TFTs as a function of annealing temperature of ZrGdOx films. Figure 8 Schematic cross-section view of the ZnSnO TFTs with (a) 2ME-derived ZrGdOx dielectrics, and (b) WI ZrGdOx dielectrics. c) Schematic energy-band diagrams of (c) 2ME-ZrGdOx/ZnSnO interface and (d) WI-ZrGdOx/ZnSnO interface. Figure 9 a) Transfer curves of 430oC ZnSnO/560oC WI ZrGdOx TFT under PBS tests. b) The VTH shift as a function of stress time. The inset shows the time dependence of ΔVTH in the ZnSnO TFT with the 560oC-annealed ZrGdOx gate dielectric under the bias stress of 1.5 V. Figure 10 a) The VTCs and b) signal gain of resistor-loaded inverter with 430oC ZnSnO/ 560oCWI ZrGdOx TFT. c) Voltage gain and the transition width of the inverter at various VDD values. d) Dynamic switching behavior of the inverter under AC square waves at 1Hz.

Table 1. Electrical parameters of ZrGdOx/ZnSnO TFTs at various annealing conditions.

Table 2. Electrical parameters of the solution-processed ZnSnO-based TFTs based on various high-k dielectrics.

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Table 3.

Electrical parameters of ZTO integrated WI-ZrO2, 2ME-ZrGdOx, WI-

ZrGdOxTFTs at the same annealing conditions.

TOC GRAPHIC

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Figures and Tables

Fig. 1 He et al

Fig. 2 He et al



Fig. 3 He et al

Fig. 4 He et al


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Fig. 5 He et al

Fig. 6 He et al



Fig. 7 He et al

Fig. 8 He et al


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Fig. 9 He et al

Fig. 10 He et al



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Table-1

Sample

μsat

Ion/Ioff

VTH [V]

SS [V dec-1]

NSmax [cm-2]

[cm2V-1S-1] 380oC ZnSnO/510oC ZrGdOx

1.4

1.2×104

0.78

0.14

4.3×1012

430oC ZnSnO/510oC ZrGdOx

3.1

3.3×105

0.5

0.091

1.63×1012


2.9

1.4×105

0.36

0.1

2.19×1012


3.4

5.4×103

0.6

0.17

4×1012


3.1

3.3×105

0.5

0.091

1.63×1012


2.9

1.1×106

0.7

0.092

1.65×1012


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Table-2

Temp

Channel layer

Dielectric layer

Solvent

[oC]

μ

Ion/Ioff

Vg range

Year

Ref.

[V]

[cm2V-1S-1]

500

ZTO

ZrO2

Acetonitrile

2.5

106

-1.5-5

2010

20

500

ZTO

Gd2O3/Y2O3

2ME

2.5

105/104

-1-10

2011

21

300

ZTO

HfOx

2ME

1.05

105

-4-4

2012

16

400

ZITO

Gd2O3

2ME

1.9

103

-2-6

2013

22

500

ZTO

Gd2O3

2ME

2.5

106

-2-7

2013

23

450

ZTO

Al2O3

2ME

2.11

104

-2-6

2014

28

500

ZnO

HfLaO

2ME

1.6

106

-2-6

2014

3

350

ZTO

AlOx

2ME

0.8

104

-1-4

2015

7

400

SnO

ZrO2

2ME

2.5

103

-3-3

2017

3

430

ZTO

ZrGdOx

H2O

~3.1

106

-0.5-2


This work


Page 44 of 44

Table-3 μsat

Sample

Ion/Ioff

VTH [V]

SS [V dec-1]

NSmax [cm-2]

[cm2V-1S-1] 430oC ZTO/560oC WI-ZrO2

2.68

2.6×104

0.7

0.12

3.8×1012

430oC ZTO/560oC 2ME-ZrGdOx

2.38

8.2×104

1.15

0.102

2.7×1012

430oC ZTO/560oC WI-ZrGdOx

2.9

1.1×106

0.7

0.092

1.65×1012


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