Luminescence Applications - ACS Publications - American Chemical

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2018.2854778, IEEE Transactions on Power Electronics 1

Ripple-free Input Current High Voltage Gain DC-DC Converters with Coupled Inductors Ashok Kumar, Student Member, IEEE and Parthasarathi Sensarma, Senior Member, IEEE

Abstract—This paper presents three non-isolated high voltage gain dc-dc converters with ripple-free input current. The proposed converters combine coupled inductors and voltage-doubler structure (VDS) to achieve high step-up of input voltage. An active clamp circuit is used to suppress voltage spike of the switch caused by of the leakage inductor of the coupled inductor. VDS is placed in the secondary winding of the coupled inductor which clamps the diodes voltage stress. Working principle and design methodology of the proposed converters are presented in detail. Experimental results for a 300 W laboratory prototype, 48 V input voltage and regulated output voltage of 400 V, are shown to validate the operation of proposed converters. Index Terms—High voltage gain, dc-dc converter, active clamp, ripple-free input current, coupled inductor, voltage doubler.

I. I NTRODUCTION High voltage gain is an essential demand on grid interfacing converters for small renewable energy sources, apart from applications like uninterruptible power supplies (UPS), high intensity discharge (HID) lamps, telecommunication and server power supplies [1]. In these applications, a high voltage gain (≈ 10) and efficiency, along with reduced switch voltage, component count, input current ripple, weight and volume are priority features, while galvanic isolation is usually of lower importance. The canonical boost converter has limited voltage gain, due to parasitic losses of real circuit elements. Though cascade connection of several boost converters is one of the possible solutions [2], but this results in poor efficiency and greater control complexity. Z-source converter [3] and its derivatives [4]- [5] provide high voltage gain by utilizing the shoot-through state. However, large voltage gain invariably requires greater part count, resulting in higher cost and circuit complexity. Reported techniques to achieve high voltage gain with non-isolated structures include switched capacitors [6]- [8], switched inductors [6], [7], voltage lift [9], voltage doubler [10]- [12], voltage multiplier [13]- [14] and bootstrap capacitors [15]. Another approach for achieving high voltage gain is through interleaved converters [1], [11], [16] configured in input parallel output series (IPOS) mode, which also reduces input current ripple. Using coupled inductors [17]- [19] is the most widely used technique for obtaining high voltage gain and its combination with the above methods produces even higher voltage gain. However, this increases component count and reduces efficiency. Also, due to multiplicity of states, these converters are This work was supported by a grant no. DST/RCUK/JVCCE/2015/02 (C) from the Department of Science & Technology, Government of India. The authors are with the Department of Electrical Engineering, Indian Institute of Technology, Kanpur, India (e-mail: [email protected]; [email protected]).

complex to design and control. Other approaches [20]- [22] introduce an active coupled inductor network that produces high voltage gain, but the use of two coupled inductors increases volume of magnetics. Some coupled inductor based circuits [23]- [24] have been reported with reduced component count but their pulsating input current makes these unsuitable for renewable energy and similar weak-source applications. Discontinuous input current converters, e.g. buck, require an extra input filter for mitigating electromagnetic interference (EMI) which increases component count. Even converters which ensure continuous input current, e.g. boost, require large magnetics which reduces the overall power density. To achieve ripple free input current (RFIC), [25]- [27] propose coupled inductor based ripple cancellation circuits but these are not designed for achieving high voltage gain. Interleaved converters [11] is another way of reducing input current ripple, but it increases component count. Combination of zero ripple boost cell (ZRBC) with coupled inductors, [28]- [31], results in RFIC along with high voltage gain. Despite these advantages in [30]- [31], high voltage stress across the output side diode is inevitable, which is further exacerbated by the resonance between its junction capacitor and the leakage inductance. This resonance also increases electromagnetic interference (EMI) problems within the circuit and adjoining equipment. This paper proposes improved versions of [30]- [31] by incorporating voltage-doubler structure (VDS), presented in [10]- [12], which not only protects the output diode from high voltage stress but also provide higher voltage step-up ratio. Besides, the resonance between the leakage inductance and the junction capacitor of the output diode is completely eliminated. Active clamping [32] is employed to suppress the turn-off voltage surge due to inevitable leakage inductance of coupled inductors, thus reducing switching loss, and to realize zero voltage switching (ZVS) during turn ON of active semiconductor devices. The voltage stress of diodes are clamped to output voltage by VDS. Operating principle of the proposed converters is presented in detail followed by design rules for switches and passives. Experimental results obtained from a 300 W laboratory prototype are then presented to validate converter performance. II. C ONVERTER C IRCUIT AND O PERATION Fig.1 shows the reported topologies, [30] and [31], where the diode D1 , suffers high voltage stress. Configuration of the proposed converters are shown in Fig.2. Components of the converters are: input inductor (L1 ), coupled inductors with magnetizing inductance (Lm ), intermediate capacitors (C1−2 ), auxiliary capacitor Ca , output capacitor (Co ), main and auxiliary switches Sm,a with body diodes Dm,a , respectively.

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(a) Fig. 1.

(a) Fig. 2.

(b)

Reported Converters (a) [30] (b) [31].

(b)

(c)

Proposed Converters (a) Topology-1 (b) Topology-2 (c) Toplogogy-3.

(a)

(b)

(c)

(d)

(e)

(f)

Fig. 3. Operating circuits of topology-1 (a) Mode-1, (t0 − t1 ) (b) Mode-2, (t1 − t2 ) (c) Mode-3, (t2 − t3 ) (d) Mode-4, (t3 − t4 ) (e) Mode-5, (t4 − t5 ) (f) Mode-6, (t5 − t0 ).

Output capacitance of switches (Sm,a ) are CrSm and CrSa , respectively and their sum is denoted by Cr . Sa and Ca form the active clamp circuit whereas the capacitor, C2 , and diodes, D1,2 , are the part of voltage doubler circuit. Switches Sm and Sa are operated complementary to each other with adequate dead-time. Steady-state analysis of the proposed circuit is carried out under the following assumptions. 1) Switches Sm and Sa are ideal except their body diodes and output capacitors. 2) The capacitors Co and C1,2 are sufficiently large to ensure negligible ripple on the output voltage, Vo , and capacitor voltages, V1,2 . 3) The converter is operating in continuous conduction mode (CCM).

The coupling-coefficient, k, of the coupled inductors is defined as k = Lm /(Lm + Llk ), where Llk is leakage inductance, and its turns ratio is denoted by n = ns /np . A. Topology-1 Operation Operation of the converter is explained by six modes during one switching cycle. Fig.3 illustrates the effective circuits for each of these modes and Fig.4 shows the corresponding key waveforms. 1) M ode 1 [Fig. 3a, t0 -t1 ]: At t = t0 , Sa is turned-OFF. The negative current ilk , discharges Cr from (Vo − V1 + Va ) to zero and the diode Dm starts conducting. Therefore, zero voltage is applied across Sm . Voltage across Lm , vLm , is (V2 −



and current ilk is obtained as ilk (t) =

Vo − V1 − (V2 −Vn1 +Vo ) (t ) (t − t2 ) + Ilk2 . Llk

(2)

The currents through main switch iSm and diode D2 , iD2 , are ilk and (ilk − im )/n, respectively. 4) M ode 4 [Fig. 3d, t3 -t4 ]: At t = t3 , main switch Sm is turned-OFF and the current ilk charges the junction capacitor Cr , from zero to (Vo −V1 +va ) in short time and makes the Da conducting. The slope of im remains the same and, leakage inductance Llk and capacitor Ca form the series resonant circuit with expressions Vo + V2 − V1 dilk dva + + va = 0, ilk = Ca . dt n dt The solution of above is given by Llk

(3)

(t3 )

Va

+ vLm sin ω(t − t3 ) Z va = vLm − (Va(t3 ) + vLm ) cos ω(t − t3 ) (t )

ilk = Ilk3 cos ω(t − t3 ) − (t )

+ Ilk3 Z sin ω(t − t3 ) Vo + V2 − V1 vLm = (4) n √ √ where, ω=1/ Ca Llk and Z= Llk /Ca . The conduction of diode Da makes zero voltage across Sa . Since, iC2 = (ilk − im )/n > 0, diode D2 is in conduction. 5) M ode 5 [Fig. 3e, t4 -t5 ]: At t = t4 , auxiliary switch Sa is turned-ON to achieve ZVS. The expressions of magnetising current im , current ilk and capacitor Ca voltage va will remain same as in mode-4. The negative iC2 keeps the diode D2 , in conduction. 6) M ode 6 [Fig. 3f, t5 -t0 ]: At t = t5 , the current iC2 reverses direction and diode D2 , stops conducting. Current iC2 charges the junction capacitor of D2 from zero to Vo and discharges that of D1 to zero. The slope of magnetising current is changes to (V2 − V1 )/(nLm ). The resonance equations mentioned in mode-4 are again valid in this mode but with different vLm and initial conditions, and are given by Fig. 4.

(t )

ilk = Ilk5 cos ω(t − t5 ) −

V1 )/n and hence the current ilk is expressed as, ilk (t) =

Vo − V1 − Llk

(V2 −V1 ) n

(t5 )

+ vLm sin ω(t − t5 ) Z va = vLm − (Va(t5 ) + vLm ) cos ω(t − t5 )

Typical waveforms for topology-1.

Va

(t )

(t )

(t − t0 ) + Ilk0 .

(1)

Since, iC2 = (ilk − im )/n < 0, D1 is conducting. 2) M ode 2 [Fig. 3b, t1 -t2 ]: At t = t1 , the switch Sm is turned-ON under ZVS conditions as Dm is conducting. The current ilk follows same increasing trend as in mode-1 and reaches im at t = t2 which reverses iC2 . Therefore, diode D1 is turned OFF with zero current which alleviates the reverse recovery losses. 3) M ode 3 [Fig. 3c, t2 -t3 ]: The current iC2 charges the junction capacitor of D1 to Vo and discharges that of D2 from Vo to zero in short time. At this moment, D2 starts conducting, the voltage across inductance Lm changes to (V2 −V1 +Vo )/n

+ Ilk5 Z sin ω(t − t5 ) V2 − V1 vLm = . (5) n This mode ends when the auxiliary switch Sa is turned-OFF which leads to mode-1. B. Topologies 2 and 3 Operation The conduction sequence of semiconductor devices in topology-2,3 is same as that of topology-1. However, there is difference in secondary winding arrangement which causes the change in voltage across magnetising inductance vLm , and hence, there is change in voltage vlk in various modes. Output voltage for topology-3 is the sum of V2 and Vo . The voltage waveform across Lm and Llk for different time intervals are



TABLE I T OPOLOGIES 2 AND 3 E XPRESSIONS Modes M ode 1 [t0 -t1 ]

Va

Vo

V1

V2

Topology Expression 1 Value (V)

DVin 1−D

nkVin 1−D

Vo − Vin

(kn − 1)Vin

52

400

352

144


DVin 1−D

nkVin 1−D

Vo − Vin

knVin

52

400

352

192


DVin 1−D

nkDVin 1−D

Vo + V2 − Vin

knVin

52

208

352

192

Equations ilk (t) =

(V −V ) VO −V1 − 2 n O Llk

M ode 2 [t1 -t2 ]

(t )

(t − t0 ) + Ilk0

same as above V VO −V1 − n2 Llk

M ode 3 [t2 -t3 ]

(t )

(t − t2 ) + Ilk2

(t )

ilk = Ilk3 cos ω(t − t3 ) − M ode 4 [t3 -t4 ]

TABLE II C APACITOR VOLTAGES

(t3 )

va = vLm − (Va

(t ) Va 3 +vLm

Z

sin ω(t − t3 )

+ vLm ) cos ω(t − t3 )

(t )

+Ilk3 Z sin ω(t − t3 ) vLm = M ode 5 [t4 -t5 ]

same as above ilk =

M ode 6 [t5 -t0 ]

V2 n

(t ) Ilk5

cos ω(t − t5 ) −

va = vLm −

(t ) (Va 5

(t ) +Ilk5 Z

(t ) Va 5 +vLm Z

sin ω(t − t5 )

+ vLm ) cos ω(t − t5 )

sin ω(t − t5 )

vLm =

(V2 −VO ) n

Fig. 6.

Voltage gain vs duty ratio plot.

C1 , C2 , and Co , all topologies have identical current expressions which are given as I1 = Im = Ilk =

Fig. 5.

Voltages across Lm and Llk for topology-2.

shown in Fig.5, where, VO is Vo and Vo + V2 for topology2 and 3, respectively. The governing equations for different modes are given in Table.I. III. S TEADY STATE ANALYSIS As a matter of convenience, for the derivation of steady state voltage and current expressions, the duration of modes1,2,4 and 5 are assumed to negligible as compared to that of modes-3 and 6. Considering the duration of mode-3 and mode-6 as DTs and (1 − D)Ts , where, D and Ts are duty ratio and switching time period, respectively, the obtained voltage expressions for all topologies, after applying voltsecond balance on inductors L1 , Lm and Llk , are listed in Table.II. Therefore, all the converters have same voltage gain which is given by nk . (6) Av = (1 − D) Fig.6 shows the plot of variation of voltage gain w.r.t. duty ratio for different values of turns ratio, n and coupling coefficient, k. Similarly, by applying charge balance on capacitors,

Io n . 1−D

(7)

In [30], [31], energy transfer to secondary happens only during (1 − D)Ts interval by coupled inductor action whereas in proposed converters transfer of energy also takes place during DT s interval by transformer action. Hence more energy is transferred from source to output which results in higher voltage gain. With Llk = 0, voltage vLm is shown in Table. III. During DTs interval, voltage vLm is same for all the converters. Since these have identical voltage across L1 , the difference in their voltage gain is solely caused by the voltage vLm . Duty ratio obtained from volt-sec balance of Lm is D = 1/(1 − p), where p (p < 0) is the ratio of vLm during DTs to that in (1−D)Ts durations. In the proposed converters, inclusion of VDS causes |vLm | to decrease by V2 /n during (1 − D)Ts interval. Obviously, |p| is increased. Thus, for any given input-output voltages, the proposed converters operate at lower D, or, these have higher voltage gain at identical D. IV. C ONVERTER D ESIGN A. Selection of Semiconductor Devices To evaluate current stress on semiconductor devices, the waveforms are simplified by ignoring the dead-time between switching pulses of switches. Fig.7 show the waveforms of leakage current ilk , switch currents iSm,a , and diode currents iD1,2 .



TABLE III VOLTAGE ACROSS Lm Time Duration

[30]

[31]

Topology-1

Topology-2

Topology-3

DTs

Vin 48

Vin 48

Vin 48

Vin 48

Vin 48

- Vno

- Vn1

2 - V1 −V n

2 - Vo −V n

- Vno

-100

-88

-52

-52

-52

Expression Value (V) Expression Value (V)

(1 − D)Ts

1) Diode stress: Both the diodes D1,2 have same peak blocking voltage of Vo . Average of diode currents, iD1,2 , as shown in Fig.7, is equal to load current, Io . Therefore, the diodes current stress can be derived as 0.5IˆD1 (1 − D) = 0.5IˆD2 D = Io 2Io 2Io IˆD1 = , IˆD2 = (8) 1−D D 2) Switch stress: The peak voltage stresses on switches Sm and Sa are given by Vin . (9) 1−D Both the switches experience maximum current stress at t = t3 (t ) which is equal to leakage current Ilk3 , and corresponding expression is obtained by observing Fig.7 i.e. vˆSm = vˆSa = Vo − V1 + Va =

IˆSm,a

Iˆlk − IˆLm = IˆD2 n 2nIo nIo Vin DTs (t ) = Ilk3 = + + D 1−D 2Lm

(10)

which is also the turn-OFF instant current of Sm . All the proposed converters have the same voltage and current stress on semiconductor devices. Therefore, (8)-(10) hold for all the converters.

Fig. 7. rating.

Simplified waveforms for selection of switches and diodes current

B. Choice of Duty Ratio From (9), it is clear that for the proposed converter active switch voltage stress is only dependent on duty ratio, D. Hence, the selection of D is done to restrict switch stress maximum up-to twice of the input voltage, Vin . However, any other criterion to select D will suffice to start the design process. C. Selection of Turns Ratio, n After choosing duty ratio (D), turns ratio (n), can be obtained, using (6), to attain the desired voltage gain ns Vo (1 − D) n= = . np Vin

(11)

D. Selection of Magnetizing Inductance, Lm Lm is designed based on the maximum allowable ripple, ∆iLm , on the average magnetizing current, Im . Thus, the magnetizing inductance is obtained as Lm

Vin DTs = 2∆im

(12)

E. Selection of Input Inductance, L1 Though, ideally, the input inductor has zero current ripple, however, the combined voltage ripple across it is not negligible. The actual inductor voltage waveform is the sum of capacitor voltage ripple components, as illustrated in Fig.7, where net voltage ripple, ∆v, is (∆v1 + ∆vo ) for topologies1- 2 and (∆v1 + ∆v2 + ∆vo ) for topology-3. Flux linkage (λ) is given by λ = (1/2)∆v(Ts /2) = | {z } f rom vL1 wavef orm

L1 (2∆i1 ). | {z }

(13)

f rom i1 wavef orm

Therefore, for a given current ripple, ∆i1 , input inductance L1 is obtained as ∆vTs . (14) L1 = 8∆i1 All proposed topologies have identical steady state and ripple expressions for i1 and im . Hence, (12) and (14) are valid for all the converters.



TABLE IV C APACITOR D ESIGN C1

C2

Co

Topology Expression 1 Value (µF)

(n−1)Io Ts 2∆v1

Io Ts 2∆v2

(n+D−1)Io Ts 2∆vo

1.6

1.3

6.6


nIo Ts 2∆v1

Io Ts 2∆v2

(n+D)Io Ts 2∆vo

2.1

1.0

8.5


nIo Ts 2∆v1

(n+D−1)Io Ts 2∆v2

(n+D)Io Ts 2∆vo

2.1

3.4

16

Fig. 8.

F. Selection of Capacitances C1 , C2 and Co For voltage ripples ∆v1 , ∆v2 and vo , the required value of capacitances C1 ,C2 and Co for all converters are listed in Table.IV.

Minimum load current for ZVS of all switches. TABLE V R IPPLE SPECIFICATIONS FOR DESIGN ∆v1

∆v2

∆vo

∆i1

∆im

2%

2%

0.5%

5%

10 %

G. ZVS Conditions for Sm and Sa To achieve the ZVS of the switch Sm , the energy stored in the leakage inductor at t = t0 must be large enough to fully charge and discharge the junction capacitor of Sm and Sa , respectively, before the switch Sm is turned on. The expression (t ) for Ilk0 can be derived by using Fig.7 i.e. nIo 2nIo Vin DTs nIo Vin DTs − − =− − 1−D 1−D 2Lm 1−D 2Lm (15) which is also the turn-OFF instant current of Sa . Following equations are the ZVS conditions of the switch Sm (t )

Ilk0 =

(t )

0.5Llk (Ilko )2 ≥ 0.5(CrSm + CrSa )(Vo − V1 + Va )2 √ Vo Cr (t ) Ilko ≥ = Imin (16) n Llk where, CrSm and CrSa are junction capacitances of Sm and Sa , respectively and their sum is represented by Cr . Moreover, (t ) Ilk0 is the result of resonance between Ca and Llk . So, too small value of Ca will cause excessive ringing across the switch and its larger value will make the system bulky. A good trade-off is to select the Ca so that one-half of the resonant period formed by Ca and Llk exceeds the maximum OFF time of Sm [32]. Therefore, √ π Llk Ca ≥ TOF FSm = (1 − D)Ts ( )2 nVin Ts 1 (17) Ca ≥ Llk πVo

However, to achieve ZVS at lower load, an extra inductance, Lelk , in series with primary winding of coupled inductor, is to be connected, whose value can be calculated from (16).

H. Design example Topology-1 is designed based on power specifications mentioned in Table VI and the design steps are as follows: 1) Firstly, D is selected as per (9) such that vˆsm,a = 2Vin . Turns ratio, n, is chosen to satisfy (11). 2) Ripple specifications are used to decide Lm , L1 , C1 , C2 and Co , as per (12), (14) and Table.IV. Ripple values used for the present design are listed in Table V. 3) After fabrication of coupled inductor, Llk is measured. Validity of (16) is checked for the considered minimum load (here 30 %) to ensure ZVS of both the switches. Otherwise, the additional inductance, Lelk is calculated using (16). 4) Ca is selected using (17). Table.II, III and IV contain numerical values of the expressions listed in them. Clearly, topology-1 has least values of C1 and Co and topology-3 has highest values of all capacitors maintaining same ripple specifications mentioned in Table.V. Final selected parameters for topology-1 are listed in Table.VI.

Similarly, the condition for ZVS turn-ON of switch Sm is found to be √ Vo Cr (t ) = Imin (18) Ilk3 ≥ n Llk (t )

(t )

It should be noted that, Ilko is always less than Ilk3 . So, if (16) is satisfied for a particular load, than ZVS of both the active switches will happen for that load. Fig.8 exhibits the (t ) (t ) plot of Ilk0 , Ilk3 and Imin for different load conditions and parameters listed in Table.VI, which shows that ZVS of both the switches will be achieved for minimum 28 % of rated load.

(a) Fig. 9.

(b)

Fabricated lab prototype PCB (a) Top layer (b) Bottom layer.



TABLE VI S YSTEM PARAMETERS Vin 48 V

P 300 W

Vo 400 V

1/Ts 100 kHz

n 4

L1 60 µH

Lm 180 µH

Llk 5 µH

C1 2 µF

C2 1 µF

Co 5 µF

Cr 2x214 pF

Pmin 30 % of P

Ferrite cores (L1 , Lm ) B64290L0657, B64290L0082

I. Comparison among the proposed converters

A. Input current ripple

All the proposed topologies have identical device stresses, inductor steady state and ripple expressions. The differences exist only in capacitor design and steady state expressions. Unlike topologies-1 and 2 where C2 carries only the diode currents, in topology-3, the current through capacitor Co also flows through C2 . This makes C2 current stress highest among the proposed topologies, and thus has higher losses leading to shorter capacitor life. Moreover, for same ripple specification, from Table.IV, C2 has the highest capacitance value in topology-3, and that of Co and C1 are lowest in topology1. Also, output voltage ripple in topology-2 is ∆vo + ∆v2 . Hence, more stringent ripple specifications are required for Co and C2 design. All these confirm that topology-1 gives the best performance, without any increase in magnetics size and switch stress.

Fig.11b shows the waveforms of v1 , vo and input current, i1 , which clearly show negligible ripple in i1 . For precise verification of ripple content in i1 , ac components of v1 , vo and i1 are recorded and shown in Fig.11c. Observed values of ∆v1 and ∆vo are 4.8 V and 2.3 V, respectively. For these voltage ripples, the calculated ∆i1 , using (14), is 0.148 A which is very close to the observed value (0.14 A). Therefore, the achieved input current ripple is 2.25 % and recorded experimental waveforms closely match the theoretical analysis. B. Efficiency analysis Various loss components are calculated as follows: 1) MOSFET Losses: Switching losses in MOSFETs are computed using PSW = 0.5{(If (m) vˆs + If (a) vâ )tf + Coss (ˆ vs2 + vâ2 )}fs (19)

V. R ESULTS AND D ISCUSSIONS A 300 W, 400 V laboratory prototype of topology-1 was fabricated to validate the theoretical analysis, as per the specifications and parameters listed in Table.VI. Part numbers of semiconductor devices used are shown in Table.VII. Photographs of both top and bottom layers of the fabricated circuit board are shown in Figs.9a- 9b, respectively. Figs.10a-10b show experimental waveforms of the proposed converter under rated conditions. Fig.10a shows auxiliary capacitor voltage va , capacitor voltage v2 , current ilk , and capacitor current iC2 . Fig.10b exhibits diode voltages and currents (vD1,2 , iD1,2 ). It is evident that obtained results are in close accordance with the analytical waveforms discussed in section-II. Figs.10c-10f show the experimental results of gate voltages (vSm,g , vSa,g ), drain voltages (vSm,d , vSa,d ) and switch currents (iSm , iSa ) of the main switch Sm and auxiliary switch Sa for rated and 30% load. It is clear from the above figures that the switch currents are negative before the respective gate signals are applied. Since the body diodes Dm,a , of the switches carry the negative switch current at the turn-ON instant, ZVS turn ON of both switches are achieved at rated and 30 % load. The converter is operated in closed loop with the output voltage regulated at 400V. Fig.11a shows the experimental output voltage vo and load current io under step load variation between 40% and rated loads. It is clear that the output voltage is almost insensitive to load transients or loading level. TABLE VII S ELECTED SEMICONDUCTOR D EVICES

Proposed Implementation

MOSFET IPP200N15N3

DIODE C3D06060F

For Comparison

IPB320N20N3

C3D04065A

where, fs is switching frequency, Coss and tf are output capacitance and turn-OFF time of MOSFET, respectively, vˆs (ˆ va ) and If (m) (If (a) ) are voltage and current stress of Sm (Sa ) at turn-OFF instant, respectively, which are obtained from (9), (10) and (15). Total conduction loss of both the switches is given by 2 2 PCON = (Irms(m) + Irms(a) )Rds(on)

(20)

where, Irms(m) (Irms(a) ) is RMS current of switch Sm (Sa ) and Rds(on) is the ON-state resistance. 2) Diode Losses: Use of Schottky diodes saves the loss due to their reverse recovery charges. However, switching loss due to charging of diode junction capacitance, Cossd , is given by PSW (D) = fs Cossd Vo2 .

(21)

Total conduction loss in diodes is obtained as PCON (D) = 2VF Io

(22)

where, VF is the diode’s forward voltage drop. 3) Inductor Losses: Total conduction loss in L1 and coupled inductors, is expressed as 2 2 2 PCU = Irms(1) r1 + Irms(p) rp + Irms(s) rs

(23)

where, Irms(1,p,s) and r1,p,s are RMS currents and internal resistances of inductor L1 , primary and secondary windings of coupled inductors. Core loss in coupled inductor is obtained as PCO = ρ(∆B, fs )Ac le (24) where, ρ(∆B, fs ) is the material power loss density, Ac the cross-sectional area and le the effective mean length of the core, while ∆B is expressed as ∆B = Vin D/(NT Ac fs )

(25)



(a)

(b)

(c)

(d)

(e)

(f)

Fig. 10. Experimental results at rated output load Po =300W (a) v2 , va , ilk , iC2 (a) vD1 , vD2 , iD1 , iD2 ; Scale: v2 (100V/div), va (50V/div), ilk (10A/div), iC2 (5A/div), vD1 (500V/div), vD2 (500V/div), iD1 (2A/div), iD2 (2A/div); Gate voltage, drain voltage, switch current of (c) main switch at Po =300W ; Scale: iSm (10A/div) (d) Po =90W; Scale: iSm (2A/div) (e) auxiliary switch at Po =300W (f) Po =90W; Scale: vSm,g (20V/div), vSm,d (100V/div), vSa,g (20V/div), vSa,d (100V/div), iSa (10A/div); X-axis: Time (2µs/div).

Fig. 11. (a) Dynamic response for step change of 40 % and 100 % rated load; Scale: vo (100V/div), io (0.2A/div), X-axis: Time (100ms/div); (b) v1 , vo and i1 ; Scale: vo (100V/div), v1 (100V/div), i1 (5A/div), X-axis: Time (2µs/div); (c) ∆v1 , ∆vo and ∆i1 ; Scale: ∆vo (5V/div), ∆v1 (5V/div), ∆i1 (0.1A/div), X-axis: Time (2µs/div).

where, NT denotes the primary winding turns. Core loss in inductor L1 is neglected as the voltage ripple across it is almost negligible. 4) Capacitor Losses: Capacitor losses due to equivalent series resistance (ESR) are summarised as ∑ 2 PCAP = Ixrms rx (26) where, x∈{Ca , C1 , C2 , Co }, Ixrms and rx are the rms current and ESR of the xth capacitor, respectively. Converter efficiency is estimated using the loss expressions from (19)-(26). RMS expressions of various quantities for proposed topologies are shown in Appendix A. Fig.12a plots the estimated efficiency of topology-1 at different loads, along with the experimentally measured values. The measured efficiency at rated load is 95.8 % and maximum efficiency is 95.9 %, at 70 % load. Table.X shows the loss breakdown at rated load which shows that switching loss is the major contributor.

C. Comparison with reported ZRBC based topologies Comparison of the proposed topologies, with [30]- [31], is shown in the Table.VIII for same rating. The proposed converters exhibit same performance, however, topology-3 has highest value of L1 among all the topologies which is due to additional voltage ripple ∆v2 appearing across its input inductor. Clearly, these have reduced voltage stress on all switches as compared to [30]- [31]. Coupled inductors are designed using the same core, mentioned in Table.VI, and winding resistances are estimated by the Dowell function [33]. RMS expressions of various quantities for [30]- [31] are shown in Appendix A. For a fair comparison of efficiency, identical switching devices are used for all the converters, as listed in Table.VII. This thus dictates a higher switch voltage rating than what would be required by the proposed topology, which somewhat adversely biases its estimated efficiency. Capacitors are selected based on same ripple specifications and their losses are estimated by simulation. Nevertheless, the loss breakdown at rated load,



TABLE VIII C OMPARISON OF PROPOSED TOPOLOGIES WITH [30]- [31] MOSFET Stress Diode Stress D vˆ ˆ îD ˆD Sm,a iSm,a Irms(m) Irms(s) If (m) If (a) v (A) 10.17 9.35 6.87

(V) (A) 592 4.62 544 4.25 400 3.12, 2.88

Inductor Parameters L1 Lm imp

(V) [30] 0.67 148 [31] 0.64 136 Topology-1 0.52 100

(A) 10.17 9.35 18.41

(A) 8.73 7.74 8.99

(A) 3.54 3.36 2.50

(A) 10.17 9.35 18.41

Topology-2 0.52 100

18.41

8.99

2.50

18.41 6.87 400 3.12, 2.88 36

199 6.875

Topology-3 0.52 100

18.41

8.99

2.50

18.41 6.87 400 3.12, 2.88 42

199 6.875

given in Fig.12b, shows that the proposed converters have less losses in active switches and magnetics, and almost identical capacitor loses. Although diode loses are a little higher, their contribution to the total loss is marginal. Fig.12c compares the estimated efficiency profile of the proposed converters which validates the efficiency improvement with the proposed circuits. Table.IX shows the comparison with other reported ZRBC topologies based on voltage gain, switch count and their voltage stress, while Fig.13 shows the voltage gain comparison. Evidently, the proposed converter exhibits the best input voltage step-up capability among these converters. Though all these have the same active switch voltage stress, all reported topologies, except [28], have diode voltage stresses higher than the output voltage. However, [28] uses a three winding coupled inductor which increases magnetics size. D. Comparison with other existing topologies Table.XI shows the comparison of proposed converter with existing topologies of similar power specifications. It is seen that the proposed converter, having lesser/similar component count, has comparable performance as that of existing solutions.

(µH) 36 36 36

(µH) 175 183 199

NT

Irms(s) Irms(p) rp

(A) (turns) 10.17 30 9.35 29 6.875 25

(mΩ) 9.6 9.3 8.0

rs

∆B

ρ

(mΩ) (mT) (kW/m3 ) 153.1 54 9.86 148.0 53 9.40 128.0 50 7.99

(A) 9.42 8.44 9.33

(A) 1.60 1.53 1.73

25

9.33

1.73

8.0 128.0 50

7.99

25

9.33

1.73

8.0 128.0 50

7.99

TABLE X L OSS D ISTRIBUTION AT R ATED L OAD Switching Loss Conduction Loss Switching Loss Diode Loss Conduction Loss Core Loss Inductor Loss Cu Loss Capacitor Loss

4.26 2.09 0.41 1.12 2.00 1.27 0.54

MOSFET Loss

Total

W W W W W W W

11.69 W

TABLE XI C OMPARISON OF T OPOLOGIES Topology [7] [10] [13] [20] [21] [22] [23] [24] Proposed

S(D) 2(3) 1(5) 2(5) 2(6) 2(2) 2(3) 1(2) 2(1) 2(2)

Vin (V) 40 32 20 40 20 50 20 30 48

Vout (V) 200 380 200 200 200 380 220 200 400

P(W) 200 500 200 200 200 400 250 200 300

eff. at P (%) 95.5 91.10 94.75 96.1 95.2 95.2 93.6 92 95.8

VI. C ONCLUSION

Fig. 13.

Voltage gain comparison among ZRBC based topologies.

TABLE IX C OMPARISON AMONG ZRBC T OPOLOGIES Topology

[28]

[29]

[30]

[31]

Proposed

S(D)

1(2)

1(3)

2(1)

2(1)

2(2)

Av

1+Dn 1−D

1+D(n1 +n2 ) 1−D

nD 1−D

vˆs /Vin

1 1−D

1 1−D

1 1−D

vˆD /Vin

1+n 1−D

n1 1−D

n 1−D

nD 1−D

+1

1 1−D n 1−D

+1

n 1−D 1 1−D n 1−D

This paper presents the circuit analysis, operating principle, hardware design procedure of current fed non-isolated high voltage gain boost dc-dc converters. The proposed converters are derived by combining zero ripple boost cell (ZRBC), coupled inductors and voltage doubler structure (VDS). These converters have ripple free input current which makes them suitable for weak-source applications like renewable energy applications. An auxiliary active clamp circuit is used to suppress the turn-OFF voltage spike on the active switch caused by leakage inductor of coupled inductors. The clamp circuit also facilitates the ZVS operation of main and auxiliary switches. VDS not only restricts the diodes voltage stress to output voltage but also improves the voltage gain. The proposed converters have better voltage gain profile among the already reported ZRBC based topologies. These also exhibit better efficiency characteristic than their parent versions. Experimental results of topology-1 with a 300 W laboratory prototype are provided for validation of the theoretical analysis.



(a) Efficiency Plot Fig. 12.

(b) Loss breakdown comparison at rated load

(c) Efficiency comparison plot

Efficiency and power loss performance and comparison.

A PPENDIX A R IPPLE AND RMS EXPRESSIONS

R EFERENCES

1) For Proposed Converters: ∆Ism = nIo /D, Ism = nIo /(1 − D) + nIo /D √ Irms(m) = Ism D + (D/3)(∆Ism /Ism )2 √ Isa = nIo /(1 − D), Irms(a) = Isa (1 − D)/3 √ 2 2 Irms(p) = Irms(m) + Irms(a) Irms(D1 )

2Io = 1−D

Irms(s) =

√ √

2Io 1−D , Irms(D2 ) = 3 D

√

D 3

2 2 Irms(D + Irms(D 1) 2)

ICarms = Irms(a) , IC2rms = Irms(s) √ n2 4(1 − D3 ) 2(1 + D)n IC1rms = Io + − +z 1−D 3D4 D2 √ 2(n − 1) (n + D − 1)2 ICorms = Io D + + +z D 1−D where, z =

4(n−1)2 3D

2) For [30]- [31]: ∆Ism = Vin DTs /(2Lm ), Ism = nIo /(1 − D) √ Irms(m) = Ism D + (D/3)(∆Ism /Ism )2

Irms(a)

If (m) = If (a) = Ism + ∆Ism √ √ 1−D 2Io 1−D = If (a) , Irms(s) = 3 1−D 3 √ 2 2 Irms(p) = Irms(m) + Irms(a)

√ ICarms = Irms(a) , IC1rms = nIo D/(1 − D) √ ICorms = (n + 1)Io D/(1 − D)

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Parthasarathi Sensarma (M’00-SM’17) received his B.E.E (’90), M.Tech (’92) and PhD (2001) from Jadavpur University, IIT Kharagpur and IISc Bangalore, India, respectively, all in the area of Electrical Engineering. He had held positions in Bharat Bijlee Ltd., Thane, India, CESC Ltd., India and ABB Corporate Research, Baden-Daettwil, Switzerland, where he was a Staff Scientist with the Power Electronics Department. Since 2002, he is with the Department of Electrical Engineering, IIT Kanpur, where he is presently a Professor. There he teaches courses on Power Electronics and Electrical Engineering. His research interests include Power Quality, FACTS devices, Power converters and Renewable Energy integration.

Ashok Kumar (S’13) received the B.Tech. degree in electrical engineering from the National Institute of Technology, Raipur, India, in 2010, and the M.Tech. degree in electrical drives and power electronics from the Indian Institute of Technology (IIT), Roorkee, India, in 2012. He is currently working toward the Ph.D. degree in inverter topologies for photovoltaic (PV) applications with the Department of Electrical Engineering, IIT Kanpur, India. His research interests include power electronic converters and control for renewable energy sources.


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