Metal Nanodot Memory by Self-Assembled Block Copolymer Lift-Off

Dec 3, 2009 - As information technology demands for larger capability in data storage continue ... ACS Applied Materials & Interfaces 2016 8 (48), 332...
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Metal Nanodot Memory by Self-Assembled Block Copolymer Lift-Off Augustin J. Hong,*,|,† Chi-Chun Liu,|,‡ Yong Wang,§ Jiyoung Kim,†,⊥ Faxian Xiu,† Shengxiang Ji,‡ Jin Zou,§ Paul F. Nealey,‡ and Kang L. Wang† †

Department of Electrical Engineering, University of California, Los Angeles 90095, ‡ Department of Chemical and Biological Engineering and Center for Nanotechnology, University of Wisconsin, Madison 53706, and § Materials Engineering and Centre for Microscopy and Microanalysis, The University of Queensland, Brisbane, St Lucia, Queensland 4072, Australia ABSTRACT As information technology demands for larger capability in data storage continue, ultrahigh bit density memory devices have been extensively investigated. To produce an ultrahigh bit density memory device, multilevel cell operations that require several states in one cell have been proposed as one solution, which can also alleviate the scaling issues in the current state-of-the-art complementary metal oxide semiconductor technology. Here, we report the first demonstration of metal nanodot memory using a self-assembled block copolymer lift-off. This metal nanodot memory with simple low temperature processes produced an ultrawide memory window of 15 V at the (18 V voltage sweep. Such a large window can be adopted for multilevel cell operations. Scanning electron microscopy and transmission electron microscopy studies showed a periodic metal nanodot array with uniform distribution defined by the block copolymer pattern. Consequently, this metal nanodot memory has high potential to reduce the variability issues that metal nanocrystal memories previously had and multilevel cells with ultrawide memory windows can be fabricated with high reliability and manufacturability. KEYWORDS Flash memory, block copolymer, metal nanodot

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devices with the use of dielectric layers because charge can only be stored in defects of the dielectric layer.20 A promising candidate to solve this defect-assisted enhancement and produce a wide memory window is to employ metal nanocrystals. Since metal has a high density of states at the Fermi level, electrons can be stored more in these states than those stored in defect states.12 Also, this high density of states of metal nanocrystals alleviates the Coulomb blockade effect as nanocrystal size shrinks down, which results in longer retention time in memory devices compared to the memories with semiconductor nanocrystals.21 These metal nanocrystals were typically formed by a rapid thermal annealing (RTA) process on thin metal film deposited on top of the tunneling oxide.12-15 Nanocrystals formed in this way have a wide distribution of size, and the density of nanocrystals strongly depends on RTA temperature.14 Also, typically high temperatures in RTA processes for nanocrystal formation may cause significant reaction between the oxide and the metal. These variability issues limit device performance, scalability, and manufacturability.22 Guarini and co-workers demonstrated pioneering work of the metal lift-off process using self-assembled copolymers.23 Also, a nanocrystal FLASH memory with Si nanocrystals using self-assembled copolymer as a etch mask to define nanocrystals was fabricated by Guarini et al.24 However, a fabrication process and memory effect using metal nanodots defined by the self-assembled block copolymer liftoff have not been reported.

o meet high demand for ultrahigh bit density flash memories, three-dimensional structures that memory cells can be stacked up or multilevel cell operations that require several states in one cell were predicted as key pathways.1 Since then, 3D memory structures and multilevel cells have been extensively investigated.2-9 As for multilevel cell operation, a wide memory window is strongly required.9 In order to produce a wide memory window and further improve memory performance, nanocrystals have been proposed as storage nodes to replace polysilicon film in current state of the art flash memory technology because nanocrystals with high density (>1011/cm2) can have larger total surface area than films, which can enhance the storage capability of the memory device. Tiwari et al. demonstrated significantly improved performance in floating gate memory using Si nanocrystals for the first time.10 Afterward, extensive studies on nanocrystal memories have been reported using Ge,11 metal12-15 nanocrystals, and dielectric nanodots16-18 as storage nodes. However, the low density of states at the Fermi level and defect-related retention enhancement of semiconductor nanocrystals resulted in erasing saturation and thermal instability issues.19 These problems still remain in memory

* Author to whom correspondence should be addressed, [email protected]. |

These two authors contributed equally to this work.

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Present address: Device Solutions Business, Samsung Electronics Co., Korea. Received for review: 10/6/2009 Published on Web: 12/03/2009 © 2010 American Chemical Society

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FIGURE 1. Schematic process flow of the proposed metal nanodot memory fabrication using a self-assembled block copolymer lift-off: (a) PS-b-PMMA nanopattern on a neutral brush layer formed by spin coating; (b) selective removal of PMMA by UV exposure and acetic acid; (c) brush layer being etched through using O2 plasma for adhesion between Cr and the tunnel oxide; (d, e) Cr nanodots formed by e-beam evaporation and lift-off; (f) control oxide deposition by ALD; (g) metal gate deposition by e-beam evaporation.

In this Letter, we report the first demonstration of metal nanodot memory in which metal nanodots are defined by a self-assembled block copolymer pattern at low temperatures. A recent demonstration of the 10 terabit per square inch block copolymer pattern25 makes this device more attractive for ultrahigh bit density memory applications. Scanning electron microscopy (SEM) study showed a uniform distribution of metal nanodots and controlled nanodot sizes through the block copolymer lift-off, which implies this metal nanodot memory has high potential to reduce the variability issues. A transmission electron microscopy (TEM) study showed unique features of the resulting memory device and enabled feature sizes that are critical to evaluate device performance to be determined. The fabricated metal nanodot memory device showed an excellent memory effect of a 15 V memory window at the (18 V program/erase voltages. Such a large memory window at low program/ erase voltages has not been achieved before. A schematic process flow of the proposed fabrication method is shown in Figure 1. A 4 in. low-doped Si wafer (boron doped, 1015 cm-3) was cleaned sequentially by piranha (H2SO4 + H2O2) and RCA2 (HCl + H2O2 + H2O) solutions and then dipped into a buffered oxide etchant (BOE, HF + NH4F + H2O) to remove any residual native oxide. Then 5 nm tunnel oxide was grown by a rapid thermal oxidation (RTO) system. A self-assembled periodic nanopattern was defined on thermally grown SiO2 using a poly(styrene-block- methyl methacrylate) (PS-b-PMMA) copolymer. The block copolymer was self-assembled on top of a ∼5 nm neutral brush layer (Figure 1a) as in previous works.26-29 The diameter of the cylinders was ∼20 nm, and the pitch (center-to-center distance between cylinders) was ∼40 nm. The PMMA block was selectively removed by UV irradiation and acetic acid (CH3COOH) to form the template for patterning. (Figure 1b) The brush layer in the hole was removed by O2 plasma to guarantee good adhesion between the substrate and the evaporated metal (Figure 1c). The thickness of the polymer template was 30-35 nm after the brush etching step. © 2010 American Chemical Society

A layer of 15 nm thick chromium (Cr) was deposited by e-beam evaporation (Figure 1d). As for the e-beam evaporation conditions, the source to substrate distance was 18 in., the angle of incidence between the ion beam and the plane of the substrate was 5°, and the vacuum level was 5 × 10-6 Torr. The evaporation rate was 1.0 A/s. The lift-off process, which removes the block copolymer template and leaves the metal nanodots behind, was done by dipping the substrate into a piranha solution for 10 min at 130 °C (Figure 1e). Metal nanodots with uniform distribution over the entire 4 in. wafer were obtained. Considering that the block copolymer self-assembly was done at 190 °C, all the process temperatures in this block copolymer lift-off procedures were below 200 °C. Hence, the lift-off process is compatible with and can be easily incorporated into conventional complementary metal oxide semiconductor (CMOS) processes. A 30 nm Al2O3 was deposited as a control oxide (Figure 1f) by an atomic layer deposition (ALD, Cambridge Nanotech) and the 10 nm/300 nm Ti/Al layers were deposited by an e-beam evaporator (CHA30) through a shadow mask with a hole area of 7 × 10-4 cm2. A capacitive structure of the metal nanodot memory device was completed for electrical testing (Figure 1g). Postannealing was done at 450 °C for 30 s by rapid thermal process (RTP) in N2 ambient to enhance the contact between the gate metal electrode and the control oxide. Tilted scanning electron microscopy (SEM, LEO 1550 VP) images at different process steps are shown in Figure 2. The completed nanopattern by the self-assembled block copolymer after oxygen plasma is shown in Figure 2a. An SEM image shows the uniform distribution of nanopattern throughout the entire area (>1 µm × 1 µm). Resulting nanodot arrays after the Cr deposition and the lift-off process are shown in Figure 2b and Figure 2c. A low magnification SEM image (Figure 2b) shows the uniform distribution of metal nanodots initially formed at room temperature by e-beam evaporation and processed at 130 °C during the lift-off. The average nanodot density based on SEM images was estimated to be about 1.2 × 1011/cm2. The size of the nanodots was about 225

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FIGURE 2. Tilted SEM images at different processing stages. (a) The polymer template before Cr evaporation. Dimensions are ∼20 nm in diameter, ∼40 nm in spacing, and ∼35 nm in height. (b) Cr nanodots after lift-off. (c) Higher magnification of (b). The shape of metal dots observed in SEM is similar to that in TEM.

below 10 nm, other copolymer systems with stronger segregation forces can be applied such as the PS-PEO system demonstrated by Park et al.25 To determine the detailed structural characteristics of the metal nanodot memory, cross sectional transmission electron micrographs (TEM, FEI Tecnai F20) were obtained. TEM images are shown in Figure 3. Figure 3a shows the brightfield TEM image of a periodic array of Cr nanodots. Excellent coverage of Cr nanodots by ALD Al2O3 implies a potential low leakage current through the device, which is essential for high device performance. Cr nanodots showed a triangle (the projection of cone) shape with 18 ((5%) nm diameter and 16 ((5%) nm height. The cone shape is believed to be formed during the block copolymer lift-off process because of the possible metal hanging over on the side walls of the cylindrical holes. The high-resolution TEM (HRTEM) investigations (an example is shown in Figure 3b) revealed that the tunneling oxide layer has two different thickness: 3 ((0.5) nm underneath the Cr nanodots and 5 ((0.5) nm between the Cr nanodots. Recess of the oxide beneath Cr nanodots may come from the oxygen plasma process to remove the brush layer through the block copolymer holes. Bumps at the Si/SiO2 interface below Cr nanodots are another interesting feature caused by the stress. It has been reported that a large intrinsic stress generally exists in evaporated metal films, and the intrinsic stress can be reduced by the elevated substrate temperatures.30 Darker contrast of Si beneath the Cr nanodot also implies the strain imposed on Si because strain results in the bending and/or distortion of lattice planes, and subsequently, local variations in diffraction conditions occur to result in the change of the image contrast.31 The inset presents a Fourier transformed pattern from the Cr nanodot image in Figure 3b, which is similar to the diffraction pattern.32 This Fourier transformed pattern shows a feature of amorphous state as a diffuse ring. Moreover, by tilting the Cr to directions other than the Si zone axis (Figure 3b), no fringes or lattices were observed for the Cr nanodots in the HRTEM images (similar to the Cr nanodot in Figure

FIGURE 3. Cross sectional HRTEM images of the fabricated memory device. (a) a periodic array of Cr nanodots covered with a 30 nm Al2O3 layer on top using atomic layer deposition. (b) Cr nanodots of 18 ((5%)nm in diameter,16 ((5%)nm in height with a tunneling oxide layer of 3 ((0.5)nm underneath the Cr nanodots, and 5 ((0.5)nm between the Cr nanodots. Inset in Figure 3b shows an amorphous state of the Cr nanodot.

20 nm in diameter, and the center-to-center spacing between Cr nanodots was about 40 nm as seen in the high magnification SEM image (Figure 2c). These nanodots formed a cone shape with a height of about 15 nm. More detailed information about the nanodot dimensions and shape will be discussed in Figure 3. Although only one example using a specific block copolymer was demonstrated in this work, the block copolymer lift-off process has great potential of achieving higher density of nanodots. The diameter and the pitch of the metal nanodots in this method can be controlled by using the block copolymer templates previously reported. By using different molecular weight ratios of the block copolymers, the pitch can be scaled down to ∼25 nm using this PS-b-PMMA system.27 In order to further scale down the feature size © 2010 American Chemical Society

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FIGURE 4. (a) Capacitance-voltage (C-V) curve of the proposed memory device showing memory function with an ultrawide memory window of 15 V at (18 V voltage sweep. (b) C-V curve of the control sample without nanodots showing no hysteresis with steep transitions. (c) Memory device showing low leakage current density. (d) Energy band diagram of the metal nanodot memory device in retention state (Vg ) 0) when charge was stored on the metal nanodot after program.

3b), which indicates that the Cr nanodot is indeed amorphous. This amorphous phase was possibly formed because the Cr deposition was carried out at room temperature, so there was insufficient energy for diffusion to form a crystalline structure. For most amorphous metal studies, cooling rate of materials is known to be one of two major factors.33 Since material cooling rate is proportional to undercooling (∆T) and undercooling increases with decreasing particle sizes,34 it is highly possible to obtain amorphous Cr metal nanodot at the scale of 15 nm height and 19 nm diameter cone shape as in our work. Experimentally, an amorphous metal phase was observed at large undercooling with the particle size around 2 µm.33 However, existence of a Cr polycrystalline phases cannot be excluded completely. In terms of the memory device performance, a few percent of Cr polycrystalline phases would not affect the device performance. Capacitance-voltage curves of the metal nanodot memory device at 100 kHz with and without metal nanodots are plotted in Figure 4a and Figure 4b. The control sample without metal nanodots was fabricated by piranha, RCA2 cleaning, BOE dip, 5 nm RTO, and 30 nm Al2O3 ALD in sequence. A counterclockwise hysteresis loop in Figure 4a obtained by forward and backward bias sweeps from -18 to 18 V shows an excellent memory effect of the device with metal nanodots. A threshold voltage shift (∆Vth) of 15 V is seen in Figure 4a. This ultrawide memory window from the (18 V voltage sweep has not been reported before. This large window suggests that the metal nanodot memory device can be used for multilevel cell memory application. The total oxide capacitance of the memory device at ac© 2010 American Chemical Society

cumulation region was 87 pF, and therefore, the equivalent oxide thickness (EOT) was calculated to be 28 nm using

tOX )

εOX A COX

where εOX ) 3.45 × 10-13 F/cm for SiO2 and area A ) 7.068 × 10-4 cm2. Flat capacitance values at the accumulation region (87 pF) and inversion region (16 pF) throughout the bias sweep range ((18 V) (Figure 4a) implies the excellent quality of ALD Al2O3 film covering metal nanodots because a leaky control oxide would increase accumulation capacitance as additional charges could be induced to the oxide meanwhile capacitance would decrease as the charges were extracted from the oxide at the inversion region. Steep transitions without any kinks from accumulation to inversion and vice versa imply the low interface states at the SiO2/Si interface,35 which proves the effectiveness of the cleaning process (piranha, RCA2, and BOE) and the following rapid thermal oxidation. The control sample without a metal nanodot also showed the flat capacitance values at both accumulation and inversion regions with steep transitions (Figure 4b). More importantly, the control sample showed no apparent hysteresis loop with a (18 V bias sweep. This is strong evidence that the programmed charges in the metal nanodot memory device were mostly stored at the metal nanodots and not in the oxide or at the interfaces. These low leakage current and low interface states are critical for the high performance of the device such as large memory window, long retention time and high reliability.36 The threshold voltage shift of the metal nanodot memory device can be described as37 227

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∆Vth )

(

)

Q 1 εtun t + d εtun con 2 εnd nd

wise memory effect can be observed because of the electron transfers between metal nanodots and electrode through the control oxide (see Supporting Information). Retention time of the metal nanodot memory device might be deteriorated to some extent because of the smaller energy barrier when using Cr instead of using metals with high work functions such as Pt or Au. This potential problem has to be addressed further. However, a stronger dependence of the retention time on the barrier width of the tunnel oxide than the barrier height (Φb)12 still opens the high chance to achieve a ultrahigh-performance metal nanodot memory device without changing materials that we used in this work.. In summary, a novel device has been proposed and demonstrated to fabricate metal nanodot memory by a block copolymer lift-off. An ultrawide memory window of 15 V was achieved at low program/erase voltages using the proposed fabrication process. This ultrawide memory window is suitable for multilevel cell application that alleviates the scaling issues and enables an ultrahigh bit memory. The block copolymer lift-off process set the metal nanodot size, uniformity, and density throughout the wafer, which are critical for device reliability and manufacturability. An overall low temperature process to form a metal nanodot offers a low thermal budget for device fabrication and, more importantly, minimizes any possible reaction between the metal nanodot and tunnel oxide that may deteriorate the device performance significantly. A uniform distribution of metal nanodots, low process temperatures, and a high quality control oxide with low leakage current are believed to result in an ultrawide memory window. Metal nanodot memory by the block copolymer lift-off also has great potential to achieve a higher density of dots and potential of adjusting device performance by adopting different block copolymer systems and different metals as nanodot. This metal nanodot memory with the simple and reliable block copolymer lift-off process may open new opportunities for terabit memory applications.

(1)

where Q is the charge density (C/cm2) in the nanodot, tcon is the control oxide thickness, εox and εnd are the tunneling oxide and the nanodot permittivity, and dnd is the nanodot diameter. Since the metal nanodot permittivity εnd is reported to be anomalously high (>105),38 we may ignore the second term of eq 1. Substituting ∆Vth ) 15 V, εtun ) 3.45 × 10-13F/cm and tcon ) 3 × 10-6cm, Q is calculated to be 1.73 × 10-6 C/cm2. Using the nanodot density (≈ 1.2 × 1011/ cm2)estimated from SEM images, average 1.44 × 10-17 C is stored in one dot. Therefore, one dot stores up to about 90 electrons during the program as one electron has the charge of 1.6 × 10-19 C. It is observed that the device can be completely erased and even overerased to below the 0 V threshold voltage. This is because the Al2O3 control oxide had a low leakage current so that the electrons injected from the gate metal to Cr nanodots were effectively blocked during erase operation while electrons could be injected from Cr nanodots to Si substrate through tunneling oxide, which resulted in the overerase. The large overerase in Figure 4a (>-2 V) is beneficial because it reduces the overall program/erase voltage for multilevel cell operation.36 Figure 4c shows the dc leakage current density (A/cm2) through the device. Low leakage current densities less than 5 × 10-7 A/cm2 were observed at (18 V, which were expected from the flat C-V curves and TEM images. An energy band diagram of the metal nanodot memory device in the retention state (Vg ) 0) is shown in Figure 4d. This energy band diagram implies that the metal nanodot memory has potential of tuning energy barrier (qΦb) between the metal nanodot and Si substrate if metals with different work functions (WF) can be used as nanodots. Different metal nanodots instead of Cr using the block copolymer lift-off were demonstrated28 but not yet employed to memory devices. This energy barrier (qΦb) affects the tunneling efficiency of the tunnel oxide and the retention time of the metal nanodot memory device.12 In our case, a wider memory window than the memory window of a Pt metal nanocrystal memory previously reported36 can be explained partly from the relatively low work function of Cr (WF ) 4.55 eV). As barrier height (Φb) became smaller by using Cr, tunneling efficiency can be enhanced, and thus resulted in a wider memory window at a given electric field than that of metal nanocrystal memory with Pt (WF ) 5.6 eV). Calculated barrier height (Φb) is 0.5 eV from the Si electron affinity (4.05 eV) and the Cr work function (WF ) 4.55 eV). Furthermore, quality and thickness of the control oxide are critical to maximize the memory effect of the device. High quality control oxide with low defects minimizes the leakage current at a given electric field. Also, a thicker control oxide reduces the electron tunneling probability by increasing the barrier width. Therefore, high quality control oxide with a proper control oxide thickness to tunneling oxide thickness ratio confines the electron transfers to tunneling between metal nanodots and Si substrate during the program/erase operation. If the control oxide is leaky or the control oxide has an insufficient barrier width to block the electron tunneling, memory effect can be significantly reduced or clock© 2010 American Chemical Society

Acknowledgment. Authors would like to thank the NSF IGERT: Materials Creation Training Program (MCTP) (DGE11443), the California NanoSystems Institute (CNSI), Samsung Electronics Co., Ltd., and Australia Research Council for financial support and Sungmin Kim for his helpful discussion. Supporting Information Available. Figures showing block copolymer lift-off process optimization, more TEM evidence on device features, and a clockwise memory effect. This material is available free of charge via the Internet at http:// pubs.acs.org. REFERENCES AND NOTES (1) (2) (3)

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