Letter pubs.acs.org/NanoLett
Thermal Conductivity of Mechanically Joined Semiconducting/Metal Nanomembrane Superlattices Daniel Grimm,*,†,‡ Richard B. Wilson,§ Bezuayehu Teshome,‡ Sandeep Gorantla,∥ Mark H. Rümmeli,∥ Thomas Bublat,⊥ Eugenio Zallo,‡ Guodong Li,†,‡ David G. Cahill,§ and Oliver G. Schmidt†,‡ †
Material Systems for Nanoelectronics, Technische Universität Chemnitz, 09111 Chemnitz, Germany Institute for Integrative Materials, IFW Dresden, 01069 Dresden, Germany § Department of Materials Science and Engineering, University of Illinois, Champaign, Illinois 61820, United States ∥ Institute of Complex Materials, IFW, 01069 Dresden, Germany ⊥ Max-Planck-Institut für Intelligente Systeme, Heisenbergstraße 3, 70569 Stuttgart, Germany ‡
S Supporting Information *
ABSTRACT: The decrease of thermal conductivity is crucial for the development of efficient thermal energy converters. Systems composed of a periodic set of very thin layers show among the smallest thermal conductivities reported to-date. Here, we fabricate in an unconventional but straightforward way hybrid superlattices consisting of a large number of nanomembranes mechanically stacked on top of each other. The superlattices can consist of an arbitrary composition of n- or p-type doped single-crystalline semiconductors and a polycrystalline metal layer. These hybrid multilayered systems are fabricated by taking advantage of the selfrolling technique. First, differentially strained nanomembranes are rolled into three-dimensional microtubes with multiple windings. By applying vertical pressure, the tubes are then compressed and converted into a planar hybrid superlattice. The thermal measurements show a substantial reduction of the cross-sectional heat transport through the nanomembrane superlattice compared to a single nanomembrane layer. Time-domain thermoreflectance measurements yield thermal conductivity values below 2 W m−1 K−1. Compared to bulk values, this represents a reduction of 2 orders of magnitude by the incorporation of the mechanically joined interfaces. The scanning thermal atomic force microscopy measurements support the observation of reduced thermal transport on top of the superlattices. In addition, small defects with a spatial resolution of ∼100 nm can be resolved in the thermal maps. The low thermal conductivity reveals the potential of this approach to fabricate miniaturized on-chip solutions for energy harvesters in, e.g., microautonomous systems. KEYWORDS: Thermal conductivity, superlattice, rolled-up nanotechnology, SiGe, GaAs, scanning thermal AFM, time-domain thermoreflectance
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interface.7−10 For instance, rough interfaces efficiently degrade the coherent transport observed in AlAs/GaAs superlattices.11 In the majority of previously investigated systems, the thermal interfaces are formed by physical vapor deposition (PVD). Despite the very intimate contact type, a thermal transport reduction is usually observed, and joints of highly dissimilar material can further increase this thermal resistance.12 Depending on the material system, the reported12,13 interfacial conductivities (G) vary substantially from G ≈ 10 MW m−2 K−1 to ∼700 MW m−2 K−1. Because of the large heat generation of many surface mounted devices (SMDs), studies have been conducted to improve their thermal transport properties.14,15 Whereas for SMDs a high conductivity is desired, for thermal energy converters the material system
ncreasing demands in energy efficiency and production have triggered large interest in the development of thermoelectric devices with the potential for efficient energy conversion. However, the delicate interplay between the electrical and thermal conductivity makes it extremely difficult to design effective strategies for optimizing the thermoelectric performance. Hicks and Dresselhaus suggested that nanostructured materials could provide a route toward a high thermoelectric figure of merit, ZT,1 and thus be explored for a wide range of applications including microelectronic thermal management and thermoelectric energy conversion. Over the past years, significant reduction in thermal conductivity has been achieved by periodic structures such as superlattices.2−4 The cross-plane thermal conductivity in such superlattices is usually more suppressed when compared to the in-plane conductivity.3,5 The interfaces between neighboring layers in superlattices can act as efficient phonon barriers,6 and the resulting thermal interfacial resistance is found to be very sensitive to the exact type of © XXXX American Chemical Society
Received: December 30, 2013 Revised: March 26, 2014
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Figure 1. | Fabrication of hybrid superlattices. (a) The basic planar layer system consists of a sacrificial layer (red), a strained semiconducting bilayer (green), and optional metallic layers (orange). (b) Selective removal of the sacrificial layer converts the planar structure into a rolled tube; three turns are shown. (c) A silanated silicon stamp is pressed against the 3D structure at 200 °C , which (d) converts the tube into a planar hybrid superlattice. (e−k) Optical microscopy images of rolled and pressed-back nanomembrane superlattices. Rolled Si tube with six turns before (e) and after pressing into a superlattice (f), consisting of 12 Si nanomembranes. Rolled single-crystalline In0.2Ga0.8As/GaAs with additional Cr/Pd layers before (g) and after pressing into a hybrid semiconductor/metal superlattice (h). Other metal layers incorporated into the compressed superlattices include (i) Cr/Au and (j) TiCr. (k) A millimeter long section of a pure pressed-back In0.2Ga0.8As/GaAs semiconductor superlattice. The rolling directions are indicated by red arrows.
selectively etching the underlying sacrificial layer, the strained layers self-roll into three-dimensional tubular heterostructures (Figure 1b).24−31 By applying a high pressure, the tubes are then compressed and converted into mechanically joined planar superlattices with multiple interfaces (Figure 1c,d).17 The rolling technique allows for the incorporation of additional functional layers such as thin metal films or specific molecular layers acting as potential phonon filters.32,33 The versatility of the fabrication process is demonstrated by the optical micrographs of different hybrid superlattices (Figure 1e−k). For example, a section of a several millimeters long Si tube is shown in Figure 1e. The rolled multiturn tube is then compressed to form a mechanically joined all-Si superlattice (Figure 1f). To the best of our knowledge, this is the first report of pure semiconducting superlattices fabricated with this technique. In Figure 1g,h, a rolled tube based on strained InGaAs/GaAs and additional Cr/Pd layers is shown before and after compression, respectively. Other combinations of hybrid semiconductor/metal superlattices are also possible by the incorporation of different metal layers into the superlattices, such as Cr/Au (Figure 1i) and Ti/Cr (Figure 1j). For comparison, mechanically joined pure III−V semiconductor superlattices without any metal insertion can also be fabricated (Figure 1k). The width, height, and lengths of the superlattices can be set a priori by the two-dimensional processing. Here, the total thickness of each of the unreleased semiconducting/metal nanomembranes is t = 115 nm. Three distinct regions can be identified on the as-fabricated samples, namely, the unreleased hybrid nanomembrane (right side of the optical images), the superlattice (center), and the reference substrate exposed after the rolling process (left).
should show very low thermal conductivities. Normally, the interfacial resistance of two mechanically joined materials is orders of magnitude larger than the corresponding interface formed by PVD. For instance, a much larger thermal transport reduction was reported for a single mechanical interface between a transferred metal nanomembrane and a SiO2 substrate when compared to the corresponding PVD grown material.16 In this work, we fabricate hybrid multilayered systems by rolling and pressing back strained nanomembranes (Figure 1). The compression technique17 allows to create mechanically joined superlattices with a large number of mechanically joined interfaces between entirely different material classes. The superlattices may consist of any combination of semiconducting, metallic, oxide, or molecular layers18−20 and are interesting to be investigated both fundamentally as well as for nanothermoelectric applications. To demonstrate the versatility of this technique, Figure 1 displays a large variety of asfabricated metal/semiconductor superlattices. Charge carrier concentrations, strain, and dimensions of the superlattices are controlled by conventional 2D deposition techniques and standard semiconductor processing technologies. As shown in Figure 1a, the core system consists of single crystalline semiconductor nanomembranes, grown by molecular beam epitaxy (MBE), onto a sacrificial layer. We consider two different semiconductor materials: the first system consists of a 40 nm Ge sacrificial layer and a 20 nm Si strained nanomembrane.21,22 The second one consists of a 40 nm AlAs sacrificial layer and a strained 20 nm In0.2Ga0.8As/70 nm GaAs bilayer.18 We employed highly n- or p-type doped (>5 × 1018 cm−3) semiconductors in order to simultaneously increase/decrease the electrical/thermal conductivity.23 By B
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Figure 2. Cross-sectional TEM investigations of the interfaces of the hybrid superlattices. (a) All-Si superlattice consisting of 20 nm mechanically joined silicon layers (for top-view refer to Figure 1f). The side-walls of the Si superlattice are dry-etched by FIB. (b) Mechanical interface between GaAs and In0.2Ga0.8As nanomembranes. (c) Overview and (d) high-resolution image of a similar interface after incorporation of a thin Cr/Pd metal film (top-view Figure 1h). The elevated pressure and temperature during application of the compression technique leads to a diffusion of the palladium across the interface into the single-crystalline semiconductor.
Figure 3. Time-domain thermoreflectance (TDTR) maps of hybrid III−V superlattices. TDTR maps (500 × 88 μm2) of a hybrid III−V + Cr/Pd superlattice (a) transferred to a new GaAs host substrate and (b) as-fabricated with the thermal conductivity color-coded from 0.1 (blue) to 200 W m−1 K−1 (red). The pixel size is 4 μm2. Pixels with optical TDTR artifacts are whited-out (see Supporting Information). Inset: Dark field image of the laser spot (r ≈ 3.8 μm) adjusted on top of the superlattice. (c) Line scan along the superlattice, averaged over two neighboring pixel lines as indicated by the green arrow in panel b. (d) Cross-sectional scan of the dashed rectangle in panel b. Each data point/error bar is the average/root-mean-square of all values in the xdirection. Averaged red/violet points consist of most/some pixels with large Vin. Both curves take all measured pixels into account.
We investigated the interfaces by high-resolution transmission electron microscopy (TEM), see Figure 2. The crosssectional images of the mechanically joined semiconductor superlattices reveal abrupt interfaces without any visible voids between the layers. The all-Si superlattice is shown in Figure 2a and the InGaAs/GaAs superlattice in Figure 2b. In the silicon system, we expect a thin surface oxide21 as the rolling is done in H2O2; however, the thermal resistance from this oxide layer is negligible. In the III−V system no oxide is present as the rolling media (HF or HCl) is usually also used to remove the native oxide.18,20 The contacting interface is very thin (smaller than ∼1 nm), which is not surprising since the as-grown nanomembranes have atomically flat surfaces. The incorporation of metal between these windings further improves the mechanical contact. As shown in Figure 2c,d, the pressing conditions lead to a partial diffusion of the 20 nm thick Pd film across the interface into the single-crystalline InGaAs semiconductor, which can be observed throughout the superlattices. In all cases, the single crystallinity of the semiconductors is preserved during all process steps. Therefore, after roll and press-back, well-defined mechanical interfaces are created in addition to the existing interfaces formed during the physical vapor depositions. We expect the mechanical interfaces to have a large impact on the thermal transport properties due to the weak interfacial bonding and imperfect contact.16 Indeed, the thermal conductivity maps in Figure 3 reveal a large suppression of the thermal conductivity across the hybrid III−V/metal superlattice (see cross-section in Figure 2c) when compared to the bulk GaAs substrate. The thermal measurement maps are obtained using scanning timedomain thermoreflectance (TDTR) measurements. Details of our measurement technique and method for data analysis have been described previously34 (see Supporting Information). The hybrid III−V and Si superlattices were measured with a 1/e2 laser beam radius of ∼3.8/2.6 μm, and the pump modulation frequency was set to 1.6/9.8 MHz, respectively. The super-
lattice in Figure 3a,b was transferred/not transferred to a new position prior to pressing, and both structures exhibit similar features. For a better comparison, all thermal maps presented in this work have the same logarithmic scale from λ = 0.1 to 200 W m−1 K−1. The measured data are analyzed with a model for heat flow in layered structures.35 Our model assumes that the measured inphase and out-of-phase changes in the probe beam’s reflected intensity are proportional to temperature oscillations at the surface of the solid. In the in-plane direction, we assume a semiinfinite solid, i.e., boundaries are not taken into account. Both of these assumptions break down near the side walls of the superlattice, which can result in unphysical values for the TDTR derived thermal conductivity. The TDTR measurements in the center of the superlattice are not sensitive to the thermal transport near the edges as the heat diffusion length (∼0.5 μm) is smaller than the laser beam diameter and superlattice width, which are the in-plane length-scales in this problem. Furthermore, topographic defects such as small variations of the surface height, small defects, or nanogaps between the superlattice layers may also cause artificial variations in TDTR measurements. The advantage of collecting measurement maps is that the spatial contrast allows spurious locations to be more easily identified and disregarded in the discussion (whited pixels in the maps). The criteria of accepting measurement points are explained in detail in the Figure S2, Supporting Information. Additionally, the map allows us to test the spatial distribution of the superlattices’ thermal conductivity and thus differences in the quality of the mechanical joints. The C
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transport reduction through the superlattice is clearly visible in the TDTR map in Figure 4a (see also Figure S3, Supporting
maps verify that the transfer procedure does not damage isolated regions of the superlattices. Averaging across multiple pixels provides a better value for the superlattice thermal conductivity. The averaged crosssection of the region indicated by the dashed rectangle in Figure 3b shows very reproducible values on the GaAs substrate of λ ≈ 43 W m−1 K−1, see Figure 3d. This result is close to the values reported in the literature for heavily doped GaAs.36 A clear thermal transport reduction is observed across the superlattice. The spatial dependence of the reduced thermal conductivity along the central part of the superlattice is shown in Figure 3c. The values are averaged over the two neighboring lines close to the center of the superlattice. Topological defects on the top of the superlattices can be clearly identified by the sharp peaks in the graph. By averaging over all accepted positions of the 0.5 mm long tube section, a thermal conductivity of λ = 1.5 W m−1 K−1 with a standard deviation of 0.3 W m−1 K−1 is obtained. These low values present a 30× reduction of the thermal transport properties by the mere incorporation of multiple interfaces. A thermal conductivity of 1.5 W m−1 K−1 corresponds to a thermal conductance per membrane of GTDTR = λ/t = 13 MW m−2 K−1, with t = 115 nm. This is low considering the high thermal conductivities of the individual multilayer materials. We attribute this low value to the extra thermal resistance from the mechanically joined interfaces between the stacked nanomembranes. By estimating the thermal conductance intrinsic to an individual membrane (Gmemb), we can deduce the conductance reduction caused by the mechanically joined interfaces (Gmech). Each t = 115 nm membrane consists of 20 nm In0.2Ga0.8As, 70 nm GaAs, 5 nm Cr, 20 nm Pd, and an evaporated semiconducting/metal interface. We assume the thermal conductivities36 are InGaAs layer λInGaAs = 8, the GaAs layer λGaAs = 43, and the Cr/Pd layer λCrPd = 50 W m−1 K−1. The conductance of the evaporated interface between the Cr and GaAs has not been previously measured; however, a value of Gevap = 200 MW m−2 K−1 is a typical interfacial thermal conductance for many other Cr/dielectric systems.37 The conductance accounts for the thermal resistance due to interfacial phonon scattering. Thermal conductance values add like resistors in parallel:
Figure 4. TDTR maps of Si superlattices. (a) TDTR map (200 × 30 μm2) of the hybrid superlattice with the thermal conductivity colorcoded from 0.1 (blue) to 200 W m−1 K−1 (red). Pixel size is 1 μm2. Large variations of Vin are whited-out. (b) Untreated section along the center of the superlattice, as indicated by the arrow. The right side of the superlattice with a larger amount of topographic features is indicated by the dashed curve. (c) Cross-sectional scan of the dashed rectangle in panel a. Each data point is the average of all values along the x-direction. Defect pixels are indicated in red.
Information). In the averaged cross-section in Figure 4c, reproducible thermal conductivities of the silicon substrate (left side) are obtained around λ ≈ 135 W m−1 K−1, comparable to the Si bulk values.36 The unreleased Si/Ge layers on top of the Si substrate (right side) exhibits slightly decreased values around ∼100 W m−1 K−1. No similar difference in thermal conductivity between the InGaAs/GaAs/AlAs trilayer and GaAs substrate can be observed in Figure 3d because we used a lower pump modulation frequency (1.6 vs 9.8 MHz), which decreases the sensitivity of the TDTR measurement to the near surface region. As shown in Figure 4b, similar transport reduction is obtained along the entire superlattice with a thermal conductivity of 0.7 ± 0.3 W m−1 K−1. The data is taken from the center of the superlattice, as indicated by the arrow. The low conductivity of the superlattice composed of 12 Si nanomembranes represents a transport reduction of more than 2 orders of magnitude. A similar analysis as described above for the III−V superlattice suggests that Gmech = 30 MW m−2 K−1 for the Si superlattice. Interestingly, this is a factor of 2 higher compared to the mechanically joined interfaces of the III−V system. In order to obtain a more reliable insight into the spatial dispersion of thermal conductivity values, we employed a special scanning thermal microscope (SThM).39 With this scanning probe technique, the lateral resolution can be increased by over 1 order of magnitude compared to our TDTR.40 The SThM cantilever on top of the superlattice is shown in the inset in Figure 5a. The cantilever has specially designed metal wirings to the apex, which permits to apply temperatures up to 130 °C by Joules heating (see also Supporting Information). Several models have been employed to derive an absolute conductivity value with SThM methods,39,41−43 yet the varying thermal contacts on the same sample and between different measurements on the same area under ambient conditions makes it a difficult task.42 Here,
Gmech = (GTDTR −1 − Gmemb−1)−1 = (GTDTR −1 − (tCrPd /λCrPd + tGaAs/λGaAs /λInGaAs −1
+ Gevap−1))
with t the respective thicknesses. Therefore, the total conductance of the membrane without mechanical interfaces is expected to be near Gmemb = 100 MW m−2 K−1. For the mechanically joined interfaces we thus obtain Gmech = 15 MW m−2 K−1. Typical approaches for joining interfaces macroscopically result in very poor contacts and therefore the interface conductance values are typically15,38 on the order of 0.1 MW m−2 K−1. Our results are closer to the interface conductance values of evaporated interfaces, which typically range between 20 and 500 MW m−2 K−1 and are consistent with prior measurements for thin nanomembranes mechanically transferred to a host substrate.16 Similar results are obtained from the silicon superlattice (see TEM Figure 2a), which consists of several mechanically joined single-crystalline 20 nm thin Si nanomembranes. The thermal D
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estimate the resolution limit of our SThM setup to be around 100−300 nm. We also investigated the III−V Cr/Pd superlattice system with this high lateral resolution technique. The topography image (Figure 5e) shows smooth surfaces both on the reference substrate as well as on the 6× multilayered hybrid system. As expected, the thermal map (Figure 5f) proves a substantial thermal transport reduction on top of the superlattice. In contrast to the Si system, the AFM measurements of the III−V Cr/Pd superlattice do not show the generation of defect particles after pressing. The SThM map appears more homogeneous compared to the respective TDTR results. A possible explanation for the observed differences between both measurement techniques is that the depth resolution of SThM is smaller than TDTR, which also explains the high lateral resolution. As the tip scans across a high topographic feature such as the superlattice, the finite width of the tip causes it to be lifted and a worsened thermal contact is recorded for some lateral distance. In order to rule out the possibility that the observed transport reduction is caused by this tip-convolution edgeeffect,44 we prepared a step of similar height (200 nm) by dryetching a pristine Si wafer (Figure 5c). The respective thermal map in Figure 5d shows no detectable variations on top of the step compared to the reference substrate. Directly at the step edge, spurious measurement values with a lateral influence of less than 200 nm are observed (darker vertical line). Similar results are obtained for different step heights, see Figure S5, Supporting Information. As in the case of Si, the reference step etching into a pristine GaAs wafer of similar height shows no significant thermal response signal (Figure 5g,h). Thus, the substantial thermal transport reduction is indeed caused by the superlattices. Conclusion. A substantial thermal transport reduction of 2 orders of magnitude is achieved in all the investigated rolled and pressed-back nanomembrane superlattices. By combining the absolute values of the thermal mapping of the TDTR method (resolution ≈ 2 μm) and the more qualitative SThM method (resolution ≈ 100 nm), a better understanding of the thermal transport properties of the hybrid superlattices is achieved. These results offer a promising path to reduce the thermal conductivity by the incorporation of mechanical interfaces. By the roll and press-back techniques, a large variety of different types of interfaces with different materials such as metals, semiconductors, oxides, and molecules can be produced. The technique allows the straightforward integration of single-crystalline p- and n-type semiconductors necessary to fabricate thermoelectric generators.
Figure 5. Scanning thermal AFM (SThM) on the superlattices. Topography on the left side, thermal maps (scale 300 mV) on the right. (a) The silicon superlattice (240 nm height) in the middle of the image consists of 12 Si nanomembranes. (b) Thermal measurements reveal a voltage difference between superlattice and substrate of 160 mV. Inset shows the SThM cantilever during measurement. Reference sample, consisting of (c) a 200 nm step etched into a pristine Si wafer, shows (d) no thermal response beside the negligible edge effect. (e) Hybrid III−V/Cr/Pd superlattice with an approximate height of 450 nm and 6 interfaces. (f) A thermal voltage difference of 80 mV is detected. Reference sample, consisting of (g) a 400 nm step etched into a pristine GaAs wafer, shows (h) no thermal response. A heating voltage of 1 V and 1000× gain is used throughout all thermal maps.
we take advantage of the combined absolute TDTR values with the higher resolution SThM measurements for a detailed description of the spatial thermal conductivity distribution. The topographic image in Figure 5a is able to resolve all details of the rolled and pressed-back silicon superlattice: the Si substrate exposed after the rolling process (right), the superlattice composed of 12 Si nanomembranes (center), the underetched and backbonded single Si nanomembrane (left), and the unetched Si/Ge multilayer (left corner). The thermal map in Figure 5b is acquired during the same scan as the topography. The same resolution is achieved, and all the types of interfaces can be detected: the reference Si substrate (right) has a slightly higher conductivity compared to the Si/Ge layer (left). On top of the superlattice, a substantial transport reduction is obtained (dark colors) with a voltage difference of ∼110 ± 12 mV. As expected from the TDTR measurements (Figure 4b), the conductivity distribution on top of the superlattice appears to be quite homogeneous with variations around 10%. The advantage of the SThM maps is the capability to detect the thermal properties of small topographical features such as the step edge caused by the end of the rolled nanomembrane, see Figure S6, Supporting Information. Further, as shown in Figure S7, Supporting Information, sub μm particles as well as their nonhomogenous spatial distribution can be resolved. As they are observed only close to the rolled-down Si tube, they most probably originate from transferred parts of the Si nanomembrane after pressing. As shown in Figure S7b,c, Supporting Information, these small topographic features can be used to
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ASSOCIATED CONTENT
* Supporting Information S
Detailed fabrication methods, structure of the semiconducting multilayers, and information about the press-back method, as well as further thermal investigations. This material is available free of charge via the Internet at http://pubs.acs.org.
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AUTHOR INFORMATION
Corresponding Author
*(D.G.) Tel: +49-371-5347872. Fax: +49-371-5347871. E-mail:
[email protected] E
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Author Contributions
(11) Luckyanova, M. N.; et al. Coherent phonon heat conduction in superlattices. Science 2012, 338, 936−939. (12) Lyeo, H.-K.; Cahill, D. G. Thermal conductance of interfaces between highly dissimilar materials. Phys. Rev. B 2006, 73, 144301. (13) Costescu, R. M.; Wall, M. A.; Cahill, D. G. Thermal conductance of epitaxial interfaces. Phys. Rev. B 2003, 67, 054302. (14) Huang, I.-Y.; et al. Development of low-cost micro-thermoelectric coolers utilizing MEMS technology. Sens. Actuators Phys. 2008, 148, 176−185. (15) Song, W.-B.; Sutton, M. S.; Talghader, J. J. Thermal contact conductance of actuated interfaces. Appl. Phys. Lett. 2002, 81, 1216− 1218. (16) Oh, D.-W.; Kim, S.; Rogers, J. A.; Cahill, D. G.; Sinha, S. Interfacial thermal conductance of transfer-printed metal films. Adv. Mater. 2011, 23, 5028−5033. (17) Zander, T.; et al. Planar hybrid superlattices by compression of rolled-up nanomembranes. Appl. Phys. Lett. 2009, 94, 053102. (18) Deneke, C.; Songmuang, R.; Jin-Phillipp, N. Y.; Schmidt, O. G. The structure of hybrid radial superlattices. J. Phys. Appl. Phys. 2009, 42, 103001. (19) Deneke, C.; Jin-Phillipp, N.-Y.; Loa, I.; Schmidt, O. G. Radial superlattices and single nanoreactors. Appl. Phys. Lett. 2004, 84, 4475− 4477. (20) Deneke, C.; et al. Interfaces in semiconductor/metal radial superlattices. Appl. Phys. Lett. 2007, 90, 263107. (21) Songmuang, R.; Deneke, C.; Schmidt, O. G. Rolled-up microand nanotubes from single-material thin films. Appl. Phys. Lett. 2006, 89, 223109. (22) Cavallo, F.; Songmuang, R.; Schmidt, O. G. Fabrication and electrical characterization of Si-based rolled-up microtubes. Appl. Phys. Lett. 2008, 93, 143113. (23) Asheghi, M.; Kurabayashi, K.; Kasnavi, R.; Goodson, K. E. Thermal conduction in doped single-crystal silicon films. J. Appl. Phys. 2002, 91, 5079−5088. (24) Mendach, S.; et al. Preparation of curved two-dimensional electron systems in InGaAs/GaAs-microtubes. Phys. E 2004, 23, 274− 279. (25) Grimm, D.; et al. Rolled-up nanomembranes as compact 3D architectures for field effect transistors and fluidic sensing applications. Nano Lett. 2013, 13, 213−218. (26) Bof Bufon, C. C.; et al. Self-assembled ultra-compact energy storage elements based on hybrid nanomembranes. Nano Lett. 2010, 10, 2506−2510. (27) Thurmer, D. J.; Bof Bufon, C. C.; Deneke, C.; Schmidt, O. G. Nanomembrane-based mesoscopic superconducting hybrid junctions. Nano Lett. 2010, 10, 3704−3709. (28) Rogers, J. A.; Lagally, M. G.; Nuzzo, R. G. Synthesis, assembly and applications of semiconductor nanomembranes. Nature 2011, 477, 45−53. (29) Cavallo, F.; Lagally, M. G. Semiconductors turn soft: inorganic nanomembranes. Soft Matter 2010, 6, 439. (30) Cho, J.-H.; et al. Nanoscale origami for 3D optics. Small 2011, 7, 1943−1948. (31) Lee, K.-N.; et al. Stress-induced self-rolled metal/insulator bifilm microtube with micromesh walls. J. Micromech. Microeng. 2013, 23, 015003. (32) Nozaki, D.; Sevinçli, H.; Li, W.; Gutiérrez, R.; Cuniberti, G. Engineering the figure of merit and thermopower in single-molecule devices connected to semiconducting electrodes. Phys. Rev. B 2010, 81, 235406. (33) Losego, M. D.; Grady, M. E.; Sottos, N. R.; Cahill, D. G.; Braun, P. V. Effects of chemical bonding on heat transport across interfaces. Nat. Mater. 2012, 11, 502−506. (34) Huxtable, S.; Cahill, D. G.; Fauconnier, V.; White, J. O.; Zhao, J.-C. Thermal conductivity imaging at micrometre-scale resolution for combinatorial studies of materials. Nat. Mater. 2004, 3, 298−301. (35) Cahill, D. G. Analysis of heat flow in layered structures for timedomain thermoreflectance. Rev. Sci. Instrum. 2004, 75, 5119−5122.
D.G. coordinated the project. E.Z. grew the MBE samples. D.G. fabricated the hybrid superlattices. T.B. optimized the pressback technique. R.B.W. performed the TDTR measurements. D.G., B.T., and G.L. performed the SThM measurements. S.G. and M.H.R. performed the TEM measurements. D.G., R.B.W., O.G.S., and D.G.C. analyzed the data. O.G.S. had the idea and initiated the project. D.G. wrote the article with input from all authors. Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS Christoph Deneke from the Brazilian Nanotechnology National Laboratory, Francesca Cavallo from the University of Wisconsin−Madison, and Mathieu Stoffel from the MaxPlanck-Institut für Festkörperforschung, Stuttgart, are acknowledged for part of the MBE growth. Gianaurelio Cuniberti (TU Dresden, Germany), Peixuan Chen and Armando Rastelli (Uni Linz, Austria), Carlos Cesar Bof Bufon (LNNano, Brazil), and Erwin Peiner and Andrej Stranz (TU Braunschweig, Germany) are acknowledged for fruitful discussions. Martin Bauer, Tina Sturm, and Stefan Baunack are acknowledged for technical assistance and Pablo R. Siles for assistance on measurements (TU Chemnitz). R.B.W. acknowledges the U.S. Department of Defense for the NDSEG fellowship that supported him during this work. The work at U. Illinois was supported by the U.S. Air Force Office of Scientific Research under grant number FA9550-12-1-0073 and at IFW Dresden by the DFG project SPP 1386, Nanostructured Thermoelectric Materials: Theory, Model Systems and Controlled Synthesis.
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ABBREVIATIONS TDTR, time-domain thermoreflectance; SThM, scanningthermal microscope; SEM, scanning electron microscope; TEM, transmission electron microscope; SMD, surface mounted device; PVD, physical vapor deposition; FIB, focused ion beam; InGaAs, In0.2Ga0.8As
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REFERENCES
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