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Minimizing self-heating and heat dissipation in ultra-scaled nanowire transistors Reto Rhyner, and Mathieu Luisier Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.5b04071 • Publication Date (Web): 04 Jan 2016 Downloaded from http://pubs.acs.org on January 5, 2016
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Minimizing self-heating and heat dissipation in ultra-scaled nanowire transistors Reto Rhyner and Mathieu Luisier∗ Integrated Systems Laboratory, ETH Zurich, 8092 Zurich, Switzerland E-mail:
[email protected] Abstract Through advanced electro-thermal simulations we demonstrate that self-heating effects play a significant role in ultra-scaled nanowire field-effect transistors, that some crystal orientations are less favorable than others ( for n-type applications, for p-type ones), and that Ge might outperform Si at this scale. We further establish a relationship between the dissipated power and the electrical mobility and another one between the current reduction induced by self-heating and the phonon thermal conductivity. Keywords: Scaling, electro-thermal transport, device simulation, nanowire transistors
The mass production of the 14 nanometer technology node of the semiconductor industry started at the end of 2014. It relies either on the second generation of Si Fin field-effect transistors (FinFETs) 1 or on fully depleted Silicon on insulator (FD-SOI) FETs. 2 In both cases the gate contact has a length comprised between 20 and 25 nm. Although the reduction of the transistor dimensions has considerably slowed down in the recent past 3 the point where Moore’s scaling law will come to an end is getting closer and closer. Many device engineers believe that 5 nm gate lengths represent the ultimate limit under which no conventional logic switch can properly operate. ∗ To
whom correspondence should be addressed
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Promising results towards 5 nm transistors have already been reported, e.g. in 2012 a carbon nanotube field-effect transistor (FET) with a gate length of 9 nm and good electrical performance was successfully demonstrated. 4 Parallel to the on-going experimental efforts many theoretical works have started tackling this issue too. 5–10 In these studies gate-all-around (GAA) configurations and ultra-thin materials have been identified as top candidates to provide an excellent electrostatics control, which is a critical requirement in the sub-10 nm range. Beside that it has been recognized that the channel material should not exhibit a (too) low band gap and/or transport effective mass since these characteristics drastically increase source-to-drain and band-to-band tunneling leakage, thus deteriorating the sub-threshold regime. Based on these key findings it appears that Si GAA nanowire FETs and logic switches made of single- or few-layer transition metal dichalcogenides are among the most promising ones at 5 nm gate lengths. The theoretical results briefly summarized above have all been obtained assuming ballistic transport conditions where electrons and holes do not interact with their surrounding. Such an approximation is justified when the total transistor length is shorter than the mean free path for scattering of the charge carriers. However, we recently demonstrated that even in ultimately scaled Si GAA nanowire FETs with a channel length of 5 nm, transport along the crystal axis, and a perfect atomic fitting (no surface roughness), electron-phonon interactions cause a drain current reduction of roughly 30% 11 as compared to the ballistic limit of transport. Furthermore, phonon emissions on the drain side of the transistor locally increase the lattice temperature and contribute to an additional current decrease of 30%. These self-heating effects, together with the associated power dissipation, might severely limit the performance of nanoscale devices and should therefore not be neglected in theoretical analyzes. Modeling self-heating is not a straightforward task since it involves a precise description of the electronic and thermal properties of the structures of interest as well as their self-consistent coupling. Classical 13 and semi-classical 14–16 treatments of self-heating have been used for a long time, but they are not really suitable to deal with ultra-scaled devices whose behavior is dominated by quantum mechanical phenomena (energy quantization, geometrical confinement, tunneling) and
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whose active region is composed of a countable number of atoms. Full-band and atomistic solvers including all the necessary physics to handle self-heating at the nanoscale have been developed too, but they are usually restricted to very small systems with less than 100 atoms. 17,18 In this paper we present a comprehensive study of self-heating in ultra-scaled Si and Ge nanowire transistors with a 5 nm gate length, different transport directions, and composed of thousands of atoms. It is based on the advanced quantum mechanical simulation approach of Ref. 12 Instead of looking for the device configuration that provides the highest ON-current at a given OFFcurrent, we fix the ON-state current to the same level in all cases, 1500 µ A/µ m (normalized by the nanowire diameter), extract relevant thermal metrics (current reduction induced by self-heating, maximum lattice temperature, lattice temperature in the source, and dissipated power), and compare them with each other. By doing so we are not only able to identify the component with the best electro-thermal properties, but also to show that the power dissipated within the semiconducting channel decreases as the phonon-limited mobility of the nanowires increases and that the importance of self-heating effects diminishes as the lattice thermal conductivity enhance. These nonobvious relationships could help device engineers design next-generation nano-transistors with a reduced internal power consumption and heat dissipation. The investigated gate-all-around nanowire FETs are schematized in Fig. 1. The channel is either made of Si with transport along the , , and crystal axis or of oriented Ge. Both n- and p-type configurations are considered. All structures have the same total length, 35 nm, decomposed into two 15 nm, doped source and drain extensions and a 5 nm gate contact. To maintain a good electrostatics control despite the short gate dimensions the diameter of the nanowires is set to 3 nm and the channel is surrounded by 3 nm HfO2 dielectric layers, except on the source and drain regions where a low κ material is used. The contact series resistances are not taken into account, but their maximum value is discussed below. To simulate the I-V characteristics and the electro-thermal properties of these nanowire transistors a full-band and atomistic quantum transport approach is employed. It relies on the sp3 d 5 s∗ tight-binding model without spin-orbit coupling to account for the Si and Ge electronic struc-
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Figure 1: Schematic view of the n- and p-type ultra-scaled nanowire field-effect transistors (FET) examined in this work. They consist of a gate-all-around contact of length Lg =5 nm and source/drain extensions of length Ls =Ld =15 nm (doping ND/A =1e20 cm−3 ). The semiconductor channel has a diameter d=3 nm, it is either made of Si , Si , Si , or Ge , and is surrounded by 3 nm oxide layers (HfO2 with εR =20 under the gate contact, low-κ spacers with εR =5 on the source and drain extensions). The three bottom sub-plots show the atomic configuration for -, -, and -oriented channels. tures 19 and on a valence-force-field method including four interaction terms to describe the phonon modes and frequencies. 20 Quantum transport is solved within the Non-equilibrium Green’s Function (NEGF) formalism where the electron Green’s Functions G(E) at energy E are coupled to the phonon ones D(ω ) at frequency ω through scattering self-energies Σ(E) and Π(ω ). 12 More details about the exact form of the governing equations and applied approximations can be found in the Supporting Information. The G(E)-D(ω ) coupling drives both populations out-of-equilibrium and induces an energy exchange between them so that each time an electron emits (absorbs) a phonon it looses (gains) energy that is transferred to (taken away from) the phonon bath. Hence, the implemented solver ensures not only current, but also energy conservation. In all investigated devices the supply voltage VDD is equal to 0.6 V, the gate-to-source voltage Vgs =0 V at a drain-to-source voltage Vds =VDD corresponds to the OFF-state with an imposed 4 ACS Paragon Plus Environment
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Figure 2: (a) Transfer characteristics Id -Vgs at Vds =0.6 V for the Si nanowire FET from Fig. 1 with transport along the crystal axis. The currents with (dashed red lines) and without (solid blue lines) self-heating are plotted. They are normalized with the nanowire diameter d=3 nm. The SHCR quantity refers to the self-heating induced current reduction. (b) Effective lattice temperature profile along the same device as in subplot (a) at Vgs =0.4 V and Vds =0.6 V. The temperature is averaged over the nanowire cross section. Its maximum (Tmax ) and source (Tsource ) values are indicated. (c) Electron (blue line), thermal (phonon, green line), and total (red line) energy current flowing through the nanowire FET in sub-plot (a) at Vgs =0.4 V and Vds =0.6 V. The sign of the thermal current indicates its direction of propagation, either from left to right (positive) or from right to left (negative). The power dissipated as heat by the electrons between the source and the drain, Pdiss , is reported. (d) Maximum temperature Tmax and dissipated power Pdiss in the same transistor as before as a function of Vgs at Vds =0.6 V. leakage current IOFF =0.1 µ A/µ m. The work function of the gate contact was adjusted to align the OFF-current with Vgs =0 V. The ON-state current ION is fixed to 1500 µ A/µ m, a reasonable value for 5 nm gate length high performance transistors, but lower than the target of the International Technology Roadmap for Semiconductors (ITRS). 21 The required Vgs,act to obtain this current level can be calculated and used to estimate the maximum allowed contact series resistance RSD,max at the given supply voltage, assuming that the source and drain resistances are equal, i.e. RS =RD =RSD /2. In effect, the potential drop over RS in the ON-state, ION × RS should be smaller than the difference between the externally applied gate-to-source voltage (VDD ) and the internal value needed to reach ION =1500 µ A/µ m (Vgs,act ) so that RSD,max < 2 × |VDD − Vgs,act |/ION . In
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reality, RSD,max should be even smaller than predicted by the proposed model since the latter does not account for the difference between the external and internal Vds , which affects the current magnitude due to drain induced barrier lowering (DIBL). The extraction processes for the other considered metrics are summarized in Fig. 2 with the n-type, -oriented Si nanowire FET as an example. First, the self-heating induced current reduction (SHCR) concept is illustrated in sub-plot (a): two quantum transport simulations with electron-phonon scattering must be performed, one where the phonon population remains in equilibrium with its environment and the lattice temperature does not vary, another one where the phonons emitted (absorbed) by the electrons modify the local phonon population and induce an increase (decrease) of the lattice temperature. The generation of additional phonons with whom electrons have the possibility to interact causes a current reduction that can be attributed to selfheating. The SHCR measures therefore the difference between the current with an equilibrium and with a non-equilibrium phonon population. The effective lattice temperature shown in sub-plot (b) is derived from the non-equilibrium phonon population 12 and is characterized by a maximum value Tmax situated close to the drain side of the nanowire FETs. The source lattice temperature Tsource is also relevant since it reveals how quickly phonons can escape the active region. Sub-plot (c) reports the electron, phonon, and total energy current flowing through the simulated transistors. As mentioned above and demonstrated here, the total energy current is conserved in the present formalism. This allows one to determine the power dissipated by the electrons as heat, Pdiss : its value is smaller than ION ×VDD since it only accounts for the losses in the 35 nm long semiconducting region, not for the further electron/hole energy relaxation in the metallic contacts. Due to the very high thermal conductivity of metals heat dissipation poses a less important problem in the contacts than in the channel. Finally, in sub-plot (d) the Vgs dependence of Tmax and Pdiss is displayed: it can be seen that they exhibit a similar behavior, both curves being parallel. As a next step the Vgs,act , Tmax , Pdiss , Tsource , and SHCR data are extracted from the simulation of the eight nanowire FETs described in Fig. 1 at a ON-current ION =1500 µ A/µ m. The results
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Figure 4: Same as Fig. 3, but for the complementary p-type transistors in Fig. 1. Note that the Si nanowire FET is not capable of reaching ION =1500 µ A/µ m at IOFF =0.1 µ A/µ m within a Vgs budget of 0.6 V corresponding to the chosen supply voltage. p-type structure needs a large Vgs to reach its ON-state due to source-to-drain tunneling, (ii) the Si FETs with as transport direction are the least prone to self-heating, (iii) Si (Si ) has the highest lattice temperature and power dissipation in the n-type (p-type) case, and (iv) the -oriented Si nanowire cannot reach 1500 µ A/µ m within the allotted supply voltage. As shown in Fig. 2(d) for the Si n-FET and confirmed in Figs. 3 and 4 the maximum lattice temperature Tmax and the dissipated power Pdiss follow a similar trend. A direct correlation between the lattice temperature in the source Tsource and the current reduction induced by self-heating (SHCR) seems to exist too. To better understand the mechanisms that govern these quantities and relate them to more familiar observables, we have computed the phonon-limited electron/hole mobility µ ph and the lattice thermal conductivity κ ph of the transistors in Fig. 1 us-
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Table 1: Summary of the phonon-limited electron/hole mobility µ ph (second column) and phonon thermal conductivity κ ph (third column) corresponding to the eight different nanowire transistors in Fig. 1. All the µ ph and κ ph were calculated at the electron (n-type) or hole (p-type) density found at the top-of-the-potential barrier 23 under the ON-state condition (nToB , fourth column). The electron/hole mobility values follow the same trends as in Ref., 24 where their behavior has been extensively discussed. The variations in the thermal conductivities originate from quantum confinement that has a strong, orientation-dependent influence on the average phonon velocity. In Si nanowires, the latter reaches its maximum along the crystal axis, while it is smaller along and . The effective mass of the lowest (highest) conduction (valence) subband along the nanowire axis, m∗ is reported in the fifth column, while the maximum contact series resistance RSD,max =2 × |VDD −Vgs,act |/ION is given in the last column. n-Si n-Si n-Si n-Ge p-Si p-Si p-Si p-Ge
µ ph (cm2 /Vs) κ ph (W/Km) nToB (cm−3 ) 304 22.8 4.4e19 124 23.7 7.4e19 542 50.9 4.3e19 2000 32.6 2.2e19 47 19.5 8.2e19 1907 29.8 2.7e19 803 55.1 3.2e19 1622 32.1 2.1e19
m∗ 0.28 0.44 0.17 0.09 0.48 0.12 0.14 0.06
RSD,max (Ω · µ m) 206 0 194 208 0 168 192 65
ing the “dR/dL” method. 22 To be as accurate as possible, µ ph and κ ph have been evaluated in the presence of out-of-equilibrium, self-consistently coupled electrons and phonons, with a small bias difference ∆V =1 mV between the two nanowire extremities for µ ph and a temperature gradient ∆T =5 K for κ ph . In the chosen approach anharmonic phonon processes are not taken into account, as explained in the Supporting Information, so that the lattice thermal conductivity is totally determined by the interactions between the high density carriers and the phonons. The values of µ ph and κ ph as well as the electron and hole concentrations at which they have been calculated are given in Table 1. The latter also contains the transport effective mass m∗ of the nanowires and the maximum source/drain contact series resistance RSD,max . It is well-known that the mobility of a device can be approximated as µ ph ∼ q × τ ph /m∗ , 25 where q is the elementary charge, m∗ the effective mass of the underlying material, and τ ph the time between two scattering events, here an electron-phonon interaction. If we assume that the electrical power dissipation mainly occurs through the emission of optical phonons of energy h¯ ω ph,opt , then Pdiss /¯hω ph,opt measures the number of phonons that are emitted per second, which should be 9 ACS Paragon Plus Environment
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Figure 5: (a) Relationship between the phonon-limited mobility times the effective mass (time between two scattering events) and the dissipated power Pdiss divided by the optical phonon frequency h¯ ω ph,opt (number of phonons emitted per second) for the same nanowire FETs as before. The dashed line is just a guide for the eyes. (b) Relationship between the phonon thermal conductivity and the current reduction induced by self-heating in the same devices. inversely proportional to τ ph and to µ ph × m∗ . Hence, there should be a direct relationship between
µ ph × m∗ and Pdiss /¯hω ph,opt , a higher phonon-limited mobility at a given effective mass leading to a smaller phonon emission rate and less power dissipation as a consequence. This connection is verified in Fig. 5(a) for the eight nanowire transistors that have been simulated. The Pdiss /¯hω ph,opt vs. µ ph × m∗ curve obeys an exponential decay that is consistent with the above analysis. Note that the normalization of Pdiss with the phonon energy is essential since h¯ ω ph,opt =63 meV in Si, but only 37 meV in Ge. It has been shown in Ref. 12 that self-heating reduces the current magnitude because some of
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the phonons that are emitted close to the drain side of the transistors move towards the source extension where they interact with electrons, thus increasing their backscattering coefficient. 26 The more phonons propagate without perturbation from the location where they are generated to the source contacts, the less significant the current reduction induced by self-heating is. Since the lattice thermal conductivity best characterizes phonon transport a second relationship between κ ph and SHCR can be established, as shown in Fig. 5(b). It infers that the influence of self-heating decreases as the lattice thermal conductivity increases. The lattice temperature at the source site, Tsource correlates also very well with SHCR since it indicates how efficiently the emitted phonons can be evacuated from the active region of the nanowire FETs. In conclusion we have demonstrated that the interactions of electrons and phonons still give rise to serious electro-thermal effects (self-heating, increase of the lattice temperature, high electrical power dissipation) in ultra-scaled nanowire transistors with a 5 nm gate length. Their influence depends on the channel orientation and on the material. Furthermore, we have shown that the electron/hole mobility remains a meaningful concept in the investigated structures since it determines the amount of power dissipated within the semiconductor channel and the maximum lattice temperature located close to the drain contact. Similarly, the thermal conductivity controls the reduction of current through self-heating. When looking for the best transistor material at 5 nm gate lengths it might be thought that one with a very high mobility represents the optimal choice because it minimizes heat dissipation. However, such a candidate usually possesses a very low transport effective mass and therefore suffers more from source-to-drain tunneling leakage, as the analyzed Ge p-FET. Compromises will be necessary to keep self-heating effects as small as possible, while maintaining decent subthreshold properties. Also, the quality of the nanowire surfaces will be crucial, the lattice thermal conductivity being very sensitive to roughness.
Acknowledgement This work was supported by SNF Grants No. PP00P2_133591 and PP00P2_159314, by the EU 11 ACS Paragon Plus Environment
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FP7 DEEPEN project, and by a grant from the Swiss National Supercomputing Centre under Project No. s579. We also acknowledge PRACE for giving us access to Hornet at the High Performance Computing Center (HLRS) in Stuttgart, Germany.
Supporting Information Available Detailed description of the modeling approach and of the applied approximations. This material is available free of charge via the Internet at http://pubs.acs.org/.
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