LETTER pubs.acs.org/NanoLett
Modeling Novel Double-in-Plane Gate Electric-Double-Layer Thin-Film and Nanoscale Transistors Mingzhi Dai* and Qing Wan* Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201, People's Republic of China ABSTRACT: A novel double-in-plane gate oxide-based electric-double-layer (EDL) transistor structure applicable to thinfilm transistors (TFTs) and nanoscale transistors (nanoFETs) is proposed. An equivalent circuit model is provided to illustrate the operation mechanism. The double-in-plane gate structure can simplify device fabrication effectively and provide unique tunability of threshold. Specifically, the gate bias modulates the threshold voltage of TFT and nanoFET and effectively controls the transistor subthreshold swing and leakage current. Moreover, the EDL gate dielectric can lead to a high gate dielectric capacitance (>1 μF/cm2). These simulation results provide basic understanding needed to use and control EDL TFTs and nanoFETs in a novel manner. KEYWORDS: Double-in-plane gate structure, EDL TFTs, nanoFETs, simulation
T
hin-film transistors (TFTs) are one of the most fundamental state-of-the-art electronic devices.1,2 Meanwhile, inorganic nanoscale transistors (nanoFETs), such as nanoparticles, nanorods, and nanowires, are currently under active investigation as components for PV devices due to their potential for exploring new device concepts.3 6 Recently, the double-gate structures have been widely studied.7,8 The main goal of the structure is to improve the electrostatic control of the gate over the conductive channel. This is because, for the double-gate transistors, the gates control the energy barrier between the source and drain effectively. The double-gate design can modulate subthreshold swing and leakage current.8 Additionally, in-plane gate transistors have received a great deal of interest for applications in electronics due to their inherent advantage of self-alignment technology.9,10 In the case of this structure, the source, drain, and gate terminals are located on the same plane. However, among the group of nanodevices, TFTs and nanoFETs with double-in-plane gate structure are seldom reported. In this Letter, a double-in-plane gate oxide-based electricdouble-layer (EDL) structure for TFTs and nanoFETs is proposed, together with the simulation and modeling of this kind of interesting TFT structure. By using one of the double gates as the reference gate, electrical properties of this kind of EDL TFTs could be adjusted flexibly in a certain range. This structure is useful to broaden the application of EDL TFTs and nanoFETs,11,12 where the adjustment and stability of threshold voltage or on-current is required. The double-in-plane gate could be deposited on the SiO2-based solid electrolytes together with source and drain using only a nickel shadow mask. The interesting structure is modeled and simulated, which is of use for better control and understanding of this property-adjustable EDL TFTs and nanoFETs with double-in-plane gate.13 16 The fabrication of the typical double-gate devices is based on conventional planar process technologies.7,8 Nevertheless, steps r 2011 American Chemical Society
of hard mask deposition and EB lithography are needed in the process, which requires work from engineers and the equipment. If a more simple structure is given, these process procedures could be simplified effectively. Double-in-plane gate TFTs could be fabricated easily in this way. Initially, microporous SiO2 solid electrolyte films are developed directly on conductive ITO glass substrates. Afterward, the semiconductor channel is deposited. Consequently, the double gates are deposited onto the dielectrics with one mask, together with drain and source. The deposition is completed using radio frequency magnetron sputtering.11,12 Simulations based on semiconductor models and theories are performed.13 15 The equivalent circuit modeling of the gate capacitance of these double-in-plane gate EDL TFTs is also shown in Figure 1. The channel length is 80 μm, the channel width is 1000 μm, and the gate dielectrics thickness is equivalent to 1 nm electricdouble-layer (EDL). Either side of the double-in-plane gates (Gate1 and Gate2) could be regarded as two EDLs in series, and the capacitance of either gate could therefore be equivalent to the gate capacitance of 2 nm SiO2. We define the gate voltage applied on Gate1 and Gate2 as VG1 and VG2 and the drain current as IDS. The threshold voltage VTH is set to be the one leading to IDS as much as 10 8 A/μm. Considering the electric coupling effect between gate to gate, the structure would be regarded as two capacitors in series on both left gate side and right gate side of the device, respectively. This is due to the conductive layer, which acts as an intermediate electrode. As shown in Figure 2, the experimental results of the true inplane gate EDL device and those of the simulated conventional top-bottom double gate device are compared. In the modeling, Received: July 12, 2011 Revised: August 12, 2011 Published: August 17, 2011 3987
dx.doi.org/10.1021/nl202368z | Nano Lett. 2011, 11, 3987–3990
Nano Letters
LETTER
Table 1. Key Properties in TCAD Simulationa channel length
Immax
Immin
VJD
VJS
(μm)
(A/cm)
(A/cm)
(V)
(V)
80
0.671
1.22 10
1.39
0.92
100
0.535
9.7 10
1.32
0.91
150
0.354
5.21 10
1.25
0.90
11 12 12
a
Figure 1. Schematic of the double-in-plane gate device. The channel length is 80 μm and the gate dielectric thickness is equivalent to 1 nm electric-double-layer (EDL). Either side of both gates (Gate1 and Gate2) could be regarded as two EDL in series, and the capacitance of either gate could therefore be equivalent to the gate capacitance of 2 nm SiO2.
Immax and Immin refer to the maximum current density and minimum current density in the middle of the channel length, respectively, VJD and VJS are the potentials of the junction on the drain and source side of the main channel, respectively.
Table 2. Key Parameters in TCAD Simulation
Eg (eV) channel dopant (cm 3) μEFF (cm2/(V s))
Figure 2. Transfer curves with ITO channel materials. The filled point curve refers to the experimental results of the true double-in-plane EDL device, while the hollow points refer to the simulated IDS VG1 curve for constant Gate2 voltage VG2 = 0 V, where the top and bottom gates have the same gate capacitance equivalent to 2 nm thick SiO2. The results show the similar function of the double-in-plane gate structure and the top-bottom gate structure.
both gates of the top-bottom double gate device have the same gate capacitance, which is equivalent to 2 nm thick oxide dielectric, respectively. The nice fitting between the experimental results and simulation suggests our model might be reasonable. Under this in-plane structure, the gate potentials affect the key electronic properties of the channel, such as the transfer curve, in the similar manner with conventional top-bottom double gates. The physical geometry changes of the physical dimension of the device could affect the key properties of the in-plane double gate, including the carrier density and potential, as shown in Table 1. The simulation is based on standard TFT device simulations using TCAD tools.13 18 The TCAD simulations depend on analytical expressions to simulate the behavior of semiconductor devices. These semiconductor models include basic semiconductor equations, such as the transport equations and displacement current equation, together with basic theory of carrier statistics, such as Fermi Dirac and Boltzmann statistics, effective density of states (DOS) model, intrinsic carrier concentration, and energy band gap model. Additional details are given in refs 17 and 18. The availability of the simulation could be supported by the nice fitting for the measurement.15,16 The key fitting parameters for our simulation are shown in Table 2, which are in a reasonable range with the previous data we have shown in a single gate EDL TFT device.15,16 In Figure 3, IDS VG1 curve with VG2 as a constant and IDS VG2 curve with VG1 as a constant are shown in panels A and B of Figure 3. The symmetrical controllability behavior of
ITO
IGZO
3.65 0.9 1019
3.05 5 1017
30
10
Nc (cm
3
eV 1)
1 1020
1 1020
Nv (cm
3
eV 1)
1 1020
1 1020
Gate1 and Gate2 is demonstrated by Figure 3A and Figure 3B, which have the same shape of transfer curve and the same electrical properties such as VTH (0.1 V). In Figure 3C, IDS VG1 with different G2 values ( 1.0, 0.5, 0, 0.5 V) is given to demonstrate how VTH can be tuned. It is shown that with VG1 sweeping from negative to positive voltage ( 1.5 to 2 V), IDS would be increased. By adding VG2, VTH could be adjusted effectively in a range from negative value ( 0.55 V) to positive value (0.78 V) as shown in Figure 3C. The results suggest the tuning effect of double-in-plane gates is obvious and effective. As shown in Figure 4A, when the channel length L is changed from 80 to 150 μm (i.e., 80 μm, 100 μm, 150 μm) at the same constant VG2, VTH would be also tuned obviously. While changing the constant VG2 (i.e., 1.0 V, 0.5 V, 0, 0.5 V) at the same L, VTH is also different. Figure 4B illustrates that the transfer curve should be shifted significantly, by adjusting the equivalent silicon dioxide thicknesses of gate dielectrics (TOXeq), VTH of which could be tuned significantly from 0.5 to 0.95 V (the shift of VTH is 90%). Therefore, the controllability of the double-in-plane gates would be adjusted by tuning device structure design such as L and TOXeq. Recently, semiconductor nanowires have emerged as building blocks for PV devices, where studies have investigated fundamental device performance limits in several different nanowire structural motifs.3 6 To explore further the robust of the doublein-plane EDL structure design and its potential for more colorful applications, we have simulated the double-in-plane EDL structure with another semiconductor material. Figure 5 shows when channel materials are changed with the main parameters listed in Table 2, the corresponding VTH could be different from that for ITO. When the channel is In Ga Zn O (IGZO), VTH could be a positive value (0.94 V) instead of a negative one in the case of ITO ( 0.55 V) at the same constant VG2 value (VG2 = 0.5 V). Additionally, Figure 5 shows, at variant VG2 values (0, 0.5, 0.8 V), VTH for the IGZO channel could be tuned from 0.7 V (1.0 V), standing for the shift of VTH as much as over 50%. Therefore, the tunable device performance results in Figure 5 suggest the possible application of double-in-plane gate structure with different types of semiconductor channel materials 3988
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Figure 3. Transfer curves with ITO channel materials: (A) simulated IDS VG1 curve for constant Gate2 voltage VG2 = 0 V, where threshold voltage VTH is 0.1 V. (B) Simulated IDS VG2 curve for VG1 = 0 V, where VTH is 0.1 V. The results show symmetric function of Gate1 and Gate2. (C) The shift of IDS VG1 of double-in-plane gate EDL TFTs for variant VG2 ( 1.0, 0.5, 0, 0.5 V), suggesting VTH could be effectively changed from negative value ( 0.55 V) to positive value (0.78 V).
Figure 4. (A) The change of threshold voltage VTH of the double-in-plane gate EDL TFTs for variant channel length L (80, 100, 150 μm) and constant Gate2 voltage VG2 ( 1.0, 0.5, 0, 0.5 V) for ITO channel materials, where VTH is tuned from positive values (>0.5 V) to negative values (< 0.5 V). (B) The shift of IDS VG1 transfer curves of the double-in-plane gate EDL TFTs by adjusting the equivalent silicon dioxide thicknesses of gate dielectrics (TOXeq) with ITO channel materials, suggesting VTH changing from 0.5 to 0.95 V (the shift of VTH is 90%).
beside ITO. The semiconductor channel materials could be IGZO, group III nitride thin films, and semiconductor nanowires, the dopant and morphology of which can be readily controlled.3 5,19 Therefore, the application of this device configuration is likely to extend to other channel materials, such as semiconductor nanowires, and carbon nanotubes. The nanowire EDL device with single gate has been realized, proven to work properly, and published.19 The simulation for the nanowire EDL device with double-in-plane gate structure is performed and shown in Figure 6, using the key parameters comparable to the published parameters including the mobility (100 cm2/(V 3 s)) and Ion/Ioff ratio (105). Figure 6 suggests the effective regulation of the gate structure on the electrical properties of device such as threshold voltage and leakage current. The author acknowledges further adjustment and optimization would be needed for the simulation.
With this kind of double-in-plane gate EDL structure, the functions of OR gate, AND gate, and NAND gate could be achieved. As both Gate1 and Gate2 could control the channel current between source and drain separately and independently,20 the structure is equivalent to an OR gate. By adjusting the doping concentration carefully, the channel of the structure could be fabricated to turn on when both gate voltages are positive, as shown in Figure 5, which is equivalent to the function of an AND gate. Additionally, the channel of the structure could be fabricated to be on without gates and be turned off when both gates are turned on, by tuning the channel material physics, channel length, and/or the equivalent gate dielectric thickness, as suggested by the above discussion and results for Figures 3, 4, 5 and 6. With this function, the NAND gate operation would be achieved also. 3989
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Nano Letters
Figure 5. The shift of IDS VG1 transfer curves of the double-in-plane gate EDL TFTs with variant VG2 values (0, 0.5, 0.8 V) for IGZO channel materials, VTH could be tuned from 0.7 V (1.0 V), the shift of which is over 50% (54.28%). This shows the application of this double-in-plane gate structure could be extended to nanodevices with different semiconductor channel materials.
Figure 6. The shift of IDS VG1 transfer curves of the nanowire EDL TFTs with variant VG2 values ( 0.5 to 0.5 V) with the double-in-plane gate structure, using the key parameters comparable to the published ones in ref 19.
In this Letter, a double-in-plane gate EDL structure for TFTs and nanoFETs, with the double-in-plane gates and source/drain made in a single mask, is proposed. On one hand, this simply designed structure results in a flexible adjustment of device electrical characteristics. On the basis of the data of simulation, electrical characteristics such as threshold voltage could be adjusted in a certain range in the case of the simply made double-in-plane gate device. Therefore, the structure could enable a flexible and convenient control of the device for a stable performance. On the other hand, the structure allows device fabrication more simple and effective than the conventional double-gate technology. These two features of the new structure will introduce TFT and nanoFETs technology to the area of nanoelectronics and more application. In this work, devices based on depletion mode and enhanced mode are considered and discussed. If experimental observation proves the results of our theoretical simulations, a new family of switching devices for simpler logic circuits with TFTs and nanoFETs could be developed.
’ AUTHOR INFORMATION Corresponding Author
*E-mail: (M.D.)
[email protected].
’ REFERENCES (1) Nomura, K.; Ohta, H.; Takagi, A.; Kamiya, T.; Hirano, M.; Hosono, H. Nature (London) 2004, 432, 488.
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(2) Yabuta, H.; Sano, M.; Abe, K.; Aiba, T.; Nomura, K.; Kamiya, T.; Hosono, H. Appl. Phys. Lett. 2006, 89, 112. (3) Tian, B. Z.; Zheng, X. L.; Kempa, T. J.; Fang, Y.; Yu, N. F.; Yu, G. H.; Huang, J. L.; Lieber, C. M. Nature 2007, 449, 885. (4) Tsakalakos, L.; Balch, J.; Fronheiser, J.; Korevaar, B. A.; Sulima, O.; Rand, J. Appl. Phys. Lett. 2007, 91, 233117. (5) Kempa, T. J.; Tian, B. Z.; Kim, D. R.; Hu, J. S.; Zheng, X. L.; Lieber, C. M. Nano Lett. 2008, 8, 3456. (6) Tian, B. Z.; Kempa, T. J.; Lieber, C. M. Chem. Soc. Rev. 2009, 38, 16. (7) Son, K.-S.; Jung, J.-S.; Lee, K.-H.; Kim, T.-S.; Park, J.-S.; Park, K. C.; Kwon, J.-Y.; Koo, B.; Lee, S.-Y. IEEE Electron Device Lett. 2010, 31, 812. (8) Han, J.-W.; Ryu, S.-W.; Kim, D.-H.; Kim, C.-J.; Kim, S.; Moon, D.-I.; Choi, S.-J.; Choi, Y.-K. IEEE Electron Device Lett. 2009, 30, 742. (9) Ito, M.; Miazakia, C.; Ishizakia, M.; Kona, M.; Ikedaa, N.; Okuboa, T.; Matsubaraa, R.; Hataa, K.; Ugajina, Y.; Sekinea, N. J. NonCryst. Solids 2008, 354, 2777. (10) Park, J.; Kim, C.; Kim, S.; Song, I.; Kim, S.; Kang, D.; Lim, H.; Yin, H.; Jung, R.; Lee, E.; Lee, J.; Kwon, K.-W.; Park, Y. IEEE Electron Device Lett. 2008, 29, 879. (11) Lu, A.; Sun, J.; Jiang, J.; Wan, Q. Appl. Phys. Lett. 2009, 95, 222905. (12) Lu, A. X.; Sun, J.; Jiang, J.; Wan, Q. IEEE Electron Device Lett. 2010, 31, 1137. (13) Hsieh, H.-H.; Kamiya, T.; Nomura, K.; Hosono, H.; Wu, S.-C. Appl. Phys. Lett. 2008, 92, 133503. (14) Fung, T.-C.; Chuang, C.-S.; Chen, C.; Abe, K.; Cottle, R.; Townsend, M.; Kumomi, H.; Kanicki, J. J. Appl. Phys. 2009, 106, 084511. (15) Dai, M.; Wu, G.; Yang, Y.; Jiang, J.; Li, L.; Wan, Q. Appl. Phys. Lett. 2011, 98, 093506. (16) Dai, M.; Wu, G.; Yang, Y.; Huang, J.; Li, L.; Gong, J.; Wan, Q. Appl. Phys. Lett. 2011, 98, 153501. (17) The double-in-plane gate structure was simulated by TCAD as follows: Meshes were defined and a conductive metal layer was deposited on a glass substrate. Silicon dioxide was deposited on the conductive layer to 1 nm thick. An n-type channel semiconductor material was grown to 15 50 nm thick, with doping concentration in the range from 1016 to 1019 cm 3. The double-in-plane gates and source and drain contacts are then deposited. Lastly, the electrodes for double-in-plane gates and source/drain were defined. (18) After the spatial structure of the device is formed, the physical properties of materials could be specified based on the experimental results. Specifically, the parameters for the semiconductor channel materials were defined, including mobility (10 30 cm2/V 3 s), effective density states of holes and electrons (1020 cm 3 3 eV 1), band gap Eg at room temperature (3.65 eV for ITO and 3.05 eV for IGZO), and the Shockley Read Hall recombination time for holes and electrons (10 8 s). Physics models were defined afterward, involving Shockley Read Hall recombination, band-to-band tunneling model according to Klaassen, and the device degradation model based by hot carrier injection; defects were also defined by using the density of states model, more detailed information of which could be found in refs 15 and 16. The full Newton method was then used for the analysis of electrical properties. The bias conditions such as the drain voltage and the doublein-plane gate voltages were defined. The solved electrical simulated results were then saved in the output files. (19) Liu, H.; Sun, J.; Jiang, J.; Tang, Q.; Wan, Q. IEEE Electron Device Lett. 2011, 32, 315. (20) Majkusiak, B.; Janik, T.; Walczak, J. IEEE Electron Device Lett. 1998, 45, 1127.
’ NOTE ADDED AFTER ASAP PUBLICATION This article was published ASAP on August 22, 2011. A corresponding author has been added (Qing Wan). The corrected version was posted on September 14, 2011.
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