Multi-Valued Logic Circuits Based on Organic Anti-ambipolar Transistors

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Letter Cite This: Nano Lett. XXXX, XXX, XXX−XXX

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Multi-Valued Logic Circuits Based on Organic Anti-ambipolar Transistors Kazuyoshi Kobashi,†,‡ Ryoma Hayakawa,† Toyohiro Chikyow,† and Yutaka Wakayama*,†,‡ †

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International Center for Materials Nanoarchitectonics (WPI-MANA), National Institute for Materials Science (NIMS) 1-1 Namiki, Tsukuba 305-0044, Japan ‡ Department of Chemistry and Biochemistry, Faculty of Engineering, Kyushu University 1-1 Namiki, Tsukuba 305-0044, Japan ABSTRACT: Multivalued logic circuits, which can handle more information than conventional binary logic circuits, have attracted much attention as a promising way to improve the data-processing capabilities of integrated circuits. In this study, we developed a ternary inverter based on organic field-effect transistors (OFET) as a potential component of high-performance and flexible integrated circuits. Key elements are anti-ambipolar and n-type OFETs connected in series. First, we demonstrate an organic ternary inverter that exhibits three distinct logic states. Second, the operating voltage was greatly reduced by taking advantage of an Al2O3 gate dielectric. Finally, the operating voltage was finely tuned by the designing of the device geometry. These results are achievable owing to the flexible controllability of the device configuration, suggesting that the organic ternary inverter plays an important role with regard to high-performance organic integrated circuits. KEYWORDS: Organic field-effect transistor, multivalued logic circuit, anti-ambipolar transistor, ternary inverter atomically thin layers and are, therefore, mechanically flexible. However, the TMDC-based devices reported so far have a fatal demerit in that they are fabricated by mechanical exfoliation methods with adhesive tape. This method is not suited for large-scale manufacturing because of its low yield and poor scalability. Systematic control of device geometry is impossible and, furthermore, device property modification is hampered due to a strong Fermi-level pinning effect.20,21 In a previous study, we developed an organic AAT based on a heterojunction consisting of α-sexithiophene (α-6T) and N,N′-dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C8) as an alternative candidate for flexible MVL circuits.22 Our device is fabricated by vacuum deposition processes, which make device patterning simple by using shadow masks. Device geometries, including channel length and thickness, are systematically controllable. Interface engineering makes it possible to enhance carrier injection and to reduce the operating voltage.23,24 These features are advantageous for improving individual device performance as well as for designing logic circuits. In this paper, we first discuss the operating mechanism of a ternary inverter consisting of an organic AAT and an n-type OFET. Next, we investigate the effective use of a high-k dielectric layer to reduce the operating voltage. Finally, we demonstrate the fine manipulation of the ternary inverter

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he Internet of things (IoT), which is a network of physical objects interacting with each other via the Internet, is emerging as the next industrial revolution.1,2 Wearable and flexible integrated circuits (ICs) based on organic field-effect transistors (OFETs) have been considered as potential components for building future IoT devices because of their mechanical flexibility, light weight, and low-cost fabrication.3−5 Applications of these OFET-based devices have been limited so far to simple functions, e.g., sensors, actuators, and RFID tags. This is mainly attributed to the difficulties involved in downsizing individual OFETs and their high-density integration.6,7 However, further improvement in the data processing capabilities of organic ICs is indispensable.8−10 Therefore, it is crucial to develop a new device architecture in which mechanical flexibility and data processing capability are simultaneously attained. The main purpose of this study is to tackle this issue by developing a multivalued logic (MVL) circuit based on organic field-effect transistors. Recently, MVL circuits such as ternary inverters have been developed.11−14 MVL circuits allow us to process more data by increasing the number of logic states rather than the integration density. Therefore, MVL circuits offer a promising solution for enhancing the performance of flexible ICs without downsizing each element. Typical devices for building MVL circuits are tunnelling diodes 11,15,16 and anti-ambipolar transistors (AAT)12−14,17−19 because these exhibit a negative differential resistance (NDR). These devices have been intensively studied based on two-dimensional transition metal dichalcogenides (TMDCs), such as MoS2 and WSe2. TMDCs consist of © XXXX American Chemical Society

Received: April 5, 2018 Revised: May 13, 2018

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DOI: 10.1021/acs.nanolett.8b01357 Nano Lett. XXXX, XXX, XXX−XXX

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Figure 1. (a) Schematic illustration of an organic ternary inverter consisting of n-type (red dotted line) and anti-ambipolar (blue dotted line) transistors (AAT). Sexithiophene (α-6T) and perylene derivative (PTCDI-C8) were employed as p-type and n-type semiconductors, respectively. (b) Equivalent circuit diagram of the organic ternary inverter. (c) Transfer characteristics of the organic AAT (blue line) and PTCDI-C8 transistor (red line) measured at |VD| = 60 V. (d) VOUT−VIN characteristic of the organic ternary inverter exhibiting distinct three states: “0”, “1/2”, and “1”.

characteristics. Here, we give importance to the designability of the geometry of our organic AAT, in which the operating voltage is precisely controlled by changing the channel lengths. Figure 1a shows a schematic illustration of our organic ternary inverter comprising an organic AAT and an n-type PTCDI-C8 transistor. Highly doped Si wafers with a thermally grown SiO2 layer (200 nm) were used as substrates. These work as a bottom gate electrode and a gate dielectric, respectively. The SiO2 surface was coated with a 10 nm thick poly(methyl methacrylate) (PMMA) film to terminate defects on the SiO2 surface and to facilitate carrier transport.25,26 On this surface, organic semiconductor layers of α-6T and PTCDIC8 were thermally evaporated in a vacuum with a background pressure of 1 × 10−7 Pa through respective shadow masks as ptype and n-type channels. Both layers were deposited at a fixed deposition rate of 1.0 ML/h at a substrate temperature of 60 °C. These layers were partially overlapped to form a pn heterojunction, which plays a central role in an AAT. The α-6T and PTCDI-C8 were 3 and 12 MLs thick, respectively. Subsequently, Au thin films as source and drain electrodes were deposited onto these layers by thermal evaporation through another shadow mask. The organic AAT and PTCDIC8 transistor were connected in series as illustrated in the equivalent circuit diagram in Figure 1b. The input voltage (VIN) was applied to the common bottom gate. The supply voltage (VDD) was applied to the source electrode of the organic AAT, and another source electrode of the PTCDI-C8 transistor was connected to the ground. The output voltage (VOUT) was monitored by the middle electrode, which works as a common drain electrode for both the AAT and the PTCDI-C8 transistor. All measurements were performed in an ambient condition at room temperature. Conventional FET characteristics of pristine α-6T and PTCDI-C8 channels had been reported in our previous work for comparison.23

The blue and red lines in Figure 1c represent the transfer characteristics of the organic AAT and PTCDI-C8 transistor, respectively. The PTCDI-C8 transistor exhibited a typical ntype property. Meanwhile, the drain current of the AAT reached its peak value at a VG of −42 V (Vpeak), and a further increase in VG induced a large reduction in the drain current. The observed steep increase and decrease in the drain current can be explained in term of a shoot-through current. That is, the drain current is induced only when both channels are in the on state. Details about mechanism was discussed in our previous work.22 This behavior is analogous to that of NDR. These contrastive characteristics of the two transistors enable a multivalued operation. The VOUT of the inverter is determined by the resistance ratio of the organic AAT and PTCDI-C8 transistor and these can be modulated by VIN. In terms of the resistance ratio, the transfer characteristics can be divided into three ranges: range I (VIN < 7 V), range II (7 V < VIN < 18 V) and range III (18 V < VIN). In range I (VIN < 7 V), the drain current of the organic AAT was higher than that of the PTCDIC8 transistor. Both transistors showed comparable amounts of drain current in range II (7 V < VIN < 18 V). A further increase in VIN reversed the drain currents; the PTCDI-C8 transistor exhibited a higher drain current than the organic AAT in range III (18 V < VIN). That is, a drastic decrease in the drain current above Vpeak through the AAT channel is essential to producing distinct three resistance ratios. As a result of these VIN-induced variations in drain current, we observed three distinct logic states, as shown in Figure 1d. Here, the corresponding VOUT−VIN characteristic of the organic ternary inverter was measured at a constant VDD of 60 V. In range I (VIN < 7 V), a conducting path was formed between VDD and the output terminal that yielded a high voltage value close to VDD (logic state “1”). In range II (7 V < VIN < 18 V), VDD was divided between the two transistors, resulting in an B

DOI: 10.1021/acs.nanolett.8b01357 Nano Lett. XXXX, XXX, XXX−XXX

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Figure 2. (a) Schematic illustration of the organic ternary inverter with a 30 nm thick Al2O3 layer. (b) Transfer characteristics of the organic AAT (blue line) and PTCDI-C8 transistor (red line) with the Al2O3 layer measured at |VD| = 10 V. (c) VOUT−VIN characteristic of the organic ternary inverter with the Al2O3 layer at VDD = 10 V.

Figure 3. (a) Optical microscope image of the organic ternary inverter. Plural electrodes are connected to the channels. (b) Schematic illustration showing the variations in the α-6T channel length. (c) Transfer characteristics of the organic AAT to show the channel length dependence of the operating voltage. The Vpeak values were shifted with increasing channel lengths. (d) VOUT−VIN characteristics of the organic ternary inverters. The transition points were precisely controlled by changing the α-6T channel lengths, as emphasized by arrows in the inset.

intermediate voltage value (logic state “1/2”). In range III (18 V < VIN), a conducting path was formed between the output terminal and ground, which led to logic state “0”. VOUT in the respective states, which are VOUT(I), VOUT(II), and VOUT(III), showed clear margins to yield distinct ratios: ca. 3.5 of VOUT(I)/VOUT(II) and 51.0 of VOUT(II)/VOUT(III). In this manner, we successfully realized the first ternary inverter based

on an organic anti-ambipolar transistor. This inverter operation is known as “NOT” gate operation in Kleene’s algorism. The medium state “1/2” shows the value neither “0” nor “1”. The introduction of the ternary values therefore enables us to design more-complex logic circuits with less numbers of transistors compared with that of the binary inverters.27 C

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to 2.4 V. This is because the threshold voltage of the α-6T channel increased with increasing channel lengths. These variations in Vpeak were effectively reflected in the VOUT−VIN characteristics as shown in Figure 3d. The inset emphasizes the transition points of the logic states from “1/2” to “0”, which were lowered from 2.8 to 2.4 V, as indicated by arrows. This precise control of the operating voltage, which is not achieved in other studies,11−19 enables the further reduction of VIN. This is advantageous in terms of power consumption. In conclusion, we developed a ternary inverter consisting of organic anti-ambipolar and n-type transistors. The organic ternary inverter exhibits three distinct logic states. The operating voltage of the organic ternary inverter was reduced below 10 V by taking advantage of the high-k Al2O3 gate dielectric. Furthermore, the patterning capability of the device configuration was utilized as an effective way of fine-tuning the driving voltage. Importantly, all measurements carried out in ambient conditions at room temperature ensured the stability and reproducibility of the device operations. These facts suggest that our organic ternary inverter has great potential as a key element of future flexible IoT devices.

Recently, similar device operations have been reported in which pn heterojunctions formed by TMDCs play key roles. For example, Nourbakhsh et al., developed a ternary inverter with a MoS2/WSe2 heterojunction.14 Li et al. investigated a three-channel device based on an anti-ambipolar transistor with a SnS2/WSe2 heterojunction.12 These devices and ours have some common features. The channel materials are mechanically flexible. A pn heterojunction can be formed with weak interactions, such as a van der Waals interaction, which do not suffer from lattice mismatch. The most important common feature is that the drain current flows with only a limited range of gate bias voltage,12 which is analogous to NDR.14 In particular, Li et al., claimed that a multivalued operation allowed 3N digital signals to be processed by Ns device units, which is superior to conventional 2N data processing with traditional CMOS devices. Although these devices have a weak point in regards power dissipation because both p and n channels should be in the on state to produce logic state “1/2″, pn-heterojunction-based transistors have potential as an element of high-performance flexible multivalued logic circuits. Meanwhile, a challenge still remains as regards our organic ternary inverter namely its large operating voltage. A VDD of 60 V is unrealistic for practical applications. To solve this problem, we employed a 30 nm thick Al2O3 (k ≈ 9)28 layer instead of a 200 nm thick SiO2 (k = 3.9) layer. It is well-known that a gate insulator with a high dielectric constant (high-k) can induce a high charge-carrier density at the semiconductor−dielectric interface to reduce the operating voltage of OFETs.29−31 Figure 2a shows an illustration of the inverter in which an Al2O3 dielectric layer was deposited directly on a Si substrate by an atomic layer deposition technique. The growth process of the Al2O3 layer is detailed in our previous work.23 Figure 2b shows the transfer characteristics of the organic AAT (blue) and PTCDI-C8 (red) transistors with the Al2O3 layer. The operating voltages were effectively reduced. As a result, three logic states, namely “1” in range I (VIN < 1.5 V), “1/2” in range II (1.5 V < VIN < 2.8 V) and “0” in range III (2.8 V < VIN), were clearly observed at a low VDD of 10 V as shown in Figure 2c. Importantly, the ratios of VOUT between the respective VIN ranges (VOUT(I)/VOUT(II) and VOUT(II)/VOUT(III)) were confirmed to be reproducible to those observed in Figure 1d. This is because these ratios are determined by the ratios of respective channel resistances regardless of the dielectric constants of the gate insulators. As mentioned above, a strength of our organic AAT is that device patterning is available for the systematic design of geometries. In turn, the geometry patternability allows the precise control of the device properties, e.g., the bias voltage at the peak current (Vpeak) of the organic AAT is controllable by changing the channel lengths.24 Employing this advantage, we demonstrate the fine-tuning of the transition point by adjusting the channel lengths. Figure 3a shows an optical microscope image of a ternary inverter, in which plural electrodes were deposited through a shadow mask. Among these electrodes, a pair of electrodes was fixed to the PTCDI-C8 channel; one was used to monitor VOUT as a common drain electrode and the other was used to connect to the ground. The position of another source electrode connected to the α-6T channel was varied to change the channel lengths from 300 to 550 μm as shown in Figure 3a,b. These AATs were labeled AAT-1, AAT-2, and AAT-3, respectively. The transfer characteristics of these AATs are shown in Figure 3c. Here, the red line was taken from Figure 2b. As seen here, the Vpeak values clearly shifted from 2.8

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AUTHOR INFORMATION

Corresponding Author

*E-mail: [email protected]. ORCID

Yutaka Wakayama: 0000-0002-0801-8884 Notes

The authors declare no competing financial interest.

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ACKNOWLEDGMENTS This research was supported by the World Premier International Center (WPI) for Materials Nanoarchitectonics (MANA) of the National Institute for Materials Science (NIMS), Tsukuba, Japan, and JSPS KAKENHI Grant Numbers JP15K13819 and JP23686051.

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DOI: 10.1021/acs.nanolett.8b01357 Nano Lett. XXXX, XXX, XXX−XXX