Subscriber access provided by UNIVERSITY OF ADELAIDE LIBRARIES
Communication
Multiple physical timescales and dead time rule in few-nm sized graphene-SiO-graphene memristors x
Laszlo Posa, MARIA EL ABBASSI, Peter Makk, Botond Santa, Cornelia Nef, Miklos Csontos, Michel Calame, and Andras Halbritter Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.7b03000 • Publication Date (Web): 06 Oct 2017 Downloaded from http://pubs.acs.org on October 8, 2017
Just Accepted “Just Accepted” manuscripts have been peer-reviewed and accepted for publication. They are posted online prior to technical editing, formatting for publication and author proofing. The American Chemical Society provides “Just Accepted” as a free service to the research community to expedite the dissemination of scientific material as soon as possible after acceptance. “Just Accepted” manuscripts appear in full in PDF format accompanied by an HTML abstract. “Just Accepted” manuscripts have been fully peer reviewed, but should not be considered the official version of record. They are accessible to all readers and citable by the Digital Object Identifier (DOI®). “Just Accepted” is an optional service offered to authors. Therefore, the “Just Accepted” Web site may not include all articles that will be published in the journal. After a manuscript is technically edited and formatted, it will be removed from the “Just Accepted” Web site and published as an ASAP article. Note that technical editing may introduce minor changes to the manuscript text and/or graphics which could affect content, and all legal disclaimers and ethical guidelines that apply to the journal pertain. ACS cannot be held responsible for errors or consequences arising from the use of information contained in these “Just Accepted” manuscripts.
Nano Letters is published by the American Chemical Society. 1155 Sixteenth Street N.W., Washington, DC 20036 Published by American Chemical Society. Copyright © American Chemical Society. However, no copyright claim is made to original U.S. Government works, or works produced by employees of any Commonwealth realm Crown government in the course of their duties.
Page 1 of 22
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Nano Letters
Multiple physical timescales and dead time rule in few-nm sized graphene-SiO x -graphene memristors László Pósa,
†, ‡
Maria El Abbassi,
Miklós Csontos,
∗,†
¶
Péter Makk,
Michel Calame,
¶ , §, k
¶
Botond Sánta,
†
Cornelia Nef,
and András Halbritter
¶
†
†Department of Physics, Budapest University of Technology and Economics and MTA-BME Condensed Matter Research Group, 1111 Budapest, Budafoki ut 8, Hungary
‡Research Institute for Technical Physics and Materials Science, 1121 Budapest, Konkoly-Thege M. ut 29-33, Hungary
¶Department of Physics, University of Basel, Klingelbergstrasse 82, CH-4056 Basel, Switzerland
§Swiss Nanoscience Institute, University of Basel, CH-4056 Basel, Switzerland. kEmpa, Swiss Federal Laboratories for Materials Science and Technology, Transport at Nanoscale Interfaces Laboratory, CH-8600 Dübendorf, Switzerland. E-mail:
[email protected] Abstract The resistive switching behavior in SiOx -based phase change memory devices con ned by few nanometer wide graphene nanogaps is investigated. Our experiments and analysis reveal that the switching dynamics is not only determined by the commonly observed bias voltage dependent set and reset times. We demonstrate that an internal timescale, the dead time, plays a fundamental role in the system's response to various 1
ACS Paragon Plus Environment
Nano Letters
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
driving signals. We associate the switching behavior with the formation of microscopically distinct SiOx amorphous and crystalline phases between the graphene electrodes. The reset transition is attributed to an amorphization process due to a voltage driven selfheating; it can be triggered at any time by appropriate voltage levels. In contrast, the formation of the crystalline ON state is conditional and only occurs after the completion of a thermally-assisted structural rearrangement of the as-quenched OFF state which takes place within the dead time after a reset operation. Our results demonstrate the technological relevance of the dead time rule which enables a zero bias access of both the low and high resistance states of a phase change memory device by unipolar voltage pulses.
Keywords Memristor, resistive switching, silicon oxide, graphene nanogaps, phase change memory, multiple timescales While current CMOS technology is reaching the sub-10 nm regime, a broad consensus arises that a further boosting in computational power will primarily rely on novel circuit elements exhibiting an increased functional complexity as well as on beyond-von Neumann architectures bene ting from an improved interconnectivity of their building blocks. 1 Two-terminal resistance change memory devices (ReRAMs) 25 are outstanding candidates as they are not only scalable below 10 nm due to the lamentary nature of their resistive switchings but they also oer multi-bit operations via the analog tunability of their resistance states. The large scale integration of such devices on semiconductor industry compatible material platforms is demonstrated in the form of stacked crossbar arrays which are operated at reasonable current and voltage levels and a reduced thermal budget. 69 Nonvolatile data storage is enabled by the widely observed exponential dependence of the set and reset times on the bias voltage which provides the means of fast programming at higher
2
ACS Paragon Plus Environment
Page 2 of 22
Page 3 of 22
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Nano Letters
voltage and non-invasive readout at lower signal levels. 10,11 This highly nonlinear behavior together with the possibility of multilevel programming provide the basis for a diverging number of applications ranging from long-term, non-volatile data storage to neural network modeling involving programmable learning and forgetting abilities among other synaptic functionalities. 1,12,13 The two-terminal nature of ReRAM devices also oer the possibility of a major simpli cation with respect to conventional CMOS architectures relying on three-terminal, unipolarly driven units. However, the operation of various memristive devices utilizing bidirectional ion transport requires bipolar voltage signals. Alternatively, ReRAM cells exhibiting unipolar current-voltage [I(V)] characteristics eliminate the need for such bipolar driving but this approach sacri ces the possibility of the zero bias read-out of the low and high resistance states. 14 Here we report on the experimental observation of a complex memristive behavior in thermally grown SiO x thin lms where the active region of the resistive switching is con ned under the 2 nm wide gap realized by controlled electrobreakdown of a narrow graphene constriction. We found that the switching dynamics is not only governed by the above mentioned, voltage dependent set/reset times but an additional independent timescale, the so-called dead time also appears playing a crucial role in the device operation: after switching the device OFF, the ON state cannot be restored as long as the dead time has not passed. This eect gives rise to the opportunity of reproducible transitions between unipolar and bipolar switching characteristics within the same nanodevice and thus programming its either state at zero bias by unipolar voltage signals. In this Letter we analyze the complex switching behavior arising from the coexistence of the strongly voltage dependent set and reset times and the dead time rule. The resistive switching capability of SiO x was discovered in the 1960's in silicon rich metal-insulator-metal structures. 1517 In the recent years various types of SiO x based resistive switches were demonstrated based on either extrinsic 1820 or intrinsic 21,22 mechanisms. In
3
ACS Paragon Plus Environment
Nano Letters
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
the former case the SiO x merely acts as a passive matrix for metallic lament formation fueled by the electrodes while in the latter it plays an active role by forming conductive, silicon rich pathways upon biasing. The complete switching cycle is explained in terms of crystallization and amorphization of the Si along the conductive lament. The presence of Si nanocrystals (NCs) embedded in the SiO x matrix within the active device volume was indeed con rmed by in-situ transmission electron microscopy studies. 2325 Additionally, the accumulation of defect sites were also identi ed to contribute to lamentary resistive switching. 2630 Vertically stacked devices with SiO x thicknesses above 10 nm show nonvolatile behavior, good endurance ( >104 cycles), high OFF/ON resistance ratios ( >105 ) and short set/reset times (
