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J. Phys. Chem. C 2008, 112, 1276-1281
Multiple ZnO Nanowires Field-Effect Transistors Duk-Il Suh, Seung-Yong Lee, Jung-Hwan Hyung, Tae-Hong Kim, and Sang-Kwon Lee* Department of Semiconductor Science and Technology, Semiconductor Physics Research Center, Chonbuk National UniVersity, Jeonju 561-756, Korea ReceiVed: October 3, 2007; In Final Form: NoVember 3, 2007
We report on the multiple ZnO nanowires field-effect transistors (FETs), which were formed by assembling as-synthesized ZnO nanowires on a SiO2/Si substrate using an optimized alternating current (AC) dielectrophoresis (DEP) technique in three-probe back-gate geometry. The AC DEP was optimized with a bias voltage of 10 Vp-p at a frequency of 10 kHz. Our multiple ZnO nanowires FETs containing ca. 50∼65 nanowires in one device exhibited excellent electrical characteristics with a transconductance of 3∼11.5 µS at a drain voltage of 1∼5 V, a mobility of ∼30 cm2/V‚s, and a carrier concentration of 9.4 × 1017 cm-3. For a comparison study, we also present conventional single ZnO nanowire FETs prepared by e-beam lithography with a back-gate structure.
1. Introduction Zinc oxide (ZnO) has a wide energy band gap of ∼3.3 eV at 298 K with a wurtzite crystal structure. These ZnO nanomaterials (nanorods and nanowires) have received extensive interest for use in room-temperature ultraviolet (UV) lasing cavities,1 photodetectors,2,3 gas/chemical sensors,4,5 electronic devices,6-9 and dye-sensitized solar cells.10-12 ZnO semiconductors have intrinsically an n-type carrier owing primarily to the presence of oxygen vacancies and/or zinc interstitials. Approaches that are fully scalable in terms of device density and the area of coverage are highly important for wafer-based large-scale integration. Jin et al. reported a layer-by-layer assembly technique using a conventional Langmuir-Blodgett (LB) method.13 They arranged Si nanowires with controlled alignment and photolithography to define their interconnects. Subsequently, they found a high-performance Si nanowires field-effect transistor (FET).13 Despite of their successful fabrications of highperformance Si nanowires FETs, more advanced assembly techniques are still required for scalable device applications because the LB method has weak points. Such weak points are that the nanomaterials should be hydrophobic and the fabrication requires many steps. However, the dielectrophoresis (DEP) process now has become one of the most promising methods to assemble and/or align one-dimensional nanostructures.3,14,15 There have been a few studies on DEP techniques with a combination of assembled ZnO nanowires FETs. Another requirement to meet for these nanowire-based FETs to be useful in practical device circuits is that the nanowire FETs must afford sufficiently high on-currents to drive an electronic circuit, meaning that the nanowire FETs should drive at least an oncurrent of >1mA. Previous reports showed that most of the nanowire-based FETs had quite low on-currents (
