Nanostructured High-Performance Thin-Film Transistors and

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Nanostructured High-Performance Thin-Film Transistors and Phototransistors Fabricated by a High-Yield and Versatile Near-Field Nanolithography Strategy Kairong Huang, Jin Wu, Zihao Chen, Huihua Xu, Zixuan Wu, Kai Tao, Tengzhou Yang, Qian Wu, Hang Zhou, Bolong Huang, Huanjun Chen, Jun Chen, and Chuan Liu ACS Nano, Just Accepted Manuscript • DOI: 10.1021/acsnano.9b00665 • Publication Date (Web): 13 May 2019 Downloaded from http://pubs.acs.org on May 13, 2019

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Nanostructured High-Performance Thin-Film Transistors and Phototransistors Fabricated by a High-Yield and Versatile Near-Field Nanolithography Strategy Kairong Huang1#, Jin Wu1#*, Zihao Chen1, Huihua Xu1, Zixuan Wu1, Kai Tao3, Tengzhou Yang1, Qian Wu1, Hang Zhou4, Bolong Huang5, Huanjun Chen1, Jun Chen1, Chuan Liu1, 2* 1State

Key Laboratory of Optoelectronic Materials and Technologies and the Guangdong Province

Key Laboratory of Display Material and Technology, School of Electronics and Information Technology, Sun Yat-sen University, Guangzhou 510275, China 2State

Key Lab of Silicon Materials, Zhejiang University, Hangzhou 310027, People’s Republic of China

3The

Ministry of Education Key Laboratory of Micro and Nano Systems for Aerospace, Northwestern Polytechnical University, Xi'an, 710072, China

4Shenzhen

Key Lab of Thin Film Transistor and Advanced Display, Peking University Shenzhen Graduate School, Peking University, Shenzhen, 518055, P. R. China

5Department

of Applied Biology and Chemical Technology, the Hong Kong Polytechnic

University, Hung Hom, Kowloon, Hong Kong SAR, and The Hong Kong Polytechnic University Shenzhen Research Institute, Shenzhen, China Corresponding Authors: E-mail: [email protected], [email protected] # These

authors contribute to this work equally.

ABSTRACT Thin-film transistors (TFTs) and field-effect transistors (FETs) are basic units to build functional electronic circuits and investigate transport physics. In conventional TFTs or FETs, performance in terms of current level, on–off ratio, and the sensitivity of detection is limited by homogeneous 1 ACS Paragon Plus Environment

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semiconducting layers. In this paper, we develop TFTs with sub-micron heterostructures by using a strategy

based

on

near-field

photolithography.

We

use

an

array

of

total-reflective

polydimethylsiloxane (PDMS) pyramids or trenches as a soft photomask in photolithography to induce multiple reflections and diffractions to focus the light. The textured feature enables the generation of gaps, dots, and grids at the nanoscale, with dimensions as small as sub-100 nm on substrates at the centimeter scale. We demonstrated the very-high-performance oxide TFTs on nanoscale and periodic degenerately doped heterojunctions, and they yielded a nearly 20-fold increase in transconductance and apparent device mobility. The on–off ratio was higher than 109, with notably enhanced output current and clear scaling effect with channel length. We also built nanostructured wide-gap/narrow-gap heterojunctions to balance the high on–off ratio and sensitive photoresponse in a unidirectional phototransistor. This study shows the viability of programming a variety of nanoscale sub-micron patterns or interfaces in TFTs and FETs to significantly enlarge the scope of research on multi-functional TFTs and FETs.

KEYWORDS:

nanostructures,

thin-film

transistor,

patterning,

oxide

semiconductors,

phototransistor

Thin-film transistors (TFTs) or field-effect transistors (FETs) have been widely used as standard devices to explore logics and sensing circuits as well as the transport physics of materials. Conventional TFTs or FETs use continuous, homogeneous, and uniform semiconductors as active layers to implement carrier accumulation and transport. Recently, microstructures have been introduced to TFTs or FETs to offer better electrical properties and mechanical flexibility, such as wavy structures,1 nanogrooves,2 nanowires,3 and split structures.4, 5 Some improvements are the sideeffect4,

5

of manufacturing (e.g., modifying ionic bonding during manufacturing). Despite the

advancements in TFTs or FETs with micron-scale microstructures, a general and versatile method to create sub-micron structures and interfaces to facilitate charge transport or induce interfacial effects is still lacking. Moreover, the theoretical understanding and experimental characterization of such a 2 ACS Paragon Plus Environment

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method are limited. For practical applications, TFTs yielding a large output current and high device mobility (e.g., over 50 cm2V-1s-1) are desirable to drive high-resolution displays or Virtual Reality with organic light-emitting diodes (OLEDs) or micro-LEDs. For fundamental research, considering that nanostructures in LEDs and solar cells can induce optical coupling and enhance quantum efficiency.6-9 Nanostructured TFTs may help explore electronic processes at interfaces. The key to fabricating nanostructured TFTs or FETs is to develop a lithographic strategy that can provide nanoscale features over large surface areas.4, 10-14 A wealth of maskless nanolithographic strategies have been developed, such as electron-beam lithography (EBL),15 scanning-probe-based lithography,16, 17 nanoimprint lithography,18, 19 block copolymer lithography,20, 21 and interference lithography.22 Nevertheless, trade-offs are inevitable among cost, throughput, flexible feature size, and geometry,10, 11 and a cost-effective photolithographic strategy to produce sub-micron patterns with flexible feature geometries over a large area remains elusive.10 Recently, the development of polymer pen lithography, beam pen lithography (BPL), and related techniques has enabled nanopatterns over a large range of the nanoscale.10, 13, 23-27 However, it is challenging to apply BPL to the fabrication of TFTs or FETs because this requires an opaque metal for the coating and subsequent creation of sub-wavelength nanoscopic apertures at the apexes of metal-coated elastomeric pyramids,10,

13

and the repeated friction between metal-coated tips and substrates

gradually wears off the metal coating.10 In this study, we develop a simple but effective near-field photolithographic strategy to produce nanostructures on surfaces covering several square centimeters for nanostructured TFTs. By using an array of pristine total-reflective polydimethylsiloxane (PDMS) pyramids or trenches, light beams are diffracted or reflected by slopes until they focus to expose the underlying photoresist, generating subwavelength geometries as small as below 100 nm in width. With this near-field photolithographic strategy, we successfully constructed nanostructured transistors with degenerate/non-degenerate or wide-gap/narrow-gap heterojunctions for high on–off ratio for TFTs and photosensitive TFTs, respectively. Based on an oxide semiconductor (InGaZnO), the former exhibited output current and 3 ACS Paragon Plus Environment

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transconductance nearly 20 times higher than conventional TFT and, thus, a high on–off ratio (> 109). Compared with high-mobility oxide TFTs reported in the literature, the proposed method is superior in three respects: First, it does not require recovery time,28 and the devices begun functioning immediately after fabrication. Second, the scaling effect is clearly observed for various channel lengths in this study, and guarantees that the relevant devices are suitable for different channel lengths, especially for L smaller than 10 μm. Third, the tested devices achieved better performance and reliability in terms of the ideal TFT behaviors. Using a high-k ZrO2 dielectric layer, low operational voltage (< 5 V) was achieved with negligible hysteresis and stable operation of stress tests. Moreover, the nanostructured phototransistors with wide-gap/narrow-gap heterojunctions were highly sensitive to visible light, maintained a high on–off ratio, and exhibited unidirectional transport. By combining 2D device simulations and experimental characterizations, we show how the nanostructured TFTs operate with heterojunctions, and demonstrate that such techniques and devices offer various possibilities for fundamental research and applications.

RESULTS AND DISCUSSION Sub-wavelength near-field photolithography The proposed near-field photolithographic technique with textured masks is as shown in Figures 1a and 1b. Using a periodic array of micro-pyramids or trenches on PDMS masks, the normalincidence light transmitted onto an underlying photoresist surface can take one of three possible paths: through the sidewall b (path ①), through the space a between the bases of adjacent pyramids (path ②), or through the pyramid’s apex c (path ③). The intensity of incident light passing through slope b (path ①) to expose the underlying photoresist is weak due to total internal reflection at the PDMS– air interface.29, 30 Total internal reflection occurs because the normally incident light travels from the high-refractive-index PDMS (refractive index n = 1.43) to the low-refractive-index air (n = 1.00) and the incident angle (54.7°) exceeds the critical incident angle (44.5°).29, 31-33 In principle, if the space between adjacent pyramids or trenches is less than the wavelength of the incident light, the light 4 ACS Paragon Plus Environment

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diffracts as it travels from region a to the underlying photoresist (path ② ), which significantly attenuates the intensity of light reaching the photoresist. Thus, the effective exposure dose along path ② becomes insufficient to completely expose the underlying photoresist. Therefore, only the incident light following path ③ should efficiently penetrate the PDMS mask. The above processes are quantified by numerical simulations, showing how the textured PDMS mask induces the sub-wavelength-scale focusing. We built a 2D model to calculate the light paths as well as the distribution of light intensity inside and outside the PDMS mask. The light paths in a few picoseconds after incidence are shown in Figure 1c. Normal-incidence ultraviolet (UV) light through the sidewalls is first reflected and then refracted to another pyramid or trench. With multiple refractions and reflections, light is mostly trapped inside the PDMS mask and generates a highintensity area near the tip. Simultaneously, light through the apexes directly penetrates into the substrate and forms high-intensity areas as small as the sizes of the apexes. The resulting distribution of light intensity is shown in Figure 1d, and energy density is squeezed near the interface of the apexes of the PDMS and the substrate. Consequently, only the photoresist below the apexes is completely exposed, thereby producing periodic sub-wavelength nanostructures. The values of energy density at different positions near the interfaces of the substrate are given in the Supporting Information (Figure S1). Compared with the aforementioned BPL, no metal coating is needed here because of the total reflection achieved by the textured PDMS mask. The focusing effect can be achieved by employing micro-pyramids with sharp peaks or micro-trenches with sharp edges in the PDMS masks to generate nanoscale dots or gaps in the photoresist, respectively.

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Figure 1. (a-b) Schematic representations of near-field photolithography with textured mask. The PDMS stamped with arrays of micro-pyramids or micro-trenches affords the total reflection of the incident light and focuses the energy onto the positive photoresist to create sub-wavelength nanostructures. (c) Numerical simulations of the trajectory of incident light with the PDMS photomasks. The wavelength of incident light is 300 nm and light paths for the first few picoseconds are shown. (d) The calculated distributions of light energy density with textured mask under vertical incidence of UV light. For near-field photolithography, we first fabricated Si molds with a zigzag cross-sectional profile using photolithography followed by anisotropic etching using KOH (Figure 2a). We used the anisotropic wet etching of Si (100) to reduce the spacing between the recessed Si trenches to as small as 60 nm (Figure 2b). The apexes at the bottom of the Si trenches were approximately 30 nm. Thus, the array of PDMS micro-trenches or micro-pyramids with 90-nm-wide spacings and 60-nm-wide apexes was replicated from the Si-trench mold (Figure 2c, and Figure S2 in Supporting Information). Centimeter-scale and even wafer-scale Si molds and corresponding PDMS photomasks can be fabricated in this way (the inset of Figures 2b and S3). Centimeter-scale sub-100 nm nanostructures can be produced via near-field photolithography with the corresponding PDMS photomasks on the positive photoresist. As shown in Figure 2d, the vertical sidewalls on the photoresist structure facilitated the high-fidelity transfer of the nanostructures of the photoresist to other materials.34 The stickiness of the pristine PDMS, and the Van der Waals force between the PDMS and the photoresist ensured intimate and conformable contact between the apex of the PDMS 6 ACS Paragon Plus Environment

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pyramid and the photoresist surface, which introduced a near-field optical effect and precluded farfield light diffraction.32, 35, 36 Importantly, the photoresist below the slope of and the spacings between the micro-trenches or micro-pyramids was not exposed, even after prolonged exposure (Figure S4). Prolonged exposure only deepened the recessed positive features of the photoresist below the apexes but did not lead to the exposure of the other regions. To evaluate the repeatability and reusability of the PDMS photomasks, the same mask was used for near-field photolithography 50 times. An average line width of 95 nm with a small tolerance value of 9 nm was obtained as a result (Figure S5). No appreciable trend of increase in the line width of the photoresist was observed, indicating the good reusability and wear-tolerant ability of the PDMS masks. The authors also check their pressure reliability by applying pressure and investigating the outcome of the patterns. The results are shown in Figures 2e-g and S6 (the dry etching process was used here). As the pressure on the PDMS photomasks was tuned in a wide range from 0.25 kPa to 3.75 kPa, and to 10 kPa, the line width of the Si array fabricated by RIE dry etching slightly increased from 298 nm to 432 nm. By further tuning the mechanical properties of the PDMS,37 we expect higher pressure reliability in processing. Overall, the proposed technique exhibits good repeatability and reusability, acceptable pressure reliability, and is compatible with both wet and dry etching processes.


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Figure 2. (a) Steps for producing an array of totally reflective PDMS trenches and sub-micron line arrays. Once the zigzag silicon mold has been fabricated by anisotropic wet etching, an array of PDMS trenches is replicated from the silicon mold and used to produce a 95-nm-wide positive photoresist line array via near-field photolithography. (b) SEM image of straight Si mold. The inset figure is a photograph of a 4-inch wafer of a totally reflective PDMS photomask. (c) AFM image of PDMS mask replicated from the silicon mold in (a). (D) SEM image of 95-nm-wide positive photoresist line array. (e) Scheme illustrating pressure from the supporting glass on PDMS mask during exposure. (f) SEM image of dry etched Si lines fabricated using the total reflective PDMS photomask under pressure at 0.25 kPa, 3.75 kPa, and 10 kPa. (g) The relation between Si line width and pressure on the PDMS mask. In addition, the proposed nanolithographic strategy has versatile applications. First, with the negative-tone photoresist, it is possible to create SU-8 nanopatterns over a large area with line widths as small as 120 nm (Figure S7), which is sub-wavelength. This indicates that this low-cost nanolithographic strategy is complementary to previously reported phase-shifting lithography and EBL.15, 32, 34, 38 Second, the horizontal geometries on the zigzag Si molds and PDMS photomasks can be flexibly designed. For instance, dots, grids, and squares can be fabricated by deploying Cr-based hard photomasks with corresponding feature shapes in the first step of far-field photolithography during the fabrication of the Si molds (Figure S8). The PDMS masks reproducing the patterns 8 ACS Paragon Plus Environment

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(Figure S9) can then be used to generate various nanoscale geometries, including dots, grids, and concentric squares on the photoresist or metal films (Figure S8 and S10). Limited by the resolution in the fabrication of textured PDMS mask, areas of periodic nanoscale under the apexes of the mask were exposed with micro-scale spacing with one-time exposure. By multiple overlay exposure, the proposed near-field photolithographic method can fabricate both nanostructured patterns and nanospacings between patterns, as shown in Figure S11. Although introducing an extra mask to the lithography may increase the complexity of fabrications to some extent, the versatility of the proposed strategy offers possibilities for research on electronic devices, and the authors focus on converting the semiconducting layer into nanostructures for TFTs in the following.

TFTs with degenerately doped heterojunction In conventional TFTs, homogeneous semiconducting layers act as the channel area, where the carrier concentration is tuned by the vertical gate field and drift velocity by the lateral drain field. To enhance the gate-tunability of TFTs, output current, and on–off ratio, we introduce the nanoscale and periodic degenerately doped heterojunctions using the above nanolithographic technique. InSnO (ITO) and InGaZnO (IGZO) are used as materials for the degenerate and the non-degenerated states in the channel, respectively. As shown in Figure 3a, these heterojunction TFTs are typical bottomgate top-contact structure. The dielectric layer was 100 nm SiO2, or a high-k dielectric layer was fabricated by using the sol-gel process and spin-coating, as explained in the experimental sections. For active layers of the heterojunction, a 50-nm ITO was first deposited by direct-current (DC) sputtering, and the degenerate ITO film was then patterned with sub-micron gaps by photolithography using total reflective PDMS trenches (Figure 3b). The scanning electron microscopy (SEM) image shows that gaps between neighboring ITO strips were 315 nm wide. Note that these sub-micron gaps were parallel to the width of the source/drain electrode so that there was no current flow at this stage. The nanopatterned samples were then deposited on a 70-nm IGZO film through RF sputtering followed by conventional photolithography to define the region of the active layer. The schematics 9 ACS Paragon Plus Environment

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of the fabrication process are shown in Figure S12. The cooperation between near-field photolithography and conventional lithography demonstrates the potential for the application of this transistor structure to any methodology based on conventional lithography, such as self-aligned gate channels.39, 40 As shown in the cross-sectional SEM image, the IGZO film filled in the ITO nanogaps, which generated a vertical heterojunction through ITO to build the path of the current between the source and the drain electrodes. The electrical properties of the heterojunction TFTs are shown Figures 3d-g. In both the linear and the saturated transfer scanning, the device exhibited strong gate tunability and high on–off ratio without observable hysteresis during forward and backward scanning. This indicates that the states of defect and the localized states at the interface of the IGZO/ITO nanostructured heterojunction and the channel/dielectric interface were negligible.41 Devices with the proposed method using nanoscale and periodic heterojunctions achieved drain current ID an order of magnitude higher than and offcurrent identical to the conventional TFTs with uniform IGZO channel layers, as shown in Figures 3d and 3e. In the saturated regime (gate voltage VG = 40 V and drain voltage VD = 40 V), the drain current reached 17.5 mA, 17.5 times higher than that in the conventional IGZO TFT (IDmax = 0.996 mA). In the linear regime (VG = 40 V and VD = 0.1 V), a similarly large enhancement was obtained ∂𝐼D

for ID and transconductance 𝑔m = ∂𝑉G . When using the method of extraction of field-effect device mobility, the linear and saturated device mobilities were 165.8 cm2V-1s-1and 144.2 cm2V-1s-1 (from fitting the slope of ID and 𝐼D against VG, from VG = 25 V to 40 V), respectively, both 17 times higher than those of conventional IGZO TFTs with μlin = 9.8 cm2V-1s-1 and μsat = 8.5 cm2V-1s-1. The detailed relations between transconductance and differential apparent mobility with VG are shown in Figure 3g. Note that these values are not the field-effect mobility of the active layer but the apparent mobility for the device, and can be regarded as the figure of merit for measuring the gate-tunability of conductance and the output current. If assuming ITO to be totally conductive, the field-effect mobility of the IGZO part was 16.6 cm2V-1s-1 (linear) and 14.4 cm2V-1s-1 (saturated). Statistical data concerning devices with varied channel lengths L are shown in Figures 3h-k. The on–off ratios of devices with 10 ACS Paragon Plus Environment

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different values of L were 108 to 109, and followed the relationship 𝐼ON/𝐼OFF ∝ 1/𝐿. As both 𝐼ON and 𝐼OFF should ideally increase with 1/L, such results indicate that the off current could be even lower than the lower limit in our measurements.

Figure 3. Thin film transistors with nanostructured IGZO/ITO heterojunction as channels. (a) Optical images of transistor arrays and a schematic representation of single gate device. (b) Images taken from optical microscope and SEM. (c) Cross-sectional SEM image of the heterojunction channel. The electrical properties of devices on the SiO2 dielectric layer with a nanostructured heterojunction channel (red symbol lines) or normal IGZO TFT (black symbol lines). (d) The transfer curves in the saturated regime for TFT with a nanostructured channel or homogeneous IGZO channel under forward and backward scans (VD = 40V) (e) The transfer curves in the linear regime (VD = 0.1V) for TFT with nanostructured channel or the homogeneous IGZO channel under forward and backward scans. (f) Output characteristic of both TFTs. (g) Extracted apparent device mobility in the linear regime as a function of VG. The channel width and length of the transistors are 1000 and 135 μm, respectively. (h–k) Statistical data of devices with varied channel length (35 μm to 335 μm): (h) apparent mobility; (i) normalized on-current ID × L/W; (j) reversed sub-threshold slope SS; (k) on– off ratio ION/IOFF against channel length L The operational mechanisms in the off or on states were quantified by 2D device simulations with computer-aided design (TCAD). The calculated potentials, carrier concentrations, and electric field 11 ACS Paragon Plus Environment

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are shown in Figure 4 and the simulation parameters are shown in Table S1. In the off state, the nondegenerate IGZO with low electron concentrations formed regions of space charge and induced builtin electric fields near the IGZO/ITO interfaces, which impeded electron transport and comprised the source–drain field. In the on state, the electron concentration in IGZO increased to form transport paths between the degenerate parts. Consequently, the drop-in potential between source and drain mainly occurred in the IGZO parts, building up the periodic, large electric fields. The periodic heterojunctions confined a low off current at low gate fields and afforded a highly gate-tunable conductivity. In a control experiment, we exhibited changing gate-tunable conductivity by varying the length of the non-degenerate IGZO (Figure S13).

Figure 4. 2D device simulations of nanostructured degenerately doped heterojunctions of TFT for the “off” and “on” states (VG at 0 and 20V with VD fixed at 0.1V): (a) The overall schematic of the simulation structure (a side view). The red square represents the region of the results. (b, c) Distribution of electric potentials. (d, e) Distribution of electron concentration and the schematic of carrier transport. (f, g) The values of potential and electric fields near the channel–dielectric interface. 12 ACS Paragon Plus Environment

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The nanostructured TFTs are combined with a solution-processed, high-k dielectric layer of ZrO2 to implement low operational voltages and high output current, as shown in Figure 5. The device exhibited a steep threshold swing of 128 mV/dec, a large on-current of 636 μA at VG = VD = 5 V, and an apparent device mobility of 60.3 cm2V-1s-1 and 47.9 cm2V-1s-1 for the linear and saturated regimes, respectively. The transfer, output, and μ-VG curves are shown in Figures 5a–c with the extracted parameters summarized in Table 1. Moreover, the devices exhibited good stability in tests of positive and negative bias stresses (PBS and NBS) in air. As shown in Figures 5e and 5f, the shift in the turnon voltage (VON) was lower than 0.4 V and 0.2 V before 3000 s with a stressing gate biases of -2.5 V and 5 V, respectively. The bias in stressing stability was consistent with the negligible hysteresis, and manifested the low density of interfacial traps that were filled or neutralized by high carrier concentration in ITO.42 Note that the apparent device mobility was unsaturated and increased more sharply with VG compared with that in the homogeneous IGZO devices (Figures 3g and 5c). The μ–VG relations in devices with homogeneous semiconductors (e.g., with ZnO or IGZO) were due to potential fluctuations near the grain boundaries in the polycrystalline film, variance in bonding of the amorphous film, or other structural defects.43-45 The device with a continuous film of degenerated ITO did not exhibit noticeable gate-tunable conductivity (Figure S14). In the devices using the proposed technique, potential fluctuations near the IGZO/ITO heterointerfaces might have occurred from interfacial states or the energy offset between the work function of ITO (4.5 eV)46 and the conduction band edge of IGZO (4.3 eV). Such barriers and the depletion regions narrowed for tunneling as the gate-tuning increased the carrier concentrations.44 This might have been the reason for a sharper increase in transconductance and why apparent mobility was less likely to be saturated with increasing VG. For the device with a dielectric layer of SiO2, the apparent mobility exhibited the trend of saturation around VG = 40 V, indicating the tunneling process, i.e., carriers from the degenerated ITO to the non-degenerate IGZO, gradually became saturated as VG increased. For the device with a high-k dielectric layer of AlOX, the apparent mobility was low at relatively low 13 ACS Paragon Plus Environment

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operation voltage and was not saturated, which indicates that the tunneling effect at the IGZO/ITO interface was below that at the saturated state. In general, compared with the homogeneous IGZO transistor, mobility was less likely to be saturated because of interfacial defects between IGZO and ITO probably induced during the fabrication process.

Figure 5. Low-voltage nanostructured heterojunction TFTs with high-k ZrO2 dielectric layers. (a) Transfer curves with forward and backward scans in saturated (VD = 5V) or linear regime (VD = 0.1V). The gray lines represent the gate leakage current of the device. (b) Output characteristics. (c) Extracted apparent device mobility in linear regime as a function of VG. (d)Width-normalized total resistance as a function of channel length L. Gate voltage was varied from 2.6 to 5V. (e, f) The negative bias stress test (NBS) and positive bias stress test (PBS) in atmosphere for saturated regime (VD=5V). The stress biases of NBS and PBS were -2.5V and 5V, respectively. The channel width W and length L were 1000 and 85 μm, respectively. We then investigated the scaling effect of channel length L for two reasons. First, the above interfaces between IGZO and ITO might have caused contact resistance to hinder transport as well as artifacts in gate-dependent conductivity. Second, although previous studies have used high-current oxide transistors by employing nanowires or partial capping layers, the scaling effect has rarely been studied even thought it is important for practical applications and fundamental research. By varying L, we clearly observed the scaling effect as ID increased with shortening L, as shown in Figure 3k 14 ACS Paragon Plus Environment

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and Figure 5d. In particular, the total resistance Rtot= VD/ID exhibited a good linear relation with L as shown in the Figure 5d (with ZrO2) and Figure S15 (with SiO2). We calculated the channel resistance (RCH) dependent on L and contact resistance (RC) independent of L using the transmission line method (TLM)47 in the linear regime according to: 𝐿

(1)

𝑅tot𝑊 = 𝑅C𝑊 + 𝜇𝐶i(𝑉G ― 𝑉TH)

Here, μ, VTH, and Ci, are the apparent device mobility, threshold voltage, and the capacitance of the gate dielectric per unit area, respectively. When VG increased from 3 V to 5 V, the extracted value of RCW decreased from 83.2 to 32.6 Ω·cm, indicating the nearly ohmic contact near the source/drain electrodes and the heterointerfaces with a large gate field. The extracted values of apparent device mobility at VG=40 V and 5 V were 161.3 cm2V-1s-1 for the SiO2 device and 47.9 cm2V-1s-1 for the ZrO2 device, close to the values extracted from the transfer curves as shown above. We compared the proposed nanostructured TFTs with other reported oxide TFTs in terms of enhanced current and apparent device mobility. Dual active-layer TFTs have been proposed. They use a high-mobility semiconductor as underlying layer for transport and a low-carrier-concentration semiconductor material as top layer to guarantee a reasonable threshold voltage.48,

49

A thicker

underneath layer can induce high mobility and output current but sometimes may cause a negative shift in the threshold voltage and a low on/off ratio. A corrugated structure between InSnZnO (IZTO) and IGZO has been recently proposed to control the 2DEG with a dual active layer, and has yielded an apparent device mobility of 38 cm2/Vs (L = 50 μm).50 We summarize the performance of recently reported oxide TFTs in Table 1. The devices show a high on–off ratio, apparent device mobility, and obvious scaling effect. Moreover, we compare the output current of these devices with the ideal TFT, i.e., with constant mobility and zero VTH, in Figure 6. The normalized values of ID for each reported 1

device were obtained by dividing ID with the corresponding Ci and VGVD (for the linear regime) or 2 𝑉2G (saturated), and were compared with those of the ideal TFT with a series of mobility values (dashed lines). The normalized output current levels of the devices using the proposed strategy were among 15 ACS Paragon Plus Environment

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the highest, and reached the level of an ideal TFT with a constant mobility of 100 cm2/Vs and zero Vth.

Figure 6. Comparisons in terms of output current between recently reported TFTs and the ideal TFT. 1 Each drain current is normalized by division with VGVD if in the linear regime or 2𝑉2G if in the saturated regime with dielectric capacitance per unit area Ci. The width-to-length ratio W/L is used as horizontal coordinate to consider the scaling effect. The open and solid symbols represent the data measured from the linear and the saturated regimes, respectively. The dashed lines represent the values of the ideal TFT with zero threshold voltage and certain mobilities (the labeled numbers). The operational gate voltages for different TFTs are shown in Table 1. Table 1. Parameters of recently reported oxide TFTs with high device mobility, and the devices used in this work. μlin(a)

μsat(b)

VON

S.S

[nF/cm2]

[cm2 V−1 s−1]

[cm2 V−1 s−1]

[V]

[mV/dec]

Ci Semiconductor

Structure

Dielectric

Ion/Ioff

VG

Ref

[V]

ZTO/ITO

Double layer

SiO2

28.8

——

43.2

0.1

0.18

107

-10~20

49

ITZO/IGZO

Corrugated

Al2O3

108

——

38.09

-3.4

0.41

3.6×108

-15~15

50

In2O3(1)

Single layer

ZrOX

336

——

18.7

0.09

0.26

105

-1~4

51

In2O3(2)

Single layer

SiO2

8.63

——

16

-20

——

7×106

-30~60

52

In2O3/ZnO(1)

Double layer

235

——

36

-0.7

——

103

-1~2

53

In2O3/ZnO(2)

Double layer

SiO2

8.63

——

45

-40

——

107

-60~80

54

In2O3/ZnO(3)

Double layer

SiO2

34.5

——

47.9

-10.4

——

3×104

-25~40

55

In2O3/Li-ZnO

Double layer

SiO2

8.63

——

11.4

-48.7

——

4.5×105

-60~80

56

IGZO

Nano doping

PVP

13.2

——

79.2

-2.5

0.92

107

-15~20

57

IGZO

Ca capping

SiNx

70.8

——

160

-1

0.76

2.9×106

-15~20

28

IGZO

Composited with

SiO2

34.5

109

——

-12.5

——

108

-15~20

58

AlOX /ZrOX


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SnO2 nanowire Composited with IGZO

SiNx

53.1

——

105.3

-0.5

0.21

108

-15~20

59

42

Ag nanowire IGZO/ITO

Double layer

SiO2

34.5

31.6

——

-3.63

0.17

5×108

-10~20

IGZO/ITO

Nanostructured

SiO2

34.5

165.8

144.2

-0.75

0.32

1.75×109

-20~40

ZrO2

213

This work This IGZO/ITO

Nanostructured

60.3

47.9

-1

0.12

6.36×107

-3~5 work

𝐿

(a)

∂𝐼D

Extracted device mobility in linear region (VD VG − VTH) extracted from the transfer curve by using the equation 𝜇sat = 𝑊𝐶i

∂ 𝐼D 2

( ∂𝑉G ) . .

Phototransistors with wide-gap/narrow-gap nanointerfaces We also demonstrated the use of the proposed techniques to fabricate nanostructured heterojunction phototransistors with a transparent active layer (IGZO) and a light-absorber layer (MAPbI3). Half of the IGZO layers were converted into vertical nanostructured channels and covered with a patterned organolead halide perovskite photoabsorber (MAPbI3) layer by two-step fabrication (see Figures 7a–c). In this configuration, the perovskite light absorber layer did not come into contact with the source/drain electrode simultaneously, which guaranteed lower off-state current than in other phototransistors with a spin-coating capping layer. The transfer characteristics of the device in the dark and under illumination with visible light (550 nm) are plotted in Figure 7d. Upon illumination, the on-voltage (VON) shifted toward negative (-4 V) and the off-current remained under 10-9 A. The light-to-dark current ratio is shown as a function of VG in Figure 7e, and reached the maximum at 9346 (VG = -12.5 V and VD = 10 V). Compared with stacking heterojunction phototransistors composed of similar materials,60-63 the device with the proposed method exhibited a stable on–off ratio under illumination without significant degradation. In addition, in contrast to conventional heterojunction phototransistors, the asymmetrical structure achieved the unidirectional property, i.e., it could be turned on only when the positive drain voltage was applied to the side of the heterojunction with the other electrode grounded as the source. In the opposite case, the device could not be turned on (Figure S16) because the efficiency of electron injection from the electrode to MAPbI3 and IGZO 17 ACS Paragon Plus Environment

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was low. As shown in Figure 7f, the device integrated a TFT with a photodiode, had the capability to counteract reversed voltage, and provides opportunities for integrating the logic with detection functions.

Figure 7. (a) Schematic representation of nanostructured phototransistor with IGZO/MAPbI3 heterojunction. (b) Cross-sectional schematic of IGZO/MAPbI3 heterojunction. (c) Optical image of the phototransistor. (d) Transfer characteristics of phototransistors in the dark or under 550 nm of illumination. (e) The ratio between photo and dark currents of IGZO/MAPbI3 phototransistor extracted from (d). (f) The proposed unidirectional phototransistor can be simplified as a transistor and photodiode connecting in series. The channel width and length of the phototransistors are 1000 and 800 μm, respectively. The heterojunction phototransistor was evaluated by calculating responsivity (R), detectivity (D*), and linear dynamic range (LDR). These parameters can be calculated by the following equations:64 𝑅=

𝐼D ― ph ― 𝐼D ― dark 𝑃in 𝑅

𝐷∗ =

1 2

(2) (3)

(2𝑞𝐼D ― dark/𝐴)

𝐼D ― ph

LDR = 20log 𝐼D ― dark 18 ACS Paragon Plus Environment

(4)

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In the above, q is the elementary charge, ID-ph and ID-dark are the drain current in light and dark, respectively, and Pin is the power of the incident light, which is equivalent to the product of light power density and the device’s channel area A, and is the effective area of the detector. The data were extracted with 550 nm of laser light illumination with VG = -12 V and VD = 10 V. The average dark current was 2.5 × 10-11 A and the photocurrent was 2.0 × 10-7 A at a power density of 0.485 mW/cm2. The device with the proposed method achieved a responsivity of 50.7 mA/W, detectivity of 1.6 × 1010 J, and an LDR of 77.9 dB. The transient responses of the nanostructured phototransistor were measured by periodic 550 nm laser light with an on/off interval of 15 s at VG = -12 V and VD = 10 V. As shown in Figure S17, the nanostructured phototransistor exhibited fast response without significant persistent photoconductivity (PPC), which has been usually observed in transistors with oxide semiconductors.65 The rising and falling times of the transient response were 349 ms and 337 ms, respectively. The performance of the device performance was comparable to or even better than that of several recently reported IGZO-based hybrid phototransistors with organolead halide perovskite, 2D semiconductors, and organic materials.60-63, 66, 67 Compared with the non-nanostructured IGZO/MAPbI3 phototransistor (shown in Figure S18), the nanostructured phototransistors exhibited smaller negative shift in I-V curves, much faster transient response, and much larger light-to-dark current ratio under periodic illumination. It has been reported that the migration of MA+ ions during MAPbI3 deposition is responsible for the negative shift in the phototransistors.68 Such migration of MA+ ions may have been suppressed by a series of IGZO/MAPbI3 heterojunctions in nanostructured phototransistors. Moreover, the PPC phenomenon often observed in oxide TFTs69 has also been suppressed under the periodic illumination. This is because that, in the dark period, the MAPbI3 layer with a low conductivity prevented the residual photogenerated carrier transport through the heterojunctions and guaranteed a low dark current. Hence, the nanostructured phototransistors achieved fast transient response with significantly suppressed PPC phenomenon.


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Figure 8. (a) The energy-band diagram reveals the working mechanism of the IGZO/MAPbI3 nanostructured phototransistor under illumination. (b) Schematic diagram of molecular structures of MAPbI3 and IGZO. (c) The overall schematic of the structure of the simulation (a side view). The red square represents the region of results. (d–e) Results of TCAD simulation of the proposed phototransistors, demonstrating the distribution of electron concentration for the device under negative VG with illumination (d) and in the dark (e). The proposed working mechanism is as illustrated in Figure 8a, and shows the energy band diagram of the IGZO/MAPbI3 heterojunctions. In the dark, the low-conductivity MAPbI3 inhibited the injected electrons tunneling through the heterojunction and led to a low current. Under illumination, light-induced electrons and holes were generated in the conduction and valance bands in MAPbI3, either in the nanogap or on top of IGZO. The photogenerated charges tunneled into the IGZO layer to form electron conduction channels, and were transported in the horizontal source– drain field. This process is manifested by the negative VTH shift and increase in photocurrent, thereby implementing photodetection. We used the TCAD to simulate the nanostructured heterojunction phototransistor under visible light and the dark (see Figures 8d-e). With illumination and in the off 20 ACS Paragon Plus Environment

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state, the photogenerated carriers in MAPbI3 accumulated in the nanogaps and induced high electron concentration in the IGZO layer, in comparison with the negligibly small electron accumulation in the IGZO layer in the dark. Because of the energy barrier in the vertical heterojunction, the off current of the phototransistor had low values (~10-9 A) under illumination, and hence the devices exhibited a higher on–off ratio than phototransistors proposed in the literature.60, 61, 70

CONCLUSIONS In this study, we proposed and tested nanostructured TFTs fabricated by using a facile, costeffective, and high-throughput near-field photolithography technology. Centimeter-scale subwavelength nanostructures with a diversity of feature geometries were obtained by exploiting the array of totally reflective PDMS micro-pyramids or micro-trenches to modulate light intensity. The spacing between PDMS pyramids or trenches was reduced to 90 nm by reproducing the zigzag Si mold. Diffraction from the sub-wavelength spacings and total reflection at the sidewalls combined to prevent the exposure of the photoresist below these parts, and to produce nanogaps, nanodots, and nanodots in wafer-scale areas. We used the proposed nanolithographic method to fabricate transistors at the nanoscale and periodic degenerate/non-degenerate heterojunctions for high-current TFTs as well as wide-gap/narrow-gap heterojunctions for unidirectional phototransistors. Nanostructured TFTs with degenerate/non-degenerate interfaces exhibited 17.5 times the output current and transconductance than conventional TFT and, thus, a high on–off ratio (> 109). Device simulations provided quantitative mechanisms for how the nanostructures improved the on–off ratio in TFTs and light-to-dark ratios in unidirectional phototransistors. We expect many more combinations of materials and nanostructures to be explored using the proposed technique. This work can provide a platform for the investigation of interfacial effects at the nanoscale and functions in TFTs or FETs.

METHODS Fabrication of Si molds and polymer photomasks. We used conventional far-field 21 ACS Paragon Plus Environment

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photolithography with Cr-based hard photomasks to fabricate microscale positive photoresist features on Si/SiO2 (100) wafers with a 280-nm-thick SiO2 layer.26,

27

Subsequently after etching the

unprotected SiO2 with Buffered Oxide Etch acid (Transene Company), the photoresist was removed by ultrasonication of the samples in acetone. SiO2 patterns were thus obtained on the Si wafer. The samples were then subjected to wet anisotropic etching of exposed Si by KOH etching solution [30% KOH in H2O: isopropanol (4:1 v/v)] at 80 °C, forming zigzag-shaped recessed Si molds. The etching proceeds in both the horizontal and vertical directions. The etching speed was about 1 μm/min along the 100 Si crystal direction. Sharp apexes (30 nm) were obtained at the bottom of the zigzag Si molds after etching for a certain time (Figure 2b). By increasing the etching time, the spacing between adjacent Si trenches became increasingly small. By carefully controlling the etching time, a spacing of 60 nm or more may be created between the adjacent trenches. For instance, starting from the patterns with SiO2 feature size and spacing of 2 and 1 µm, respectively, Si trenches spaced 60 nm apart can be obtained by wet anisotropic etching for 2.2 min (Figure 2a). Subsequently, the samples were placed in buffered hydrofluoric acid for sufficient time (7 min) to remove the remaining SiO2 blocking layer. Zigzag Si trenches with various horizontal geometries such as rectangles, squares and concentric squares could be generated in this way. After fabricating the zigzag Si molds, arrays of zigzag PDMS pyramids or trenches were replicated from these Si molds.2 Soft PDMS (Sylgard 184, Dow Corning Singapore Pte. Ltd.) was used to fabricate the arrays of PDMS pyramids or trenches with sticky surfaces. The mixture of PDMS and its curing agent at a 10:1 wt ratio was stirred, degassed, and poured on top of the Si molds. For preparing soft PDMS structures without rigid back cover, the PDMS mixture was poured onto the Si molds so that the PDMS layer was about 0.3 cm thick. To prepare PDMS masks with glass or quartz support, after the glass or quartz was treated by oxygen plasma, the hydrophilic glass or quartz substrates were placed on top of the mixture. The assembly was degassed and then cured at 70 °C overnight. Finally, the PDMS trenches were carefully separated from the Si masters for near-field optical patterning. Centimeter-scale or even 5-inch wafer PDMS masks can be obtained in this way. 22 ACS Paragon Plus Environment

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Lithographic procedures on positive-tone photoresist surfaces. A layer of 20% (v/v) diluted positive-tone photoresist (Shipley 1805) was spin coated onto Si/SiO2 (100) wafers. The photoresist was pre-diluted with propylene glycol monomethyl ether acetate (Sigma-Aldrich) and spin coated at 2500 and 1000 rpm for 30 s to obtain 50- and 120-nm-thick photoresist layers, respectively. The photoresist-coated substrates were then soft baked on a hot plate at 105 °C for 4 min. The sticky PDMS photomasks were placed on photoresist-coated surfaces for near-field photolithography. An adjustable halogen light source (Fiber-lite Illuminators MI150, EX-PACK TECHNOLOGY PTE LTD) was used to expose the photoresist for 1 s with an intensity of 250 mW/cm2. After exposure, the samples were developed in MF319 for 30 s. To transfer photoresist nanostructures to metal nanopatterns, the resulting photoresist nanostructures were sputtered with 10 nm Cr or 2 nm Cr and 15 nm Au, followed by lifting off the photoresist in acetone. For dry etching, 20% (v/v) diluted positive-tone photoresist (Shipley 1805) was spin coated onto Si/SiO2 (100) wafers. After exposure and development, 100 nm SiO2 layer was etched by reactive ion etching (RIE, Oxford Plasmalab System100) for 3 min. The various pressures on PDMS mask were controlled by changing the weight of the covering glass. The nanostructures could then be imaged by optical microscopy (Olympus), AFM (Park Systems Co.), and SEM (JEOL JSM-7600). Lithographic procedures on negative-tone photoresist surface. Negative-tone photoresist SU8 2002 (MicroChem Inc., USA) was pre-diluted with SU-8 2002 thinner at 20% (v/v). The diluted SU-8 2002 photoresist was spin coated onto Si (100) wafers at 2000 and 1000 rpm to get 100- and 500-nm-thick SU-8 photoresist layers, respectively. Before exposure, the photoresist-coated Si wafers were pre-baked on a hot plate at 95 °C for 1 min. The typical exposure time on the aforementioned mask aligner was 2 s. After exposure, the samples were post baked at 95 °C for 2 min, followed by photoresist development in SU-8 developer (MicroChem Inc., USA) for 10 s. Fabrication of nanostructured TFTs and phototransistors. The IGZO/ITO heterojunction TFTs were fabricated in a bottom-gate, top-contact configuration on 2 cm × 2 cm heavily doped n-type Si substrate. The precursors of high-k dielectric material ZrO2 was prepared by dissolving 0.2 mol/L 23 ACS Paragon Plus Environment

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zirconyl chloride octahydrate (ZrOCl2·8H2O, reagent grade, 98%, Sigma-Aldrich) in 5 mL 2methoxyetanol (anhydrous, 99.8%). The solution was stirred at room temperature for 3.5 h and aged for 1 day. The precursor solution was filtered by a 0.45 μm polytetrafluoroethylene syringe and spin coated at 4000 rpm for 30 s, followed by annealing at 150 °C for 15 min. To obtain multilayer dielectrics, spin coating and annealing were repeated twice. The ZrO2 layers were created by spin coating two layers. The samples were annealed at 400 °C for 2 h after dielectric-film deposition. A 50 nm ITO film was deposited onto the dielectric layers by DC sputtering and then exposed for 1 s by using the totally reflective PDMS mask. The compared devices with 1μm or 2μm micro gaps were defined by conventional far-field photolithography with Cr-based hard photomasks. The ITO films were then etched in hydrochloric acid solution (38% hydrochloric acid: deionized water =1 mL: 40 mL) to form patterns with 300nm nanogaps. A 70 nm IGZO film was deposited on the samples by RF sputtering to fill the nanostructure channels and generate heterojunction with ITO. The channel area of TFT was defined by normal photolithography and IGZO/ITO layers were etched in hydrochloric acid solution (38% hydrochloric acid: deionized water =1 mL: 40 mL). After postannealing at 350 °C for 1 h, the source and drain electrodes consisted of 100-nm-thick Al deposited by ac sputtering through shadow masks. The normal IGZO TFTs on SiO2 or ZrO2 gate dielectrics were fabricated by the same processes without the ITO deposition and near-field photolithography. For the nanostructured heterojunction phototransistors, 30 nm sputtered IGZO was defined by nearfield photolithography with nanogaps in 300 nm, and then. To fabricate the perovskite MAPbI3 capping layer, 150 nm thick patterned PbI2 was thermal evaporated using shadow mask and followed by spin-coating MAI solution at 3000 rpm for 60 s and then heated on a hot plate at 100°C for 20 min. To remove residual MAI, dripping IPA on the sample during spinning at 3000 rpm and heated at 100°C for 10 min. The 30 mg mL-1 solution of MAI were synthesized by dissolving MAI in isopropanoland heating at 70°C overnight. Source and drain electrodes were fabricated with 100-nmthick Mo deposited by DC sputtering through shadow masks. Device simulations. For the simulation of light path shown in Figure 1, a 2D simulation is carried 24 ACS Paragon Plus Environment

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out with Comsol Multiphysics. Physics models used in Comsol Multiphysics includes geometrical optics and electromagnetic waves. The size of the cones in the simulation is exactly the same as ones fabricated in our experiment. In the simulation, 300 nm parallel light emits from the top edge of simulation area. The boundary condition uses a perfect match layer. For TFT calculations shown in Figure 4 and Figure 8, the technology computer aided design (TCAD) 2D device simulations are performed and details are shown in the supporting information. Device characterization. The electrical characteristics and photoresponse of the phototransistors were tested by using an Agilent B1500A semiconductor parameter analyzer under ambient conditions in the dark or illuminated state at room temperature unless stated otherwise. For photoresponsivity measurements, the applied drain-to-source voltage VD was fixed at 10 V, and the gate-to-source voltage VG was swept from −20 to 20 V in all measurements. The electrical measurement was first performed in the dark, and then under illumination. Lights of various wavelengths were provided by a 500 W Xenon arc lamp and Monochromators (Zolix Omni-λ).The incident optical power was measured by a high sensitivity power meter (Newport 818-UV-DB).

ASSOCIATED CONTENT Supporting Information The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsnano.XXXXXXX. Details of near-field photolithography with textured masks (simulation result, morphology characterization, and various programmed patterns), electric characteristics of nanostructured TFTs and phototransistors, and the paramaters in device simluaiton. (PDF)

AUTHOR INFORMATION #These

authors contribute equally to this work.

*E-mail: [email protected] 25 ACS Paragon Plus Environment

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*E-mail: [email protected] Author Contributions The manuscript was writtern through contributions of all authors. All authors have given approval to the final version of the manuscript. The authors declare no competing financial interest. ACKNOWLEDGEMENTS C. L. gratefully acknowledges the financial support of the project from the National Natural Science Foundation of China (61774174), the Guangdong Youth Top-notch Talent Support Program (No. 2016TQ03X648), and the Guangdong Natural Science Funds for Distinguished Young Scholars under Grant 2016A030306046. J.W. acknowledges the financial support from the Guangdong Natural Science Funds grant (2018A030313400).

REFERENCES (1) Nabil, H. A.; Talal, K. A.; Chandra, S. R.; Boon, O.; Mustafa, H. M., Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays. Small 2018, 14, 1703200. (2) Lee, B. H.; Hsu, B. B. Y.; Patel, S. N.; Labram, J.; Luo, C.; Bazan, G. C.; Heeger, A. J., Flexible Organic Transistors with Controlled Nanomorphology. Nano Lett. 2016, 16, 314-319. (3) Lin, H.-C.; Stehlin, F.; Soppera, O.; Zan, H.-W.; Li, C.-H.; Wieder, F.; Ponche, A.; Berling, D.; Yeh, B.-H.; Wang, K.-H., Deep Ultraviolet Laser Direct Write for Patterning Sol-Gel InGaZnO Semiconducting Micro/Nanowires and Improving Field-effect Mobility. Sci. Rep. 2015, 5, 10490. (4) Suhui, L.; Jiyeong, S.; Jin, J., Top Interface Engineering of Flexible Oxide Thin-Film Transistors by Splitting Active Layer. Adv. Funct. Mater. 2017, 27, 1604921. (5) Suhui, L.; Yuanfeng, C.; Jeonggi, K.; Hyo-Min, K.; Jin, J., Transparent AMOLED Display Driven by Split Oxide TFT Backplane. J. Soc. Inf. Display 2018, 26, 164-168. (6) Yang, Y.; Zheng, Y.; Cao, W.; Titov, A.; Hyvonen, J.; Manders, J. R.; Xue, J.; Holloway, P. H.; Qian, L., HighEfficiency Light-Emitting Devices Based on Quantum Dots with Tailored Nanostructures. Nat. Photonics 2015, 9, 259266. (7) Matterson, B. J.; Lupton, J. M.; Safonov, A. F.; Salt, M. G.; Barnes, W. L.; Samuel, I. D. W., Increased Efficiency


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