Research Article www.acsami.org
Nanostructures Significantly Enhance Thermal Transport across Solid Interfaces Eungkyu Lee,† Teng Zhang,† Taehee Yoo,† Zhi Guo,† and Tengfei Luo*,†,‡ †
Department of Aerospace and Mechanical Engineering and ‡Center for Sustainable Energy at Notre Dame, University of Notre Dame, Notre Dame, Indiana 46556, United States S Supporting Information *
ABSTRACT: The efficiency of thermal transport across solid interfaces presents large challenges for modern technologies such as thermal management of electronics. In this paper, we report the first demonstration of significant enhancement of thermal transport across solid interfaces by introducing interfacial nanostructures. Analogous to fins that have been used for macroscopic heat transfer enhancement in heat exchangers, the nanopillar arrays patterned at the interface help interfacial thermal transport by the enlarged effective contact area. Such a benefit depends on the geometry of nanopillar arrays (e.g., pillar height and spacing), and a thermal boundary conductance enhancement by as much as ∼88% has been measured using the time-domain thermoreflectance technique. Theoretical analysis combined with low-temperature experiments further indicates that phonons with low frequency are less influenced by the interfacial nanostructures due to their large transmissivity, but the benefit of the nanostructure is fully developed at room temperature where higher frequency phonons dominate interfacial thermal transport. The findings from this work can potentially be generalized to benefit real applications such as the thermal management of electronics. KEYWORDS: thermal boundary conductance, thermal boundary resistance, solid interfaces, thermal managements, nanostructures
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solid interfaces, like the substrate/device layer interface.22,23 They present great challenges for thermal management since they can contribute a large portion of the overall thermal resistance. For example, in a high power GaN-on-SiC device, over half of the total temperature rise in the device is contributed by the GaN/SiC interface due to its large thermal boundary resistance (TBR).14,17,20,24 Improving interfacial thermal transport to reduce the TBR is thus imperative to prevent performance degradation and enhance device reliability of electronic devices.25,26 Several strategies have been presented to enhance thermal boundary conductance (TBCinverse of TBR), such as atomic level species mixing,27,28 surface functionalization,3,29−32 and promoting interband phonon interactions.33,34 These strategies are proposed to improve TBC either by bridging the phonon spectra mismatch or by enhancing interfacial bonding. However, these have hardly been actually realized for solid interfaces, which are technologically relevant to electronics packaging. Incorporating nanostructures at interfaces has recently been proposed to increase TBC at solid−solid interfaces through molecular dynamics (MD) simulations and theoretical studies.35−37 The mechanism of the predicted
INTRODUCTION Engineering materials and heterostructures with nanoscale features have been under the research spotlight for the past few decades as they have led to unconventional optical, mechanical, electrical, and thermal properties not seen in traditional materials. The mechanisms behind these novel properties are multifaceted, including quantum confinement, solid-state band structure turning, classical size effect, etc.1−6 These nanofeatures have benefited many engineering applications such as solar cells,7,8 batteries,9,10 and thermoelectric devices.11,12 Miniaturization into nanoscale has also been the major trend of electronic devices. With an unprecedented number of transistors packed in tiny areas, the power density becomes enormous, making thermal management the bottleneck for the continued electronics miniaturization.13−16 Such a problem is even more serious for power electronics, where heat dissipation can lead to hot spot temperature tens of degrees higher than the average package temperature.17−19 For example, in GaN transistors on SiC substrates, joule heating near the channel region can lead to local temperatures above 115 °C.17,20,21 Due to the significantly larger surface to volume ratio of miniaturized heterostructures in electronics, the property of interfaces can sometimes play dominant roles in the overall behavior and performance of the device. Most microelectronic devices (e.g., Si-based and III−V nitride electronics) have multilayer heterostructures, involving a large number of solid− © 2016 American Chemical Society
Received: October 14, 2016 Accepted: December 6, 2016 Published: December 6, 2016 35505
DOI: 10.1021/acsami.6b12947 ACS Appl. Mater. Interfaces 2016, 8, 35505−35512
Research Article
ACS Applied Materials & Interfaces
Figure 1. (a) Schematics of Si nanopillars, where the pillars have square-shape with slightly rounded corners. The pillars have a top side length of Ltp, bottom side length of Lbp, and height of Lh. The pillar array has a periodic length of Lbp + Ls, where Ls is the pillar spacing. The area highlighted by the red solid line indicates the unit cell. (b−e) SEM images of fabricated nanopillar arrays on Si substrate with (b and d) Ls = 15 nm and (c and e) Ls = 57 nm. We note that the scale bars in panels b and c are different from those in panels d and e. (f and g) Cross-sectional SEM images of the nanostructured Al/Si interface for (f) Ls = 15 nm and (g) Ls = 57 nm, which were taken at an angle of 52° with respect to the normal (parallel to the pillar height) direction. The Pt layers were added for focused ion beam cross-sectioning. For all pillars shown in panels b−g, Ltp = 58 nm, Lbp = 87 nm, and Lh = 50 nm.
enhancement is mainly due to the enlarged interfacial contact area at the nanostructured interfaces compared to flat ones, which is analogous to the fins used in traditional heat exchangers. Hu et al.35 showed in their MD simulations that TBC of a SiC/GaN interface can be increased by periodic interlaced nanopillar structures, and an enhancement of ∼50% was achieved. Another MD simulation by Zhou et al.36 on a model interface showed similar enhancement and argued that such TBC enhancement was proportional to the enlarged contact area due to the nanopillars at the interface. These simulations, however, studied pillar sizes (
