New Type of Programmable Current-Regulated Power Supply for Operation of Hollow Cathode Lamps in a High Intensity Programmed Mode James D. Defreese, Terry A. Woodruff, and Howard V. Malmstadt’ Department of Chemistry, University of Illinois, Urbana, Ill. 6 180 1
A new type of power supply for the operation of hollow cathode lamps In a high Intensity, programmed, current-regulated mode is descrlbed. The power supply provldes the very precise current regulatlon necessary to ensure stable light output from the lamps. The control system Is applicable also to many other analytical instruments employing servo feedback control. Per cent relative standard deviations of better than 0.005% were obtained for any given load and current value between 20 mA and 210 mA. The maximum change In absolute current is only 0.03% for different hollow cathode lamps or large changes In load resistance or fluctuatlons In the output voltage of the raw supply. The power supply is regulated by digital feedback circuitry which varies the load current Incrementally until the voltage drop across a senslng resistor Is equal to a reference voltage. Major advantages of incremental control over analog control are that the response of the digital feedback circuit can be easily varied to match the total system response, the regulation has been shown to be more precise and accurate, and it is readily programmed by computer or hardware controllers.
Hollow cathode lamps have been shown to be of great utility when operated in a high current, programmed mode. Advantages include greatly increased intensity, improved stability and essentially no warm-up time compared to lamps operated in a dc mode (1).These improvements have made hollow cathode lamps excellent sources for atomic fluorescence (AF) ( 2 ) as well as atomic absorption (AA) spectrometry. The higher intensity and stability lead to increased sensitivity and reproducibility of fluorescence determinations. Also, the modulation of the hollow cathode lamps by a programmable current source provides the same measurement advantages obtained by the more cumbersome mechanical chopping of the radiation from a continuous source. A programmable power supply for operation of hollow cathode lamps in a programmed (intermittent) currentregulated high intensity mode was recently reported (2, 3 ) . T h e control circuit for that supply, although controlled by logic signals, was essentially analog in nature. The digitally controlled constant current source described here has several significant advantages over the typical analog circuits. It exhibits a faster ON-OFF response to the control signals and still provides the very precise current regulation necessary to ensure stable light output from the lamps ( I ) . The supply is shown to provide better current regulation than the previous one ( 3 ) .Although it did not produce a proportionate improvement in the stability of the hollow Address requests for reprints to this author. ( 1 ) E. Cordos and H. V . Malrnstadt, Anal. Chem.,45, 27 (1973). (2) H. V. Malrnstadt and E. Cordos. Amer. Lab., 4 (8),35 (1972). (3) E. Cordos and H.V . Malrnstadt, Anal. Chem., 44, 2407 (1972)
cathode lamp output, a t least within the limitations of the measurement system used, the regulation concept used in this supply is applicable to a wide variety of other analytical instruments employing feedback control. The feedback circuit presented here is a general model which, by varying the clock rate to control the response speed, could be used in almost any feedback control application. It is particularly valuable in systems which use a programmed mode of operation where the programmed value of the regulated variable is changed in stepped fashion. This is because the control system allows for extremely fast slewing, not limited by the necessary matching of the controller response speed to the controlled system response speed, which is necessary to avoid oscillation. The digital feedback power supply provides accurate and precise current pulses with per cent relative standard deviations (RSD) of about 0.005% for a given current and load. The absolute current is constant within about 0.01% for a t least twofold changes in the load and fluctuations of f20% in the raw voltage supply. Data are also presented on the regulation of the hollow cathode output intensity. The design principles and the experimental data for the programmable digitally controlled power supply are presented in subsequent sections. The advantages of the digital control circuit are also discussed.
PRINCIPLES OF OPERATION A simplified diagram of the digital power supply is shown in Figure 1. The high voltage, high current, unregulated raw supply V,, is connected in series with the hollow cathode lamp H.C., a power transistor Q1and a switchable accurate resistance R,. Any variation in the hollow cathode load current iL because of fluctuations in the raw voltage supply or in lamp resistance causes a change in the voltage drop us across the reference resistance R,. The change in u, causes the control circuit to vary the base current Q1 in such a way as to readjust the load current to the value dictated by the reference voltage Vre. and R,. As a specific example, assume i~ increases during the ON time of the hollow cathode lamp due to a fluctuation in the raw supply. The voltage drop across R , becomes more negative with a resultant voltage drop at the noninverting input of the comparator. The output of the comparator goes low, causing clock pulses to be gated to the UP input of the counter. As the count in the counter increases, the negative output voltage of the digital-to-analog converter (DAC), -UDAC, decreases in magnitude since the DAC has negative logic inputs. OAl (Burr-Brown 3308/12C), Q2, R4 and Rs invert the DAC output voltage and provide the necessary output current capability. The amount of current delivered from the inverter to the base of Q1 through R5 and D1 is decreased, thereby decreasing the load current. This process continues until the magnitude of u s is detectably less than that of Vref, at which time the comparator again changes state, causing the counters t o count down. Thus,
ANALYTICAL CHEMISTRY, VOL. 46, NO. 11, SEPTEMBER 1974
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Figure 1. Block diagram of power supply
the gating of U P or DOWN pulses to the counter controls the current through the lamps. The control circuit is active only during the time the lamp is turned ON, which is determined by the sequencer. The lamp ON time (usually 10 msec), the OFF time between pulses (usually 90 msec), the number of ON/OFF periods in the pulse train (10-20) and the time between pulse trains (10-20 sec) can easily be modified by the sequencer. The lamp is turned ON when current is applied to the base of Q1 through R5 and Rs. Between pulses, this current is shunted to ground through the open-collector (OC) buffer (7406 I.C.), Q1 is turned off and no current flows through the hollow cathode lamp. Therefore, the ON/OFF pattern of the lamps is controlled by logic signals supplied to the OC buffer. Also, the gating circuit is turned OFF between pulses, thus storing the count in the counter. Resistor R; shunts the collector-base leakage current of $1 to ground so that it is not amplified. I t is necessary to keep load current leakage between pulses in the 0.1-0.2 mA range or lower or the result may be significant drift and poor reproducibility ( I ) . The value of the regulated load current is determined by
iL = z',/R, where R , is the effective resistance of the parallel precision resistors R, and R1. They are in parallel because R, is grounded and R1 is held a t virtual ground a t the noninverting input of the comparator. Since R1 = RZ = 1K, and -us = Vref,it follows that
From Equation 2 , it is seen that the value of the load current can easily be changed by varying either Vref or R,. For this work, Vref was set a t 10,000 V and the value of the reference resistance R , was varied to set the load current. Therefore, 1472
iL =
lolooo + 10 Rs
mA
(3 )
EXPERIMENTAL The raw high voltage supply V,, was obtained by modification of the Heath EU-703 current-regulated dc power supply as reported previously ( 3 ) .The power supply is capable of delivering u p to 300 mA and can also be used to operate the lamps in a dc mode if desired. Comparator. It is desirable t h a t the comparator (type 710 I.C.) be as sensitive as possible to changes in L',without being overreactive to noise. T h e current mode comparator configuration shown in Figure 1 offers several advantages over others that were investigated and is probably the most commonly used a t present ( 4 ) . First, resistors R1, RP, and RB and capacitor C yield an RC time constant which tends to average out high frequency noise. RBalso reduces the effect of variations in the input bias current of the comparator. Second, the common mode voltage is always near zero which reduces common mode errors and provides best comparator operation. Also, the reference voltage Vref can be greater than the input voltage rating for the comparator inputs which is desirable since the larger Vref, the less significant are the comparator offset voltage changes and the greater the effective resolution of the comparator. Diodes DP and D3 (1N4149) form a protection circuit for the comparator input. A Schmitt trigger ST (7413 I.C.) is .placed after the comparator to sharpen the transitions of the comparator output. Reference Voltage Source. A type 723 precision I.C. voltage regulator was used to obtain a stable Vref of 10.000 V. Because of the comparator configuration used, Vref must be capable of providing a t least 10 mA of current. The use of a n external transistor with the 723 voltage regulator to satisfy the requirements of a precisely regulated voltage source with current delivering capability is shown in Figure 2. Potentiometers P1 and P 2 provide coarse and fine voltage adjustments, respectively. Since the reference voltage was not varied, it was also used to regulate the supply voltages for the comparator I.C. to increase stability (see Figure 3). Gating Circuit. T h e detailed gating circuit (gate) is shown in Figure 4.In addition to gating the clock pulses to either the U P or the DOWN input of the counter and to turning the count O N or Sheingold. Ed., "Analog-Digital Conversion Handbook." Analog Devices, Inc., Norwood, Mass., 1972, p 11-84.
(4) D. H.
ANALYTICAL CHEMISTRY, VOL. 46, NO. 11, SEPTEMBER 1974
OFF, a major function of the gating circuit is to prevent extraneous counts during transitions of the UP/DOWN and ON/OFF control signals. This is accomplished by keeping the UP/DOWN count inputs normally a t logic level “1.” Whenever the edge-triggered D flip1 transition of the clock, the flops (7474 I.C.) are toggled by a 0 datum a t D is transferred to Q. The counter is toggled only when a “0” is transferred to Q. T h e RC network determines the time Q is low (just long enough to toggle the counter, typically 20 nsec including the flip-flop preset delay) by delaying the “0” signal to the preset input which causes Q to be reset to “1.” Clock. The clock signals for the control system are obtained from a 10 MHz oscillator constructed from a voltage controlled oscillator I.C. (Motorola MC4024) and a 10.000 MHz crystal. Decade counters are used to scale down the frequency. The clock circuit performs two functions. First, it clocks the counters through the D flip-flops. Note that the frequency stability of the clock is not critical in this application because frequency drift would only slightly affect the response of the system and not the accuracy. However, clock precision is needed because the clock signal is also used in the sequencer where an accurately known frequency is required to obtain accurate lamp pulse timing. Counter. Three synchronous 4-bit binary UP/DOWNcounters (74193 I.C.) make up the counter for the system. If an 8-bit DAC were used rather than the 10-bit one, two counters would be sufficient. The counters are wired as a dead end UP/DOWNcounter ( 5 ) as shown in Figure 5 . If such a configuration is not used, the counter may underrange (count goes to zero and then to all “1” ’s on the next DOWN pulse) when the lamp is first turned ON since the load current does not reach its specified value instantaneously. The control circuit causes the counter to count down (increase current to base of Q1) and underranging may occur, depending on the clock frequency, the initial count in the counter, and the risetime of the load current. If underranging does occur, the DAC output voltage goes to zero (count is all “1” ’s) and the load current decreases. T h e counter must then continue to count down from all “1” ’s until the proper load current is established. Such a situation is avoided with the dead end counter. When the borrow output goes low, the counter is cleared to zero. Since the count cannot go to all “1” ’s, underranging does not occur. Overranging is also prevented because a carry pulse loads “1” ’s into the counter. Digital-to-Analog Converter (DAC). A Heath EU-800-GC 10-bit D/A converter card (Analog Devices, Inc. MDA 102-25 DAC) was used in the voltage mode. The input to the EU-800-GC card is negative logic so that an input of all zeros gives a full scale output voltage of -10 Y. An input of all ones gives zero volts out. Although a 10-bit DAC was used in this work, an inexpensive, low resolution DAC which is not highly linear ( e . g . , 30%) and has considerable drift can be used to obtain equivalent current regulation if a resolution enhancing technique is used to reduce the magnitude of the current change for a unit change in the count. It is desirable, however, to avoid monotonicity errors in the DAC which causes locally reduced resolution. DAC Resolution Enhancement. The effective resolution of the DAC can be increased by summing a fixed voltage or current with the DAC output. In Figure 1, the current through R j from the DAC is summed with a fixed current through Rg at the base of Q1.
+15V
I
-
2050
4
N I.
6 Figure 2. Schematic diagram of 10,000-V reference source
+I,-.
74 I
( I “,*f OOV)
+I2 0
v
I
- 6.0V Figure 3. Supply voltages for comparator
ON/OFF
.
D
0
I T
COUNT DIRECTION
DOWN
7474
CLOCK
(5) Fairchild Semiconductor, Mountain View, Calif., Application Note 304 (1972).
Figure 4. Gate
W
z c
a W
9 UP 3
C A R R Y bU 74193
DOWN
PA
C
U
B
D
C 3
14193 BORROW-
D
OB OC 0 0
74193
B ‘A
TO
DAC
‘8
‘C
‘0
INPUTS
Figure 5 . 10-Bit dead end up/down counter
ANALYTICAL CHEMISTRY, VOL. 46, NO. 1 1 , SEPTEMBER 1974
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1
7 A l E . A
0
CLEAR MEASUREYENT SYSTEM
The circuit described in this paper can be built for $50 in parts plus the cost of a raw supply if a low cost, 8-bit DAC and OAl are used.
RESULTS AND DISCUSSION T h e power supply was tested to show that the load cur-
CLOCK
I
Figure 6. Control signal generator
The magnitude of this additional current is determined by the value of Re and its +15-V source. These need not be highly stable since the control circuit will automatically correct for variations in the added current by changing the current through R5 accordingly. With this current addition, the amount of current required from the DAC branch is diminished. By increasing the value of Rg,the full range of the counter is used to supply this current. Consequently, it is practical to use a 10-bit DAC to regulate the load current t o about the same precision as a more expensive (e.g., 12-bit) DAC without current addition. Sequencer. The function of a sequencer is to set the timing for, and to synchronize, system activities such as measurement of PM tube current, printing of data on a teletypewriter, setting flags for a computer, etc. In this application, the control signals to perform these activities are obtained from the decoded outputs of a binary counter which is clocked by a scaled frequency from the 10 MHz clock. An example of the use of the control signals (decoded outputs) is shown in Figure 6. As shown, output 11 clears the binary counter so that all 16 outputs are not used. The time between pulse trains is easily set by choosing the input frequency to the counter and the decoded output which clears the binary counter. For example, with a 0.5-Hz input signal and clearing on output 11, the time between pulse trains is about 19 seconds. The timing circuit for pulsing the lamps is shown in Figure 7. The three cascaded decade counters (7490 I.C.), flip-flops (7476 I.C.) 1 and 2, monostable MS (74121 I.C.), and associated nand gates (7400 I.C.) provide the timing for the ON/OFF pattern of the lamp. As drawn, the lamp ON time is 10 msec in duration with 90 msec between pulses. The pulse train is initiated by toggling FF4 with a control signal (see Figure 4). Gate 6 synchronizes the clearing of FF3 (opening of gate 3) so that no partial lamp pulses are allowed. The pulses at the output of gate 4 are counted by a decade counter (or counters). In the configuration shown, after 10 pulses, FF3 is toggled by the 1 0 transition of the D output of the counter and the pulse train is terminated.
-
CONTROL SIGNAL
t
rent is independent of the type of load. Ten control pulses generated by the timing circuit of Figure 7 were applied to the OC buffer and the integrated voltage across R, was obtained. Pulse widths of 10 msec were used because our experience indicated that it is a desirable median from the standpoint of not only obtaining good lamp output regulation but also for conveniently and accurately making the analytical measurements in which the lamps are used. Only the last 90% of the pulses was integrated to eliminate any effect of variable rise times and turn-on transients in the lamps or in the supply. Typically, the rise time for the lamps is about 1 psec with a settling time of less than 7 gsec. Fall times are less than a microsecond. In this particular application, the fast response time of the supply is not a significant advantage since the first 10% of each pulse is not measured. The integrated voltage values given in Table I for each current are the average of 10 such determinations. The absolute values reflect the choice of RC time constant of t h e integrator. The first line of data for each current in Table I is for a 1-MHz clock with R6 (Figure 1) supplying approximately 70-75% of the base current to Q1.T h e per cent relative standard deviations of the 10 integrations at each current show that the precision is better than 0.005% regardless of the load. Also shown is that the % RSD across a row (given current, varying load) or down a column (given load, varying current) is less than 0.01%. The data in rows two and three a t each current in Table I illustrate the dependence of load current on the frequency of clocking the U P D O W N counters when no current is added from Re. Although the per cent relative standard deviations for the individual values are not as low as when current addition is used, they are still generally within 0.01%. The % RSD across the rows are within 0.1%, the resolution of the 10-bit DAC, and it is seen that apparently a lower clock frequency (100 kHz) is better at low currents and that a higher one (1MHz) gives better results at higher currents. This can be attributed t o system response
*-nq== 7476
U
I
oc
b
CLR
7490
7490
7490
MSI 74121
FF2 7476
b CLR U
Figure 7. ONIOFFtiming circuit
ANALYTICAL CHEMISTRY, VOL. 46, NO. 11, SEPTEMBER 1974
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a
