Nonvolatile Electric Double-Layer Transistor Memory Devices

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Non-volatile Electric Double Layer Transistor Memory Embedded with Au Nanoparticles Jaemok Koo, Jee Hye Yang, Boeun Cho, Hyunwoo Jo, Keun Hyung Lee, and Moon Sung Kang ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.8b01902 • Publication Date (Web): 22 Feb 2018 Downloaded from http://pubs.acs.org on February 23, 2018

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ACS Applied Materials & Interfaces

Non-volatile Electric Double Layer Transistor Memory Embedded with Au Nanoparticles Jaemok Koo#,†, Jeehye Yang #,†, Boeun Cho†, Hyunwoo Jo.† Keun Hyung Lee‡, and Moon Sung Kang*,† †

Department of Chemical Engineering, Soongsil University, Seoul, 156-743, Korea

‡

Department of Chemical Engineering, Inha University, Incheon, 402-751, Korea

(# These authors contributed equally to this work) KEYWORDS: non-volatile transistor memory, low-voltage operation, electric double layer, ion gel, Au nanoparticles

ABSTRACT We present non-volatile transistor memory devices that rely on the formation of electric double layer (EDL) at the semiconductor electrolyte interface. The two critical functional components of the device are ion gel electrolyte and gold nanoparticles (NPs). The ion gel electrolyte contains ionic species for EDL formation that allow inducing charges in the semiconductor/electrolyte interface. The gold NPs inserted between the ion gel and the channel layer serve as trapping sites to the induced charges to store the electrical input signals. Two different types of gold NPs were used: one prepared using direct thermal evaporation and the other prepared using a colloidal process. The organic ligands attached onto the colloidal gold NPs prevented the escape of the trapped charges from particles and thus enhanced the retention characteristics of the programmed/erased

signals.

The

low-voltage

driven

EDL formation

resulted

in

a

programmed/erased memory signal ratio larger than 103 from the non-volatile indium-galliumzinc-oxide (IGZO) transistor memories at voltages below 10 V, which could be held for >105 sec. The utility of the electrolytes to operate memory devices demonstrated herein should provide an alternative strategy to realize cheap, portable electronic devices powered with thin-film batteries.

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INTRODUCTION Nonvolatile transistor memories (NvTMs) have great potential due to their capability for non-destructive read-out, compatibility with complementary metal-oxide-semiconductor (CMOS) circuits, and minimal power consumption necessary to retain the stored information.1-4 Programming or erasing processes for typical NvTMs rely on applying a voltage to the gate electrode (Vprog or Vera, respectively) that leads to a variation in the electrical environment near the transistor channel and the corresponding change in the current level of the device. Such processes constitute programmable and erasable 2-bit digital signals, i.e., the ‘0’ state and the ‘1’ state of the memories.5 To realize such NvTMs in a flexible device platform, various types of functional gate dielectric layers have been developed. These include ferroelectric materials,6-7 insulating polymer electrets,8 floating gates and tunneling dielectrics based on a self-assembled monolayer9-10 and polymer films embedded with metal nanoparticles (nano-floating gates).11-13 However, the operating voltages for typical NvTMs based on these gate dielectrics have been generally high (>10 V).14-21 Other devices demonstrating sub-10 V operation require meticulous processes for fabrication.16-20,

22

To develop low-cost, portable electronic devices driven with

thin-film batteries, alternative low-voltage operating memory gate dielectrics that can be prepared through cost-effective processes are highly sought. Electrolytes with a huge specific capacitance (> 1 µF/cm2) can be employed as the gate dielectric of transistors, which allows for a reduction in the device operating voltage. These materials are also highly suitable in low cost, printed electronics since they can be processed in solution. Moreover, the performance of electrolyte-gated devices is less sensitive to the variation in the thickness of the electrolyte, and an equivalent device performance is often achieved even when the alignment of the gate electrode has not been rigorously carried out.23 These unique features allow processing materials using less sophisticated fabrication methods. Depending on the trajectory of the ions in the electrolyte under a gate bias, electrolyte-gated transistors can be classified into two categories: the electrical double layer transistors (EDLTs) and the electrochemical transistors (ECTs).24-25 EDLTs rely on a nanometer-thick EDL formed at the electrolyte-semiconductor interface.26 Meanwhile, ECTs operate through electrochemical doping processes of the channel (oxidation or reduction of the semiconductor layer), especially when the semiconductor layer is permeable to the ions. In either case, the resulting operating voltage is typically less than 10 V.27 Despite the great advantages in the materials, electrolytes have been 2 ACS Paragon Plus Environment

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rarely exploited to serve as a functional gate dielectric layer for NvTMs, and efforts have been just recently initiated. Park et al.28 demonstrated the use of a gate dielectric layer based on a polymer thin film added with an ionic liquid to operate NvTMs. Even under a low programming voltage (< 10 V), the ions included in the polymer gate dielectric could migrate in reponse to the gate field. The ions eventually became trapped at the dielectric/semiconductor interface and resulted in a change in the electrical signal of the device. The resulting programmed signal was retained as long as the ions were trapped at the interface. Kang et al.29 also demonstrated the use of an ion gel electrolyte as the gate dielectric layer for functioning a memory device at a low voltage. Similar to the operation of an ECT, the signal programming was carried out based on electrochemical doping; ions driven into the polymer semiconductor layer under Vprog caused a change in the doping level of the polymer layer and the corresponding variation in the electrical signal of the device, and these were retained as long as the ions reside within the polymer semiconductor layer. However, we point out that the programmed signals for both types of devices could not be retained for a sufficiently long period of time (< 104 sec) because holding the programmed state in these devices relies on a residence of the ions trapped at the interface or at the bulk of the polymer semiconductor film, which tends to diffuse out in the absence of the gate field. We herein demonstrate an alternative approach to exploit electrolytes to operate NvTMs at low voltages based on EDL formation. The operation of the device resembles that of EDLTs but also involves additional charge storage/release processes at the electrolyte-semiconductor interface. For this additional functionality, metal nanoparticles (NPs) were inserted between the electrolyte and the channel layer by either direct thermal evaporation or using colloidal processes. Between the two methods, the memory devices based on colloidal NPs exhibited enhanced memory performance compared to those based on directly evaporated NPs. This can be attributed to ligands on a colloidal NP surface that can act as the tunneling dielectric between the floating NPs and the channel. Consequently, sub-10 V operating NvTMs with good memory properties could be demonstrated using an ion gel electrolyte and Au NPs on sol-gel processed indiumgallium-zinc-oxide (IGZO) thin films. The current ratio between the programmed and erased signals was larger than three orders of magnitude and could be held for 104 seconds. The costeffective approach presented here should provide novel memory device architectures to develop portable, flexible electronics. 3 ACS Paragon Plus Environment


EXPERIMENTAL SECTION Chemicals. 2-Methyoxyethanol (2-Me, 99%), indium nitrate hydrate (In(NO3)3∙xH2O, 99.999%), gallium nitrate hydrate (Ga(NO3)3∙xH2O, 99.999%), zinc nitrate hydrate (Zn(NO3)2∙xH2O, 99.999%), ammonium hydroxide (NH4OH, 28.0% NH3 in water, 99.99%), acetylacetone (AcAc, 99%), tetrachloroauric acid (HAuCl4·xH2O, 99.999%), oleylamine (OAm, > 70%), toluene (99.9%) and methanol (99.8%) were purchased from Sigma-Aldrich. The chemicals were used as received without further purification. Synthesis of Au NPs. Colloidal Au NPs were prepared by a modified method from Hiramatsu et al.30 in nitrogen environment. Au precursor solution was prepared by adding 0.15 mmol (50 mg) of HAuCl4·xH2O into 1.2 mL of OAm and 1.0 mL of toluene followed by sonication for 5 min. Separately, 2.9 mL of OAm and 15 mL of toluene were placed in a three-necked flask and the mixture was heated to 117°C until boiling. The Au precursor solution was then swiftly injected into the boiling mixture, and the reaction proceeded at 110°C for 2 hr. Afterwards, the reaction mixture was quickly cooled to room temperature and purified by centrifugation using methanol, as a non-solvent, and chloroform, as a good solvent. The final Au NP solution was stored in toluene. The average diameter of Au NPs was 12 ± 2.0 nm. To prepared Au NPs wither smaller diameters (9.0 ± 1.2 nm and 5.6 ± 0.9 nm) the particle growth was proceeded at lower temperatures. Device Fabrication. Heavily n-doped Si wafers with a thermally grown SiO2 layer (thickness = 3000 Å) were used as the substrate for the devices. The wafers were sonicated subsequently in acetone, isopropanol, and deionized water baths for 10 min, respectively, and were then exposed to O2 plasma for 10 min before use. The IGZO film was prepared through a sol-gel process developed by Rim et al.31 First, a 0.1 M solution of IGZO precursors in 2-Me was prepared. The precursor solution was prepared by dissolving 225.6 mg of In(NO3)3∙xH2O, 21.3 mg of Ga(NO3)3∙xH2O, and 31.5 mg of Zn(NO3)2∙xH2O in 10 mL of 2-ME. The molar ratio of In:Ga:Zn was designed to be 9:1:2. 70 µL of NH4OH (28.0% NH3 in water) and 20 µL of AcAc, which initiated the sol-gel process of the precursors under illumination with UV, and these were also added into the solution. The solution was stirred vigorously for 12 hours at room temperature and then went through a PTFE filter. The well-mixed precursor solution was spin-coated (3000 rpm, 4 ACS Paragon Plus Environment

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30 sec) onto the pre-cleaned wafers, and then the wafers were annealed at 100ºC for 1 min to remove any residual solvents. The sol-gel conversion proceeded by placing the film under a UV lamp (wavelength = 254 nm, power = 28 W/cm2) through a shadow mask for 10 min under an N2 atmosphere. The unexposed area was removed by dipping the wafers in a mixture of methanol (20 mL) and acetic acid (1 mL) for 10 sec. The remaining photo-patterned IGZO thin film patterns were rinsed with deionized water. On top of the IGZO thin film, Al source/drain electrodes (40 nm) were thermally evaporated at a deposition rate of 0.4 Å/sec through a shadow mask. The width (W) and length (L) of the channel were 1 mm and 100 µm, respectively. Au was thermally evaporated onto the IGZO film at a rate of 0.1 Å/sec. Dewetting of Au onto the IGZO surface led to the formation of isolated Au NPs as long as the nominal thickness estimated from the quartz crystal microbalance in the thermal evaporator remained below 3 nm (a continuous thin film formed when Au was deposited for more than 4 nm in nominal thickness). Alternatively, colloidal Au NPs with OAm ligands (1, 3, 5, and 20 mg/mL in toluene) could be spin-coated (2000 rpm, 60 sec) onto the IGZO to form the charge trapping layer. To apply the ion gel, a mixture of 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ([EMIM][TFSI]) ionic liquid and poly(styrene-b-methyl methacrylate-b-styrene) tri-block copolymer (5k-75k-5k, PDI =1.3) in ethyl acetate (wt% 1:9:22) was spin coated (2000 rpm, 60 sec) onto the film. While baking the film at 80 ºC for 1 hr, the self-assembly of a tri-block copolymer in an ionic liquid led physically-cross linked network to yield ion gel. Finally, Ag paste was gently applied onto the ion gel to form the top Ag electrode. NvTM Measurements. The current-voltage characteristics of the prepared NvTMs were obtained under a vacuum ( 4 nm, a continuous thin film was formed, which is not the morphology we desired. Scanning electron microscope (SEM) images in Figure 1b show the IGZO films decorated with Au NPs of nT = 1 and 3 nm, respectively. The average diameter of the Au NPs and their areal coverage were 4.2 ± 0.9 nm and 65 %, respectively, for nT = 1 nm and were 8.9 ± 2.4 nm and 80%, respectively, for nT = 3 nm. An alternative method to deposit colloidal Au NPs will be described below. Subsequently, ion gel comprising 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ([EMIM][TFSI]) ionic liquid was patterned onto device channel. The gel formation was attained by physical crosslinking poly(styrene-b-methyl methacrylate-b-styrene) tri-block copolymer that was added along with the ionic liquid. Finally, Ag paste was gently applied onto the ion gel to form the top gate electrode. We note that the location of the Ag gate electrode could be offset from the channel owing to the unique long-range polarizability of mobile ions in electrolyte.33 Figure 2a shows a series of transfer characteristics, the drain current (ID) vs. gate voltage (VG) relations collected at a fixed drain voltage (VD = 1.5 V), for a device containing Au NPs (nT = 1 nm). The black curve in the figure is the one obtained before executing any signal programming processes. ID increases when a more positive VG is applied, which corresponds to the n-channel behavior of the electrolyte-gated IGZO film. The [EMIM] cations and the [TFSI] anions in the ion gel serve as active elements of the gate dielectric that forms the EDL under the gate bias. Since the as-prepared IGZO films would be hardly permeable to ions in the electrolyte, these transistors follow the operation of an EDLT rather than that of an ECT. The colored curves in the figure are those obtained right after applying either a positive or a negative voltage to the gate electrode for 1 ms, and an application of negative voltages shifted the transfer characteristics negatively. This process is termed as the programming process of a memory device, and the voltage that is shortly applied for programming is defined as Vprog. Meanwhile, applying a short positive voltage to the gate shifts the curves positively. This process is termed as the erasing process, and this voltage is defined as Vera. 6 ACS Paragon Plus Environment

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The negative shift in the transfer characteristic after applying Vprog can be attributed to the positive space charge that formed on top of the IGZO channel based on the holes trapped in the Au NPs. The hole trapping can be understood in terms of the energy alignment between the IGZO and Au NPs (Figure 2b). Since the work function of Au (5.1 eV) lies below that of the IGZO (4.5 eV),34 the energy levels for IGZO must be bent upward when the two materials are in contact. While the resulting built-in potential prevents an injection of the electrons from the conduction band of IGZO to the Au NP, it forms a favorable energy structure that facilitates transfer of free holes from the valence band of IGZO to Au. When a negative Vprog is applied to the gate, any holes induced by the gate-driven anions at the IGZO/Au interface would be pushed into the Au NPs along the favorable energy tilt. The resulting positive space charges located in the vicinity of the IGZO channel generate an additional gate field that helps inducing electrons in the IGZO during the subsequent transfer characteristic measurements. Consequently, the turn-on of the n-type transistor occurs at lower gate voltages, and the transfer curves shift negatively. Note that the transfer curves should not shift negatively, if the device operation follows the processes described in previous reports, including trapping the anions at the ion gel/IGZO interface28 or trapping the anions in the bulk of the semiconductor channel under a negative Vprog.29 According to these previous models, applying a negative Vprog yields a positive shift in the transfer curve, which is completely opposite from what has been observed. Therefore, we claim that our devices operate in a manner that is totally different to the previous electrolyte-driven memory devices. When a positive Vera is applied to the programmed device, the transfer characteristics shift positively. This positive shift can be also understood based on the change in the energy alignment under different biases (Figure 2b). When a positive Vera is shortly applied, the cations ([EMIM]) in the ion gel would form an EDL and induce electrons at the ion gel/IGZO interface. The increase in the Fermi level of the IGZO will lower the height of the energy barrier and eventually form a favorable energy alignment allowing the electron injection into Au NPs. As the electrons are injected into the Au NPs, the programming effect that arises from the trapped holes in the Au NPs would be negated. Consequently, the programmed transfer characteristics will recover their original position. We comment that the polarity to program and erase the voltages is critical to attain a larger signal ratio between the programmed and erased states of the memory device (Iprog/Iera), which is typically measured at VG = 0 V after conducting programming and erasing processes. In 7 ACS Paragon Plus Environment


fact, it is also possible to program the device with a positive Vprog and erase the signal with a negative Vera (Figure S1). Of course, the same operating principle above should still be applied to describe the resulting shift in the curve. If a positive voltage is applied shortly to program a device, the electrons would be injected into the Au NPs, and the transfer characteristics measured after the programming step will shift positively. When a negative voltage is applied to this programmed device shortly, holes will now be injected into the Au NPs and negate the negative charges in the Au NPs. However, a large Iprog/Iera ratio cannot be attained by applying a positive programming voltage and a negative erasing voltage on our normally-off n-channel transistor. This is because our devices remain in the off-state at VG = 0 V both after applying Vprog (the turnon voltage of the device will shift positively from its original position and thus the device at VG = 0 V would be in its off-state: the red curve in Figure S1a) and after applying Vera (the turn-on voltage of the device will now shift negatively but the device at VG = 0 V would still be in its offstate: the blue curve in Figure S1a). To obtain a large Iprog/Iera ratio, the transistor channel at VG = 0 V after applying Vprog should be in the on-state while that after applying Vera should be in the off-state, or vise and versa. For our normally-off n-type transistor operating in the accumulation mode, such a condition is met when Vprog shifts the curve negatively and shifts the device turn-on voltage to a negative value, while Vera brings this curve positively and shifts the device turn-on voltage back to a positive value. Therefore, all the programming and erasing processes in this study were conducted with negative Vprogs and positive Veras, respectively. The shift in the transfer characteristic was found to depend on the magnitude of the Vprog and Vera applied to the device. Figure 2c summarizes the Vprog/Vera-dependent shift of the transfer characteristics defined as the memory window (the memory window is estimated based on the voltages yielding ID = 10-7 A at the programmed and erased states of the device). The magnitude of Vprog and Vera had to be larger than 3 V to yield a noticeable shift in the transfer characteristics. The voltage-dependence can be understood from the number of charges that were induced at the ion gel/IGZO interface that was eventually transferred into the Au NPs. Because the induced charge density in the IGZO layer scales with the applied gate voltage, a larger shift should be obtained after the devices were programmed or erased with larger voltages. The values are consistently larger than those attained from control IGZO transistors without any Au NPs to store holes (Figure S2). The application of Vprog/Vera = ±9 V yielded a memory window (at ID = 10-7 A) as large as 0.88 ± 0.09 V in the presence of Au NPs (nT = 1nm), which is larger than 0.33 ± 0.09 V obtained from the control device. The application of Vprog/Veras larger than 10 V degraded the 8 ACS Paragon Plus Environment

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transistor performance, perhaps due to the undesired charge transfer reactions involving electrochemical species in the electrolyte at such high electrode potentials. Both the negative and positive shifts of the transfer characteristics in response to Vprog and Vera were more pronounced as the nT of the Au NPs increased. This increase can be first attributed to the increase in the areal coverage of the Au NPs on the IGZO surface. The areal coverage was 65% for nT = 1 nm and 80% respectively for nT = 3 nm. The presence of more NPs would help storing a greater amount of charges under the given program/erasing voltages. We comment, however, that simply maximizing the areal coverage of Au NPs would not necessarily result in the maximal charge storage in NPs and the largest shift in the transfer characteristics because a free surface on the IGZO, capable of making direct contact with the ion gel, is also required to induce the charges in the channel. The second contribution to explain the enhanced shift in the transfer characteristics for the devices with nT = 3 nm is the energy necessary to inject a charge into the Au NP, which is also known as the charging energy (EC). Within the first order approximation, the EC of a metallic sphere is equal to e2/(4πεrε0D),35 where e is the element charge, εr is the dielectric constant of the surrounding medium (the electrolyte in our case),36 ε0 is the vacuum permitivitty, and D is the diameter of the sphere. Because Au NPs with a larger diameter require smaller energy for charging (EC = 28 meV for nT = 1 nm (D = 4.2 nm) and 13 meV for nT = 3 nm (D = 8.9 nm)), more holes would be able to charge Au NPs under the same programming condition. A larger shift in the I-V characteristics for transistor memories with a larger nano-floating gate dielectric has been observed from other systems as well.37 Figure 2d displays series of transfer characteristics taken after applying Vprog and Vera to the gate for IGZO thin film NvTMs with larger Au NPs (nT = 3 nm). The memory window (at ID = 10-7 A) at Vprog/Vera = ±9 V was 1.32 ± 0.19 V for these devices, which was only 0.88 ± 0.09 V for those with nT = 1 nm. Due to the larger shift, the Iprog/Iera ratio increased with an increase in the Au NPs density (Figure 2e). The resulting Iprog/Iera ratio of the devices with nT = 3 nm was as large as 3.6 (± 1.6) x 103 when Vprog/Vera = ±9 V was applied, which is larger than 1.6 (± 0.6) x 102 for devices with nT = 1 nm under the same measurement condition. Overall, both i) the larger areal coverage of Au NPs providing a greater number of trapping sites between the IGZO and ion gel and ii) the smaller energy needed to insert a charge in the NPs contributed to an improvement in the memory characteristics of the devices operated via electrolyte-gating. The retention characteristic of the device is another important aspect to evaluate the memory performance. This is typically attained by monitoring Iprog (or Iera) at VG = 0 over a 9 ACS Paragon Plus Environment


period of time after a device is programmed (or erased). Figure 2f displays the retention characteristics of the programmed and erased signals obtained from IGZO NvTMs that contain different Au NPs densities (nT = 1 and 3 nm, respectively). The Iprog/Iera ratio for both devices could be retained for up to 103 sec for both devices. After 103 sec, however, Iprog was reduced and Iera increased gradually. The gradual reduction in the Iprog/Iera ratio is attributed to a relaxation in the holes trapped in the Au NPs over time. Thus, strategies to extend these characteristics were sought. To address this issue, an alternative form of Au NPs was applied onto the IGZO surface. Instead of directly depositing Au via thermal evaporation, we separately prepared Au NPs with different diameters (D = 12 ± 2.0 nm, 9.0 ± 1.2 nm, and 5.6 ± 0.9 nm), through colloidal synthesis.30 All the resulting Au NPs were coated with short oleylamine molecules (Figure 3a) that were also referred to as ligands, and they could be deposited onto the IGZO channel through simple solution casting methods, such as spin-coating. The remaining device fabrication processes were the same as that described above. The presence of the ligands on the colloidal Au NPs is expected to have a significant difference on the resulting devices when compared to those made via direct evaporation. The ligand molecules serve as a nano-scale tunneling gate-dielectric layer of the Au NP core and IGZO channel in the memory device, which did not exist in the device made by direct evaporation of gold. The tunneling gate dielectric between the channel layer and the charge trapping layer retards the charge transfer from the Au NPs back to the IGZO channel, and thus should enhance holding the programmed/erased signals for a longer duration (Figure 3b). Figure 3c displays SEM images of an IGZO surface coated with 12 nm Au NPs from different concentrations of colloidal dispersion (5 and 20 mg/mL in toluene, respectively). Due to the hydrophobic nature of the ligand molecules, the Au NPs were dewetted on the IGZO surface (the areal coverage of the 12 nm Au NPs prepared from 5 mg/mL and 20 mg/mL solutions were 32% and 49%, respectively), instead of achieving continuous coverage, and the area covered with the dewetted Au NPs increased when colloidal dispersion with higher concentration was used. Figure 4a displays a series of transfer characteristics for the resulting IGZO NvTMs inserted with 12 nm colloidal Au NPs (5 mg/mL) obtained after applying Vprogs or Veras. Consistent with previous results, the transfer characteristics shifted negatively after being shortly applied with negative Vprog. The negative shift could be attributed to trapping the holes, as discussed above. When the programmed devices were applied with positive Veras, the transfer 10 ACS Paragon Plus Environment

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characteristics shifted positively towards their original position. This positive shift can be understood from the negation of holes by electrons induced into the Au NPs during the erasing process. Despite the lower coverage of the ligated Au NPs compared to that of directly evaporated bare Au NPs, the average memory window (at ID = 10-7 A) at equivalent programming/erasing conditions was comparable. This can be understood from the size of the colloidal Au NPs. As discussed above, the charging energy of the Au NPs scales inversely with their diameter. For Au NPs with D = 12 nm, EC = 10 meV. Thus, employing larger NPs allows one to store charges efficiently at lower voltages and to program and erase the signals effectively. To verify this, memory devices with different sized colloidal Au NPs were assembled (the coverage of the NPs was held between 20~40%) and their I-V characteristics were examined (Figure S3). Figure 4b summarizes the memory margin obtained from these devices operated at Vprog/Vera = ±9 V. The summary clearly shows that using smaller Au NPs (with larger EC) results in the memory devices with a smaller margin; EC = 13 meV and 21 meV for Au NPs with D = 9.0 nm and 5.6 nm, respectively. The loading of NPs on IGZO channel also plays an important role in enhancing the device characteristics. Figure 4c summarizes the memory window (at ID = 10-7 A) obtained at Vprog/Vera = ±9 V as a function of the concentration of colloidal dispersion used to form the Au NPs layer (D = 12 nm). Consistent with the explanation above, increasing the areal coverage of Au NPs on IGZO helps storing more charges. Therefore, the NvTMs coated with 20 mg/mL dispersion of 12 nm Au NPs yielded a memory window (at ID = 10-7 A) as large as 1.77 V (±0.23 V). Here, we comment that the duration of the programming/erasing voltages could also expend the memory window. The inset of the figure plots the memory windows (at ID = 10-7 A) for IGZO NvTMs inserted with colloidal 12 nm Au NPs (5 mg/mL) as a function of the duration time for the programming/erasing voltages (= ±9 V) applied to the device, clearly showing that applying Vprogs or Veras for a longer time yields a larger memory window. This enhancement can be understood from the enlarged number of holes trapped/detrapped in the Au NPs when the programming/erasing voltages are applied over a longer period of time. However, the devices operated with programming/erasing voltages over a longer duration are often irreversibly degraded. This can be understood in terms of the undesired Faradaic processes occurring at the ion gel/IGZO interface, which would become more serious when higher voltages are applied for a longer time. To reliably measure different devices in this study, therefore, the duration time for the programming/erasing voltages was fixed at 1 ms. Figure 4d shows the resulting Iprog/Iera ratio of the NvTMs with different contents of colloidal Au NPs. Consistent with larger memory 11 ACS Paragon Plus Environment


window, the Iprog/Iera values were enhanced as a greater number of colloidal Au NPs covered the IGZO film. Consequently, Iprog/Iera as large as 3.6 (± 2.9) x 103 could be obtained from NvTMs made with a 20 mg/mL Au NPs dispersion. More importantly, due to the role of the insulating organic ligands inserted between the IGZO channel and the Au NPs layer, the retention characteristics of the memories were enhanced compared to those with NPs prepared from thermal evaporation. Figure 4e shows the retention characteristics of the programmed and erased signals for IGZO NvTMs prepared with colloidal Au NPs (5 mg/mL). The initial Iprog/Iera ratio larger than 103 could be preserved for longer than 105 sec at sub-10 V programming and erasing voltages. Finally, the consistency of the device signal upon consecutive programming and erasing processes was confirmed. Figure 4f displays a series of transfer characteristics for an IGZO NvTM prepared with colloidal 12 nm Au NPs (5 mg/mL) that were obtained between consecutive applications of Vprog and Vera (duration time = 1 ms). It was found that the series of curves shifts positively upon multiple applications of programming/erasing cycles, especially when Vprog and Vera with the same magnitude were applied. This is perhaps because the injection of induced holes into the Au NPs cannot be done comparably to the injection of induced electrons to negate the space charge in Au NPs when using IGZO layer as the channel, as the majority carrier for the n-type IGZO layer is electron. To examine the consistency of the electrical signal, therefore, Vera (= 6.5 V) with a magnitude smaller than that of Vprog (= -8.5 V) was applied. Optimized operation condition needs be found, but the results still confirm that both the programmed and erased current levels at VG = 0 V could be retained over multiple cycles of programming and erasing (see the inset, which displays the current levels at VG = 0 V for the transfer characteristics obtained during the cycling test).

CONCLUSION In conclusion, we demonstrate the utility of highly capacitive EDL for operating NvTM at low voltages below 10 V, which is critical to realize portable electronic devices. In particular, this was achieved by inserting Au NPs between the IGZO channel and ion gel electrolyte so that the EDL formation could lead to altering the space charge near the IGZO channel. Two types of Au NPs were examined: one obtained via direct thermal evaporation onto a hydrophilic IZGO surface and the other obtained from separate colloidal synthesis. For both cases, an enlarged coverage of the Au NPs on the IGZO improved the Iprog/Iera ratio of the device systematically. 12 ACS Paragon Plus Environment

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The significance of the nanoparticle size leading to lower the charging energy was also confirmed. Moreover, the presence of insulating organic ligands on the Au NPs enhanced the retention properties of the memory devices, as they could act equivalent to a tunneling gate dielectric in conventional flash memory devices. Consequently, IGZO NvTMs yield a Iprog/Iera ratio larger than 103 at programming and erasing voltages lower than 10 V, and this margin could be retained for longer than 105 sec. We anticipate that the Iprog/Iera ratio can be further improved by optimizing the turn-on voltage and lowering the off-state of the transistor. Moreover, it provides new guidelines to design an advanced device architecture and functional materials in non-volatile memory devices.

ASSOCIATED CONTENT The Supporting Information is available free of charge via the Internet at http://pubs.acs.org. ; Transfer characteristic of ion gel gated IGZO NvTMs. AUTHOR INFORMATION Corresponding Author *

E-mail: Moon Sung Kang ([email protected])

Acknowledgements This work is supported by the Technology Innovation Program (10051665) funded by the Ministry of Trade, Industry & Energy, Korea and the Korea Display Research Corporation (KDRC) for the development of future devices technology for display industry.

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Figure 1 (a) Schematic description of the device fabrication and schematic cross section of the memory device with thermally evaporated Au NPs. (b) SEM images of IGZO film decorated with Au NPs (nT = 1 and 3 nm).



Figure 2 (a) Transfer characteristics at VD = 1.5 V for an ion gel-gated IGZO NvTM containing Au NPs (nT = 1 nm) that were applied with different Vprogs and Veras. The duration time for Vprogs and Veras was 1 ms. (b) Schematic description of signal programming and erasing processes and associated energy diagram of the Au NP/IGZO interface. (c) Summary of the voltage shift in the transfer characteristics upon programming and erasing, which was extracted from the gate voltages at a current level of 10-7 A. (d) Transfer characteristics at VD = 1.5 V for an ion gel-gated IGZO NvTM containing Au NPs (nT = 3 nm) that were applied with different Vprogs and Veras. (e) Summary of the current ratio in the transfer characteristics extracted at VG = 0 V after programming and erasing the device. (f) Retention characteristics of the programmed and erased signals.


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Figure 3 (a) Schematic cross section of the memory device with colloidal Au NPs with ligands. The chemical structure of the ligand molecule, oleylamine. (b) Energy diagram of the Au NP/IGZO interface highlighting the role of ligand molecules on enhancing the retention characteristics of the memory device. (c) SEM images of IGZO films decorated with different concentrations (5 mg/mL and 20 mg/mL) of colloidal Au NPs.



Figure 4 (a) Transfer characteristics at VD = 1.5 V for an ion gel-gated IGZO NvTM prepared using 12 nm colloidal Au NPs (5 mg/mL) that were applied with different Vprogs and Veras. (b) Summary of the voltage shift in the transfer characteristics for devices containing Au NPs with different sizes (12, 9.0, and 5.6 nm) collected under a programming/erasing condition of -9 V/+9 V. The data was extracted from the gate voltages at a current level of 10-7 A. (c) Summary of the voltage shift in the transfer characteristics for devices prepared from different concentrations of 12 nm colloidal NP dispersion collected under a programming/erasing condition of -9 V/+9 V. The inset displays the summary of the voltage shift in the transfer characteristics for devices prepared using 12 nm colloidal NPs (5 mg/mL) upon programming and erasing with different duration of time. (d) Summary of the current ratio in the transfer characteristics for devices prepared from different concentrations of 12 nm colloidal Au NP dispersion that were extracted at VG = 0 V under a programming/erasing condition of -9 V/+9 V. (e) Retention characteristics of the programmed and erased signals for an ion gel-gated IGZO NvTM prepared using 12 nm colloidal Au NPs (5 mg/mL). (f) A series of transfer characteristics at VD = 1.5 V for an ion gelgated IGZO NvTM prepared using 12 nm colloidal Au NPs (5 mg/mL) that were obtained after applying multiple cycles of Vprog = -8.5 V and Vera = +6.5 V.


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ToC figure


Nonvolatile Electric Double-Layer Transistor Memory Devices

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