Nonvolatile MoTe2 p–n Diodes for Optoelectronic ... - ACS Publications

Nonvolatile MoTe2 p−n Diodes for Optoelectronic Logics Chenguang Zhu,† Xingxia Sun,† Huawei Liu, Biyuan Zheng, Xingwang Wang, Ying Liu, Muhammad Zubair, Xiao Wang, Xiaoli Zhu, Dong Li,* and Anlian Pan*

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Key Laboratory for Micro-Nano Physics and Technology of Hunan Province, College of Materials Science and Engineering, Hunan University, Changsha 410082, People’s Republic of China S Supporting Information *

ABSTRACT: Construction of atomically thin p−n junctions helps to build highly compact electronic and photonic devices for on-chip optoelectronic applications. In this work, lateral nonvolatile MoTe2 p−n diodes are constructed on the basis of the MoTe2/h-BN/ graphene semifloating gate field-effect transistor (SFG-FET) configuration. The achieved diodes exhibit excellent rectifying behaviors (rectification ratio up to 8 × 103) and typical photovoltaic properties (with power conversion efficiency of 0.5%). Through manipulating the polarity of the stored charges in the semifloating gate, such rectifying behaviors and photovoltaic properties can be erased, resulting in a high conduction state (n+−n junction). Such erasable and programmable behaviors further enable us to develop logic optoelectronic devices, realizing the switching of the device between different power conversion states and functional AND and OR optical logic gates. We believe that the achieved MoTe2-based SFG-FET devices with interesting logic optoelectronic functions will enrich the modern photoelectrical interconnected circuits. KEYWORDS: MoTe2, van der Waals heterostructure, p−n diode, nonvolatile memory, logic optoelectronic device he emergence of two-dimensional (2D) materials1,2 with dangling bond-free surfaces provides us a flexible platform, by simply stacking different 2D components into heterostructures, to construct smart devices with excellent properties and functions. Until now, a large variety of twodimensional functional devices, including tunneling transistors,3,4 memories,5−8 photodetectors,9−11 and light-emitting diodes,12−14 have been realized and shown excellent performances. Moreover, different from bulk crystals, the atomically thin properties enable the charge carrier density and even polarity in 2D materials to be easily manipulated,15−20 which expands the avenue toward flexibly designing and manipulating the device functions. In this way, through controlling the applied outer electric field, multifunctional high-performance heterostructures have been constructed and investigated. For example, Huang et al.21 reported the BP/MoS2 heterostructures, which can not only be used as p−n junctions for rectifiers but also as tunable multivalue inverters and type-tunable diodes. Cheng et al.22 demonstrated multifunctional MoTe2−MoS2/h-BN/graphene heterostructures, which can function as both programmable rectifiers and photovoltaic devices. The p−n junction, composed of two semiconductors with opposite doping polarity, can be easily achieved in 2D systems and potentially used in various photoelectrical applications.23−28 Logic optoelectronic applications,29 which can be potentially

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used in photoelectrical interconnection circuits, have not been deeply investigated yet. In this work, we report construction of SFG-FET devices by designing MoTe2/h-BN/graphene heterostructures. We show that, by dynamically engineering the stored charges in the semifloating gate, the device can be programed and switched between the p−n junction state and n+−n junction state and thus be capable of operating as multimode storage. While under light irradiation, the device possesses different power conversion states (high or low) at different working states (p−n junction state or n+−n junction state), which enable us to develop logic optoelectronic devices, realizing the switching of the device between different power conversion states. Moreover, functional AND and OR optical logic gates have also been demonstrated. We believe that the achieved MoTe2-based SFGFET devices with interesting logic optoelectronic functions will enrich the modern photoelectrical interconnected circuits.

RESULTS AND DISCUSSION The device configuration is schematically demonstrated in Figure 1a. A few-layer graphene flake is first achieved with a peelReceived: April 11, 2019 Accepted: May 31, 2019 Published: May 31, 2019 7216

DOI: 10.1021/acsnano.9b02817 ACS Nano 2019, 13, 7216−7222

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Figure 1. Device structure and basic characterizations. (a) Schematic illustration of the FET, FG-FET, and SFG-FET architecture. (b) Optical image of a typical as fabricated MoTe2/h-BN/graphene heterostructure-based device. (c) Raman spectra of graphene, h-BN, MoTe2, and their heterostructure excited by 514 nm lasers. (d) Transfer characteristics and output curves (inset) of MoTe2 FET (drain: E3, source: E4 and gate: Si).

Figure 2. Electrical characterizations of the FG-FET and SFG-FET. (a) Transfer characteristic curves of the FG-FET at different drain bias (drain: E1, source: E2 and control gate: Si). (b) Transfer characteristic curves of the SFG-FET at different drain bias (drain: E2, source: E3 and control gate: Si). (c) Output curves of the SFG-FET device after different control gate voltage pulses. (d) Semilogarithmic plots of the output curve of the SFG-FET at the p−n junction state, with the fit curve in red. Operation diagrams of the SFG-FET device (e) with positive control gate voltage applied on the device and (f) with the applied control gate voltage released. (g) Band diagrams of the SFG-FET device at the p−n junction state.

off method on a SiO2/Si substrate, and then an h-BN flake and a MoTe2 flake are exfoliated and stacked on the graphene layer by

layer. E-beam lithography (EBL) is finally employed to define Au/Cr electrodes on the obtained heterostructures. Figure 1b 7217

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retention behaviors (Figure S4). Such drain bias directiondependent memory behaviors will enable the SFG-FET devices to be applicable for multimode storage applications. The drain bias direction-dependent memory behaviors can also be reflected by the output characteristics shown in Figure 2c,d and be understood by the operation diagram shown in Figure 2e,f and Figure S5. We first check the operation mechanism of the SFG-FET device. When a positive gate voltage (+30 V) is applied on the silicon, electrons would be accumulated in the MoTe2 flake due to the field effect (Figure 2e). It is to be understood that there is a positive potential between the graphene and the MoTe2 at this condition, which would make the accumulated electrons tunnel from the MoTe2 to the graphene. After the positive control gate voltage released (reset at 0 V), the accumulated electrons in the MoTe2 would also disappear. However, the tunneled electrons are still trapped in the graphene due to the potential barrier of h-BN. Under this situation, the trapped electrons in the graphene layer would induce holes in the part of the MoTe2 over the graphene, leading to the part of the MoTe2 over the graphene p-doped (Figure 2f). As we discussed in Figure 1d, MoTe2 is intrinsically n-doped. In this way, p−n junction is formed along the MoTe2 flake, resulting in the evident rectifying behaviors (rectifying ratio up to 8.7 × 103) observed in the Figure 2c (band diagram is shown in Figure 2g). In this situation, if we make the graphene layer grounded, the trapped holes in the graphene would flow away. Thus, the heterostructures would recover to the state before the positive voltage pulse applied on the silicon control gate (Figure S6). On the contrary, if a −30 V VCG‑pulse is applied, holes would be accumulated in the MoTe2 flake. Driven by the electrical field, the holes will tunnel through the h-BN layer and thus store in the bottom graphene. After the control gate voltage is removed, the accumulated holes will further produce mirror imaged electrons in the MoTe2 channel, resulting in the formation of n+−n junction (high conduction state) in the channel (Figure 2c). Compared with the p−n junction state (rectifying ratio exceeding to 8.7 × 103), the device at the n+−n junction state shows a fairly low rectifying ratio of 1.5 (Figure S7), which can reasonably be attributed to the small Fermi-level offset between the two parts of MoTe2 (n+-doped region and the undoped region). In this way, the multimode memory behaviors observed in Figure 2b and the output characteristic in Figure 2c is clear. The transport across a p−n junction can be fitted by the Shockley diode equation extended to include a series resistance (Rs)27,28 É ÅÄ ij VDS + I0R S yzÑÑÑÑ nVT ÅÅÅÅ I0R S j z Ñ ID = WÅ expjj zzzÑÑÑ − I0 j R s ÅÅÅÅÇ nVT nVT k {ÑÑÖ

exhibits an optical microscopy image of a typical produced graphene/h-BN/MoTe2 device. Here, only part of the MoTe2 is aligned over the graphene flake to form FG-FET, SFG-FET, and FET device architectures in the same heterostructure. Atomic force microscopy (AFM) is employed to characterize the structure, indicating that graphene, h-BN, and MoTe2 possess thickness of 2.1, 15.7, and 9.0 nm, respectively (Figure S1). Raman spectroscopy was further performed to characterize the components and the heterojunction region. As shown in Figure 1c, typical Raman signatures of graphene (G peak at 1582 cm−1 and 2D peak at 2700 cm−1), h-BN (E2g peak at 1365 cm−1), and MoTe2 (A1g peak at 171 cm−1 and E2g1 peak at 233 cm−1)30−32 are observed in the corresponding Raman spectrum and the heterojunction region. Electrical properties of the fabricated devices are measured in a vacuum chamber of ∼10−4 Pa. Figure 1d illustrates the transfer characteristics of pure MoTe2 flake, where Si is employed as the back gate and the part between electrode E3 and E4 is the source and the drain electrode, respectively. With the gate voltage being swept from −50 to +50 V, the channel current first decreases to a minimum point at gate voltage of around −5 V and then increases gradually, showing typical n-type dominated ambipolar FET behavior with current on/off ratio exceeding 106. It also indicates that both holes and electrons can be effectively induced in the MoTe2 channel by electrostatic doping, which enables the further formation of homogeneous p−n junction along one MoTe2 flake. Further investigation reveals that the MoTe2 possesses an electron mobility of 15.9 cm2/V·s (the detailed calculation method is described in Figure S2). The inset of Figure 1d shows the output characteristics across the MoTe2 flake. The current is almost symmetric dependent on the bias voltage, indicating that the Au/Cr electrodes make good contact to the MoTe2 flake. While the bottom graphene is employed as floating gate to store charges and the Si back gate is employed as the control gate, we can flexibly program and erase the channel performances in the FG-FET and SFG-FET. We first monitor the transport properties between electrode E1 and E2 (FG-FET) while sweeping the Si control gate voltage (with drain bias voltage fixed at +0.5 V). As shown in Figure 2a, with the Si control gate voltage from −50 to +50 V, the transfer characteristic curve exhibits a large negative shift of the lowest conductance point (at −25 V) compared to the normal MoTe2 FET shown in Figure 1d (at −7 V). But while we reverse the sweeping direction from +50 to −50 V, the lowest conductance point appears at +20 V, and a pretty large hysteresis (ΔV = 45 V) is observed. To operate a memory, the device is often programmed or erased by voltage pulses and then read with a 0 V reset on the control gate. Here, due to the ambipolar transport behavior of the MoTe2 channel, the device shows a fairly low memory on/off ratio (10). When the drain bias voltage is switched to −0.5 V, the device shows similar behaviors, indicating drain bias direction-independent behaviors. We now probe the transport properties of the SFG-FET device (drain: E2, source: E3). As shown in Figure 2b, with drain bias fixed at −1 and +1 V, the device shows two distinct transfer curves, which are totally different from that shown in Figure 2a. It is clear that, when the drain bias is set at +1 V, the device shows a fairly low memory on/off ratio of 3.8, but when the drain bias value is switched to −1 V the memory on/off ratio increases to 3.6 × 104 (detailed comparison between FG-FET and SFG-FET can be found in Figure S3). The endurance investigation reveals that each state can be maintained well, showing excellent

where VT = kBT/e is the thermal voltage at temperature T. kB, e, W, I0, and n are the Boltzmann constant, electron charge, Lambert W function, reverse saturation current, and ideal factor, respectively. Figure 2d shows the semilogarithmic plot of ID as a function of VDS and the fitted result, where an ideal factor of 1.9 and a series resistance of 1.5 MΩ are obtained. It should be noted here that the series resistance is far smaller than the reverse resistance (0.1 TΩ at −0.8 V), indicating that the device possess a high-quality p−n interface, which enables the excellent cutoff performance. From the extracted ideal factor, we can deduce that the transport in the p−n junction is mostly dominated by recombination process. Upon light illumination, p−n junctions can be used to separate the photoexcited charge carriers and thus be developed 7218

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0.5 and 0.57%. This small η value can reasonably be attributed to our conservative calculation method. In a p−n junction, the active area where the photovoltaic effect occurs is the region where the built-in electrical field is generated (depletion region). In this lateral p−n junction, the depletion region should be very narrow, but we take the entire area of the MoTe2 channel for estimation. Thus, the real power conversion efficiency of the device should be larger.33 Parts b and c of Figure 3 show the photoresponse and the extracted generated electrical power of the device under different laser power irradiation. With continuously increasing the laser power, more electron−hole pairs will be generated and separated by the p−n junction, resulting in the shift of the ID−VDS curves toward more negative current values (Figure 3b) and the improved generated electrical power (Figure 3c). Further investigations indicate that both log(ISC) and VOC are linearly dependent on the incident illumination power (Figure S9), which is similar to the reported results.33 As is proven in Figures 2 and 3, both gate voltage pulse and light can be used as inputs to modulate the device performance. We first explored the dynamic behaviors of the SFG-FET device at p−n junction state by applying a periodic light irradiation on the device. As shown in Figure 4c, VOC (output) is generated immediately with the light (input) turned on and rapidly disappears with the light turned off, showing well-switched behaviors. In such a function (photodiode, schematically illustrated in Figure 4a), light is used as the input to modulate the device performance (output: VOC). Moreover, after hundreds of cycles, the device can still operate well and almost no deviation in photovoltage is observed, indicating excellent repeatability (Figure S10). In the SFG-FET device, we can also switch on and off the output (VOC) by modulating the control gate voltage pulse (input) while under continuous light irradiation (source), and we name it as logic optoelectronic device (schematically illustrated in Figure 4b). It can be understood that, with different voltage pulses (+20 or −20 V) applied, the device will be switched between p−n state and n+−n state and thus possesses different photoelectrical conversion abilities. As a result, the VOC can readily be switched well between the “on” and “off” states by manipulating the control gate voltage pulses (±20 V) (Figure 4d). We also notice that each state observed in Figure 4d is very stable (Figure S11). Based on the designed p−n junctions and their superior optoelectronic properties, we can further develop photoelectrical interconnected logic circuits. As shown in Figure 5, based on two MoTe2 p−n junctions, we constructed two types of basic logic gates (AND gate and OR gate). It should be noted here that, in these functions, light is used as the input, the generated open-circuit voltage (or short circuit current) is defined as the output, and no source supply is needed, which is totally different from the traditional concept of logic circuits demonstrated in 2D systems (typically, gate voltage is used as the input, the voltage drop is defined as the output and the drain bias voltage is employed as the source).34,35 Figure 5a demonstrates the operating diagram of the AND gate, and Figure 5b depicts the corresponding dynamic characteristics, where two MoTe2 p−n junctions are connected in series and two light beams are induced on each p−n junction as the input. We defined four states, ‘0, 0’, ‘0, 1’, ‘1, 1’, and ‘1, 0’, which correspond to the four combinations of on (‘1’) and off (‘0’) for the two independently controlled light beams. When all light beams are at off states (‘0, 0’), no photocurrent is generated in the circuit and the output is at the ‘0’ state. While only one of the light

for photovoltaic devices. We first applied a −30 V VCG‑pulse to make the SFG-FET device operate at the p−n junction state. Figure 3a shows the ID−VDS characteristics of the achieved p−n

Figure 3. Photovoltaic properties of the SFG-FET device at the p−n junction state. (a) Output characteristics of the p−n junction in dark and under light irradiation (wavelength: 450 nm, light power: 11.6 nW). (b) Output characteristics and (c) the generated electrical power of the p−n junction as a function of the incident light power.

junction in the dark and under light illumination. It is clear that, under laser irradiation (450 nm, 11.6 nW), a positive opencircuit voltage (VOC, voltage at zero current) of 0.3 V and a negative short-circuit current (ISC, current at zero voltage bias) of 0.4 nA are obtained, showing typical photovoltaic properties. Moreover, while decreasing the bandgap of channel MoTe2, larger VOC will be obtained due to the larger bandgap of MoTe2 and the derived larger built-in electrical field in the MoTe2 p−n diode (Figure S8). The inset of Figure3a shows the generated electrical power (Pel) according to the equation Pel = ID·VDS, and a maximum output electrical power (Pel·Max) of 67 pW can be obtained at VDS of 0.22 V. It means that, while operating as a photovoltaic device, the p−n junction can generate an electrical power of 67 pW at an operating voltage of 0.22 V (the incident light power is 11.6 nW). Based on the equations FF = Pel·MAX/ VOCISC and η = Pel·MAX/Pin, we can further find that the fill factor (FF) and the power conversion efficiency (η) of the device are 7219

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Figure 4. Photoresponse of the SFG-FET device. Schematic illustration of the working mechanism of (a) photodiode and (b) logic optoelectric device. (c) VOC switching behaviors of the SFG-FET device at the p−n junction state by periodically turning on and off the incident light (light power: 9.0 nW). (d) VOC switching behaviors of the SFG-FET device by manipulating the control gate voltage pulse under a continuous light irradiation (light power: 9.0 nW).

Figure 5. Light-triggered logic gates. (a) Schematic illustration of the AND gate, where the two p−n junctions are connected in series, two independent light sources induced on the two p−n junctions are used as input, and the generated current in the circuit is the output. (b) Measured output currents for the four input states. (c) Schematic illustration of the OR gate, where the two p−n junctions are connected in parallel and the generated voltage in the circuit is the output. (d) Measured output voltage for the four input states. The incident light power is 9.0 nW.

current flow in the circuit will be blocked and remains very small (output: ‘0’ state). While both of the light beams are turned on (‘1, 1’), photocurrent will be generated in both MoTe2 p−n

beams is turned on (‘0, 1’ or ‘1, 0’), photocurrent will be generated in the corresponding MoTe2 p−n junction. But due to the large reverse resistance of another MoTe2 p−n junction, the 7220

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ACS Nano junctions. As a result, a large current flow (0.38 nA) will be collected in the circuit and the output will be switched to the ‘1’ state. We then connected the two p−n junctions in parallel and collected the generated voltage in the circuit as the output. As shown in Figure 5c,d, when both light beams are at off states (‘0, 0’), no photovoltage is generated in the circuit and the output is at the ‘0’ state. While only one of the light beams is turned on (‘0, 1’ or ‘1, 0’), photovoltage will be generated in the corresponding MoTe2 p−n junction. Because the two p−n junctions are connected in parallel, regardless of the zero output of the other MoTe2 p−n junction we will collect a large output voltage (0.26 V). When both of the light beams are turned on (‘1, 1’), photovoltage will be generated in both MoTe2 p−n junctions. Because the two p−n junctions are connected in parallel, a similar output voltage is obtained. That is to say, if one or both the inputs are high (‘1’), the output is at ‘1’ state. If neither input is high, a low output (‘0’) is obtained. Taken together, the strong photovoltaic properties obtained in MoTe2 p−n junctions enables the successful demonstration of various logic gates.

ASSOCIATED CONTENT S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsnano.9b02817. AFM characterization, memory behavior, charge retention, operation diagram, transport behavior, rectifying behavior, thin MoTe2-based SFG-FET, photoresponse, photoresponse repeatability, and photoresponse stability (Figures S1−S11) (PDF)

AUTHOR INFORMATION Corresponding Authors

*E-mail: [email protected]. *E-mail: [email protected]. ORCID

Xiao Wang: 0000-0002-2973-8215 Dong Li: 0000-0003-0391-7060 Anlian Pan: 0000-0003-3335-3067 Author Contributions †

C.Z. and X.S. contributed equally to this work.

CONCLUSIONS

Notes

The authors declare no competing financial interest.

In summary, we have successfully realized nonvolatile programmable MoTe2 p−n junctions in the designed SFG-FET devices. The p−n junctions exhibit excellent rectifying behaviors with a rectification ratio exceeding 8.7 × 103 over a small voltage range (−0.8 to +0.8 V). Upon light irradiation, the p−n junctions exhibit typical photovoltaic behaviors with an open-circuit voltage of 0.3 V, short circuit current of 0.4 nA, and power conversion efficiency of 0.57% at incident power of 11.6 nW. On the basis of the type-tunable properties of the SFG-FET, we developed a logic optoelectronic device that can realize the switching of the power conversion state between “on” and “off” by manipulating the control gate voltage pulses. Moreover, functional AND and OR optical logic gates have also been demonstrated in this system. We believe that the achieved MoTe2-based SFG-FET devices with interesting logic optoelectronic functions will enrich the modern photoelectrical interconnected circuits.

ACKNOWLEDGMENTS The authors are grateful to the National Natural Science Foundation of China (Nos. 51525202, 51772084, 61574054, 61505051, 61474040, 61635001), Innovation platform and talent plan of Hunan Province (2017RS3027), the Program for Youth Leading Talent and Science and Technology Innovation of Ministry of Science and Technology of China, the Aid Program for Science and Technology Innovative Research Team in Higher Educational Institutions of Hunan Province, Joint Research Fund for Overseas Chinese, Hong Kong and Macau Scholars of the National Natural Science Foundation of China (No. 61528403), and the Foundation for Innovative Research Groups of NSFC (Grant No. 21521063). REFERENCES (1) Novoselov, K. S.; Geim, A. K.; Morozov, S.; Jiang, D.; Zhang, Y.; Dubonos, S. a.; Grigorieva, I.; Firsov, A. Electric Field Effect in Atomically Thin Carbon Films. Science 2004, 306, 666−669. (2) Novoselov, K. S.; Jiang, D.; Schedin, F.; Booth, T. J.; Khotkevich, V. V.; Morozov, S. V.; Geim, A. K. Two-Dimensional Atomic Crystals. Proc. Natl. Acad. Sci. U. S. A. 2005, 102, 10451−10453. (3) Britnell, L.; Gorbachev, R. V.; Jalil, R.; Belle, B. D.; Schedin, F.; Mishchenko, A.; Georgiou, T.; Katsnelson, M. I.; Eaves, L.; Morozov, S. V.; Peres, N. M. R.; Leist, J.; Geim, A. K.; Novoselov, K. S.; Ponomarenko, L. A. Field-Effect Tunneling Transistor Based on Vertical Graphene Heterostructures. Science 2012, 335, 947. (4) Fallahazad, B.; Lee, K.; Kang, S.; Xue, J.; Larentis, S.; Corbet, C.; Kim, K.; Movva, H. C. P.; Taniguchi, T.; Watanabe, K.; Register, L. F.; Banerjee, S. K.; Tutuc, E. Gate-Tunable Resonant Tunneling in Double Bilayer Graphene Heterostructures. Nano Lett. 2015, 15, 428−433. (5) Zhang, E.; Wang, W.; Zhang, C.; Jin, Y.; Zhu, G.; Sun, Q.; Zhang, D. W.; Zhou, P.; Xiu, F. Tunable Charge-Trap Memory Based on FewLayer MoS2. ACS Nano 2015, 9, 612−619. (6) Sup Choi, M.; Lee, G. H.; Yu, Y. J.; Lee, D. Y.; Lee, S. H.; Kim, P.; Hone, J.; Yoo, W. J. Controlled Charge Trapping by Molybdenum Disulphide and Graphene in Ultrathin Heterostructured Memory Devices. Nat. Commun. 2013, 4, 1624. (7) Liu, C.; Yan, X.; Song, X.; Ding, S.; Zhang, D. W.; Zhou, P. A SemiFloating Gate Memory Based on van der Waals Heterostructures for

METHODS Device Fabrication. The architectures were produced with a dry transfer technique. The graphene flakes were produced on a silicon substrate (with a 300 nm thick thermal oxide film) with a typical mechanical exfoliation method from bulk source materials. The h-BN and MoTe2 flakes were achieved on a transparent polydimethylsiloxane (PDMS) film with similar method, and then the h-BN and MoTe2 was aligned and transferred one by one with the help of an optical microscope. Standard e-beam lithography (EBL) and metal thermal evaporation were finally employed to define Au/Cr electrodes (50 nm/ 10 nm) on the produced structures with a lift-off approach. Characterization. Atomic force microscopy (AFM, Bruker Dimension Icon) in a tapping mode was used to characterize the morphology of the devices. Raman spectra were recorded with the same Raman system with a 514 nm laser. Electrical properties were measured with an Agilent-B1500 semiconductor analyzer in a lakeshore vacuum chamber of 10−4 Pa. Photovoltaic properties were performed with a laser of 450 nm in wavelength, the power of which can be tuned continually. We used an optical power meter to measure the power of the light and calculated the incident light power on the devices according to their area. 7221

DOI: 10.1021/acsnano.9b02817 ACS Nano 2019, 13, 7216−7222

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DOI: 10.1021/acsnano.9b02817 ACS Nano 2019, 13, 7216−7222