Nonvolatile Transistor Memory with Self-Assembled Semiconducting

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Non-volatile Transistor Memory with Self-assembled Semiconducting Polymer Nanodomain Floating-Gates Wei Wang, Kang Lib Kim, Suk Man Cho, Ju Han Lee, and Cheolmin Park ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.6b12376 • Publication Date (Web): 24 Nov 2016 Downloaded from http://pubs.acs.org on November 24, 2016

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ACS Applied Materials & Interfaces

Non-volatile Transistor Memory with Self-assembled Semiconducting Polymer Nanodomain Floating-Gates

Wei Wang, Kang Lib Kim, Suk Man Cho, Ju Han Lee, Cheolmin Park* Department of Materials Science and Engineering, Yonsei University, 50 Yonsei-ro, Seodaemun-gu, Seoul, 120-749 (Republic of Korea) E-mail: [email protected]

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Abstract Organic

field-effect

transistor-based

non-volatile

memory

(OFET-NVM)

with

semiconducting nano-floating-gates offers additional benefits over OFET-NVMs with conventional metallic floating-gates due to the facile controllability of charge storage based on the energetic structure of the floating-gate. In particular, an all-in-one tunneling and floating-gate layer in which the semiconducting polymer nanodomains are self-assembled in the dielectric tunneling layer is promising. In this study, we utilize crystals of a p-type semiconducting polymer in which the crystalline lamellae of the polymer are spontaneously developed and embedded in the tunneling matrix as the nano-floating-gate. The widths and lengths of the polymer nanodomains are approximately 20 nm and a few hundreds nm, respectively. An OFET-NVM containing the crystalline nano-floating-gates exhibits memory performance with a large memory window of 10 V, programming/erasing switching endurance for over 500 cycles, and a long retention time of 5000 seconds. Moreover, the device performance is improved by co-mixing with an n-type semiconductor; thus, the solution-processed p- and n-type double floating-gates capable of storing both holes and electrons allow for the multilevel operation of our OFET-NVM. Four highly reliable levels (two bits per cell) of charge trapping and de-trapping are achieved using this OFET-NVM by accurately choosing the programming/erasing voltages.

Keywords: Non-volatile memory, Organic field-effect transistor memory, Polymer nanofloating-gate, Double polymer/molecule floating-gate, Sequential spin-coating, Multilevel memory


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1. Introduction Organic memory has attracted considerable research interest due to its advantages over the inorganic counterparts, including low cost, light weight, mechanical flexibility, low-temperature and easy processing.1–13 Among the many device configurations of organic memory, field-effect transistor memory with floating-gates has attracted great interest and is considered as a promising candidate for nextgeneration organic flash memory because of its simple device structure (i.e., single transistor), non-destructive read-out, massive memory capacity, compatibility with complementary logic circuits, and potential application as a flexible or stretchable charge-storage medium.5–11 A standard floating-gate organic field-effect transistor nonvolatile memory (FG-OFET-NVM) comprises a semiconductor active layer, tunneling layer, floating-gate layer, and blocking layer in addition to three terminal electrodes. The charges can be trapped and de-trapped in the floating-gate layer (i.e., the potential well between the blocking and tunneling dielectric layers), depending upon the electric field applied to the gate electrode, resulting in bi-stable threshold voltages suitable for non-volatile memory. The use of individually separated and isolated arrays of metallic nanoparticles (NPs) embedded in a dielectric medium has advantages over a traditional planar floating-gate because it maximizes the amount of charge storage sites and minimizes charge leakage.8 The proper selection of floating-gate materials and optimization of their nanostructures (sizes and distributions) is therefore of prime importance for high performance memory.4,14 Numerous attempts have been made in recent years to develop efficient metallic NPs floating-gate layers, including vacuum thermal evaporation,1–6

electrostatic

self-assembly,7,8

templated

synthesis

with

block

copolymers,10–12 and microcontact printing.13 The formation of metal NPs that are



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uniform in both size and distribution is not straightforward and often requires the elaborate control of process parameters.15–17 An alternative route for large-area and uniform charge-storage sites is to utilize semiconducting materials such as fullerene (C60), 6,6-phenyl-C61-butyric acid methyl ester (PCBM), and 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pen) as well as conjugated polymer NPs as floating-gate layers.14,18–20 Semiconducting floating-gates are beneficial because the memory performance can be in principle controlled by adjusting the energy level alignment between the energy structure of the semiconducting channel and that of the semiconducting floating-gate. In other words, the charge injection can be further controlled beside the dielectric tunneling barrier between the channel and the floating-gate.19 Additional efforts have been made to properly isolate these semiconductors in between tunneling and blocking layers with uniform sizes and shapes. In most cases, a thin layer of semiconducting NPs was sequentially deposited on a blocking layer followed by the fabrication of a tunneling layer on the bilayers.18 All-in-one tunneling and floating-gate layers in which the semiconducting molecules are well dispersed in the tunneling electret layers have been also reported.19 Semiconducting polymers with extended π-conjugation along the chain backbone have recently been employed as floating-gate layers in which the conjugated polymer NPs prepared by re-precipitation are evenly embedded in a tunneling dielectric matrix.20 Motivated by a previous work with conjugated polymer NPs, we envisioned that the nanoscale phase segregation of a semiconducting polymer in a dielectric tunneling matrix may be a convenient way for fabricating isolated nanodomains of the semiconducting polymer spontaneously embedded in the tunneling layer, even without an additional NPs preparation step. The crystallization of a semiconducting polymer in a thin blended tunneling film wherein characteristic crystalline polymer lamellae are 4 ACS Paragon Plus Environment

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readily developed and isolated in the dielectric medium with widths and lengths of approximately tens of and hundreds of nanometers, respectively, can be used. These nanoscale semiconducting lamellae efficiently serve as floating-gate domains, giving rise to highly reliable charge-storage performance. To further take advantage of a solution-processed all-in-one tunneling:floating-gate layer with phase-segregated semiconducting nanocrystalline domains, fabricating both an active semiconducting channel and a blocking layer via a solution process would be beneficial. In this study, we demonstrate a high performance FG-OFET-NVM with top-gate device architecture containing three sequentially solution-processed stacked component layers as the semiconducting channel layer, an all-in-one tunneling:floating-gate layer, and a blocking layer. More interestingly, crystalline nanodomains of p-type poly(3-hexylthiophene-2,5-diyl) (P3HT) were spontaneously developed when spin-coating a blended solution of P3HT with a dielectric poly(styrene) (PS) tunneling polymer. The resulting nanodomains successfully serve as isolated floating-gates in the film, giving rise to a high performance NVM with large threshold voltage window; a fast programmable/erasable switching time (< 5 ms); a highly reliable write/erase switching endurance (> 500 times); and good data retention time of 5000 seconds. Moreover, the addition of n-type PCBM in the phase-segregated tunneling:floatinggate layer further improved the device performance because both holes and electrons could be stored in the P3HT and PCBM domains. The sufficiently large threshold voltage window arising from our all-in-one solution-processed p- and n-type double floating-gate allowed us to develop a multilevel FG-OFET-NVM wherein four highly reliable levels (two bits per cell) of charge trapping and de-trapping are successfully achieved by accurately choosing the programming/erasing voltages.

2. Experimental Section



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Materials. Poly{[N,N′-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6diyl]-alt-5,5′-(2,2′-bithiophene)} [P(NDI2OD-T2)] was purchased from Polyera Corp. (United States) and used without purification. P3HT (Mw = 15–45 kg mol−1 with >95% head-to-tail regioregularity), PCBM, PS (Mw = 28 kg mol−1), and Poly(methyl methacrylate) PMMA (Mw = 12 kg mol−1) were purchased from Sigma-Aldrich without purification. Device Fabrication and Characterization. The n-type semiconducting polymer P(NDI2OD-T2) was dissolved in toluene with a concentration of 0.5 wt%. Various blended solutions for tunneling:floating-gate layers of PS:P3HT and PS:[P3HT:PCBM] with different weight fractions were prepared in chlorobenzene with a concentration of 0.5 wt%. PMMA used as a blocking layer was dissolved in 2-ethoxyethanol with a concentration of 5 wt%. An Au film (30 nm) was thermally evaporated on the surface of a 200-nm-thick SiO2 insulatorcoated Si substrate as source/drain (S/D) electrode through a shadow mask. The channel length (L) and width (W) were 100 µm and 1000 µm, respectively. The P(NDI2OD-T2) solution was spin-coated on the substrates with S/D electrodes to form a 35-nm-thick semiconductor active layer. The single tunneling:floating-gate layer films comprising a PS dielectric and either P3HT or P3HT:PCBM were deposited on the surface of P(NDI2OD-T2) by spin-coating from the corresponding blended solution. Note that although chlorobenzene is not an orthogonal solvent for the active P(NDI2OD-T2) layer, we were able to avoid damage to the active channel layer upon the subsequent spin-coating of the blended solution by minimizing the contact time of chlorobenzene on P(NDI2OD-T2). The thickness of a single tunneling:floating-gate layer film was approximately 25 nm. Subsequently, 280-nm-thick PMMA was prepared on the single tunneling:floating-gate layer as a blocking layer. Upon sequential preparation of each layer, post thermal annealing was employed to remove the residual solvents at 100 °C. P(NDI2OD-T2) layer, all-in-one tunneling:floating-gate layer and PMMA blocking layer were annealed for 10, 10 and 120 min, respectively. The 80-nm-thick top-gate Al electrodes were thermally deposited with a patterned shadow mask aligned with 6 ACS Paragon Plus Environment

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respect to the previously formed S/D electrodes. To make the Au S/D electrode accessible to the contact probe tips, the devices were further etched with oxygen plasma (100 W for 200 s, 10−3 Torr, 40 sccm) generated by reactive ion etching (RIE) (Femto VITA-4E). Arrays of Al gate electrodes were used as RIE blocking masks, giving rise to arrays of top-gate bottomcontact FG-OFET-NVM devices, as illustrated in the schematic in Figure 1. The fabricated FG-OFET-NVMs were characterized with a semiconductor parameter analyzer (Keithely 4200 SCS) in ambient atmosphere and at room temperature. Capacitors with the structure of Si++/PS:P3HT tunneling:floating-gate/Al were fabricated with an area size of 0.3 x 0.3 mm2. Blend films of PS and P3HT with different compositions were spin-coated on the surface of Si++ substrate, followed by the deposition of 80-nm-thick Al top electrodes by thermal evaporation with a patterned shadow mask. The capacitance versus the voltage was measured by using semiconductor systems (Keithely 4200 SCS). Structural characterization: The thicknesses of the semiconductor active layer, the single tunneling:floating-gate layer, and the blocking layer were measured using an Alpha step 500 Surface Profiler (AS500; KLA-Tencor Co.). The surface morphology of the semiconductor active layer and the nanostructures of the single tunneling:floating-gate layers were observed by tapping-mode atomic force microscopy (AFM; Nanoscope IV, Digital Instruments) in height and phase contrast and by 2D grazing-incidence X-ray scattering (GIXD). GIXD experiments were performed on the 9 A beam line at the Pohang Accelerator Laboratory in Korea (incidence angle: 0.09°–0.15°). The samples were mounted on an x- and y-axis goniometer. The scattered beam intensity was recorded with an SCX:4300-165/2 CCD detector (Princeton Instruments). 2D GIXD patterns were obtained in the range of 0 < qz < 2.33 Å−1, 0 < qxy < 2.33 Å−1.

3. Results and Discussion



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A top-gate bottom-contact FG-OFET-NVM with a phase-segregated semiconducting nanodomain floating-gate was fabricated via the sequential spin-coating of the constituent layers, as shown in Figure 1. A detailed description of the fabrication process is given in the Experimental section. A thin semiconducting channel layer of P(NDI2OD-T2) was spincoated on a pre-defined source and drain electrodes. The film exhibited a uniform and smooth surface morphology with a root mean square (RMS) roughness of 0.470 nm, as shown in Figure S1a (Supporting Information, SI). A blended PS:P3HT film spin-coated on the P(NDI2OD-T2) layer serves as a crystalline P3HT floating-gate embedded in a tunneling PS layer. A PMMA layer with a thickness of approximately 280 nm was subsequently spincoated on the blended layer followed by the deposition of a top-gate Al electrode by thermal evaporation, as shown in Figure 1. It should be noted that the spin-coating of a blocking layer should not damage the underlying all-in-one tunneling/floating-gate layer, which was successfully achieved by employing 2-ethoxyethanol, an orthogonal solvent for the all-in-one tunneling and floating-gate layer. The crystalline morphologies of the PS:P3HT films with various blend compositions (19:1, 9:1, 7:3, 5:5, and 3:7) were investigated by tapping-mode atomic force microscopy (TM-AFM), and the results are shown in Figure 2. Most of the blended films were very smooth with RMS roughness values less than 2.9 nm; in particular, the blends with low P3HT contents less than 30 wt% exhibited very low RMS roughness values of less than approximately 0.5 nm (Figure S1,SI). We analyzed the morphology of the blend films quantitatively with several AFM images for each blend film. Thread-like edge-on crystalline P3HT lamellae with thicknesses of approximately 20 nm are apparent, even in the blended film containing 5 wt% P3HT (Figure 2a), and they become more prominent with increasing P3HT content. The films with low P3HT contents less than 30 wt% showed well-defined crystalline lamellae efficiently separated with both amorphous regions of P3HT and PS (Figure 2a-c). The lamellae varied in length from 300 to 500 nanometers. Lamellae stacking 8 ACS Paragon Plus Environment

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occurs with the increase of P3HT, making an apparent width of a P3HT domain thicker. Approximately P3HT nanodomains of 80 and 100 nm in width were observed a 10 wt% and 30 wt% P3HT film, respectively. When the P3HT content increased, phase inversion occurred in which phase-segregated PS microdomains of approximately 400 nm in diameter were embedded in the P3HT matrix containing the crystalline lamellae (e.g., in the PS:P3HT (5:5) film; Figure 2d). When the amount of PS in the blended films further decreased, the PS microdomains became smaller (Figure 2e). The blend composition of PS and P3HT in the allin-one tunneling:floating-gate layer was carefully controlled to obtain the optimized nanostructure of P3HT. As expected, the films with low P3HT contents and individual crystalline lamellae that are efficiently isolated by the insulating PS matrix are beneficial as floating-gates due to their ability to securely trap and de-trap charge through the PS tunneling layer, giving rise to excellent NVM performance, as shown later. The crystallographic molecular structures of the PS:P3HT blended thin films with different P3HT contents were examined by two-dimensional grazing-incident X-ray diffraction (2D GIXD), and the results are shown in Figs. 2f–j. These patterns display an intensified set of reflections at a scattering vector, qz, of approximately 0.38, 0.74, and 1.13 Å−1, corresponding to the (h00) plane of the P3HT crystals aligned parallel to the surface normal. The diffraction results combined with the AFM findings suggest that edge-on crystalline lamellae with P3HT chains preferentially aligned parallel to the surface were embedded in the PS matrix, as schematically shown in Figure 1. The presence of PS in a blended film did not affect the P3HT crystal orientation; however, the absolute intensity of the reflections decreased with increasing PS amount, as shown in Figure 2k. The typical electrical transfer characteristics of the FG-OFET-NVMs with the PS:P3HT blended tunneling:floating-gate layers are shown in Figure 3. The transistors exhibited a typical ambipolar current modulation with electrons and holes as the majority and minority carriers, respectively, as evidenced by the stronger right arm compared with the left one in the 9 ACS Paragon Plus Environment


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transfer curves measured at the initial, programmed, and erased states. The extracted electron mobility (µe) in the linear regions of these devices decreased with increasing P3HT amount in the blended films in the range of 0.1–0.01 cm2 V−1 s−1 (Figure 3f and Table 1). It should be noted that the variation of the electron mobility as a function of P3HT in the blended films was rarely attributed to the change in capacitance of the insulating bilayers (PS:P3HT blended layer/PMMA one). The results indicate that the P3HT in the gate insulator hampers the electron transport in the channel, due to the charge transfer between P(NDI2OD-T2) and P3HT at the supplied gate field, which is the mechanism in present memory devices, as described below. The capacitance per unit area (Ctotal) of the total dielectric layer consisting of PMMA and an all-in-one tunneling:floating-gate layer in series was obtained from the following equation: 1/Ctotal = 1/CPMMA + 1/Call-in-one where, CPMMA and Call-in-one are the capacitance per unit area of the PMMA blocking layer and the tunneling:floating-gate all-in-one layer. First, we examined Call-in-one with different PS:P3HT compositions in capacitors of highly dope Si++/all-in-one PS:P3HT tunneling:floating-gate/Al. (Figure S2, SI) As expected, at high P3HT content, the capacitance of the layer becomes sweep voltage dependent due to effective hole accumulation in the majority P3HT regions at the negative voltage which makes the effective layer thickness decreased, giving rise to the enhanced capacitance at the negative voltage regime. The enhancement in capacitance arising from P3HT became negligible when a 200 nm thick PMMA layer was placed on top of an all-in-one layer due to the low CPMMA of approximately 11.0 nF/cm2. Ctot was rarely varied with the composition of PS and P3HT, ranging from 9.84 to 10.1 nF/cm2, making the operation voltage of our device not dependent upon the relative content of P3HT of our all-in-one tunneling:floating-gate layer. The development of the binary 0 and 1 states of a memory device based on the charge transfer between the active channel layer and the floating-gate through a tunneling layer was investigated by supplying the programming (P) and erasing (E) gate-source voltage (VGS) 10 ACS Paragon Plus Environment

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pulses. During the P/E operations, source electrode and drain electrode were always maintained short circuit, and the P/E pulse time was always set as 5 ms. When a negative VGS pulse of −50 V was supplied, an obviously negative shift in the transfer curves was observed (Figs. 3a–e) due to the hole injection and trapping in the nanodomain floating-gate from the semiconductor active layer through a tunneling mechanism. This negative shift is defined as a P process. The programmed transfer curves (red lines in Figure 3a–e) shifted in the positive direction when an opposite VGS pulse of +50 V was supplied, which corresponds to an E process. Contrary to the previous results where PS exhibited charge trapping performance,21 no current hysteresis was observed in a device without P3HT in the gate-insulating layer, which clearly implies that the phase-segregated P3HT nanodomains are essential for the charge trapping and de-trapping process (Figure S3a, SI). The tunneling of a charge across dielectric medium is a function of electric field imposed between two metallic contacts and thus the tunneling distance can be varied by the applied gate voltage in a field effect transistor. The tunneling distance of approximately a few nanometers is typical in floating-gate field effect transistor memories based on Si semiconducting channels with the operation voltage of a few volts. On the other hand, tunneling layers are frequently used of tens of nanometers in thickness in numerous floating-gate memories with organic semiconductors.4,8,9,15,16,18,22 In our memories, all-in-one tunneling:floating-gate layers were successfully employed of approximately 25 nm in thickness, giving rise to the non-volatile memory which was operated at the supplied programming and erasing voltages of ±50 V. Further understanding of working principle of our device would be experimentally addressable with temperature dependent tunneling of a floating gate memory.23,24 However, the temperature dependent experiment should be done at very low temperature to minimize the thermal noises. In particular, it is hardly possible to address the temperature dependent tunneling mechanism in a floating gate memory containing self-assembled nano-floating gates where the precise control of the location of the nano-floating gates is hardly made in a tunneling layer. The 11 ACS Paragon Plus Environment


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memory devices fabricated by the present solution-processed method have a good yield of approximately 80%, and out of a single batch of 14 devices, more than 10 exhibited similar programmable/erasable properties. The threshold voltage shift of the programmed/erased transfer curves depends on the P3HT content. To quantify this dependence, both the memory ratio and memory window were examined as functions of the P3HT content, and the results are summarized in Figure 3f and Table 1. The memory ratio, defined as the ratio of the drain-source current (IDS) between the P and E states, was extracted at VGS = 0 V, which is considered to be the optimum condition for the reading (R) operation of the memory with the lowest power consumption and the smallest external influence. The memory window (∆Von) was calculated from the shift of the turn-on voltage (Von) between the P and E states. Here, Von is defined as the VGS at IDS = 1.0 nA. Figure 3f shows that both memory ratio and ∆Von increased with P3HT up to a certain composition and decreased with further increases in P3HT. Since ∆Von is proportional to the density of the charges trapped in the floating-gate,16 the increase in ∆Von with P3HT content at low P3HT contents suggests an increase in charge-trap sites in the P3HT nanodomains. When the P3HT content in a blended film increases, crystalline lamellae are not completely isolated with PS chains and tend to aggregate with each other (Figure 2), reducing the number of effective charge-trap sites. Considering that a memory with a floating-gate containing isolated metal NPs shows better performance than one with a planar metal floating-gate, the decrease in ∆Von in the presence of aggregated P3HT crystals is reasonable. In fact, a device with a planar P3HT floating-gate inserted between PS tunneling and PMMA blocking layers exhibits a ∆Von of nearly zero (Figure S3b, SI). For blended films with high P3HT contents, charges in the channel are more easily transferred to P3HT nanodomains through the thinner PS tunneling layer. The interaction between the electrons in the channel and the holes in the P3HT floating-domain becomes stronger with increasing P3HT content (i.e., decreasing of PS) in a blend film, making the electron mobility in P(NDI2OD-T2) decreased with the increase 12 ACS Paragon Plus Environment

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of P3HT at high P3HT blend films. Most of the transfer curves were located at the left side of the initial transfer curves (black lines) after E operations (i.e., the erased transfer curves; blue lines in Figs. 3a–e). The results indicate that the erase process was induced by the holes detrapped from the floating-gate and moved back to the active layer; and in some cases, a small amount of residual holes were still trapped in the floating-gate. Under optimized conditions, a device with a PS:P3HT (9:1) film showed a negligible shift in the transfer curve at the supplied erasing gate voltage (VE) of 50 V when measured in the linear region at a drainsource voltage (VDS) of 10 V (Figure 4a). When a programming gate voltage (VP) of −50 V was supplied, an obvious negative shift in transfer characteristics was observed, and a turn-on voltage at the P state (Von-P) of −9.1V was obtained. Then, by again supplying a VE of 50 V, this Von-P was positively shifted to the E state with a Von-E (the turn-on voltage at E state) of −0.6V. The distinguished P and E states correspond to the binary “1” and “0” in the memory, respectively. As a result, the typical memory ratio of 50 and a ∆Von of 8.5 V were obtained. Even at the shortest P/E pulse of 5 ms, a large ∆Von was obtained. The changes in both Von-P and Von-E were negligible when the P/E pulse time was increased from 5 ms to 1 s (Figure 4b). The program/erase characteristics of our memory with the P3HT nanodomain floatinggate were highly reliable. Both Von-P and Von-E were well maintained with only slight fluctuations, even for repetitive P/E switching for more than 500 cycles (Figure 4c). To examine the stability of our memory’s data storage over time, we investigated the retention characteristics. As shown in Figure 4d, after a VP/VE of ±50 V was supplied, the currents (IDS-1 and IDS-0) at the “1” and “0” states were measured as functions of time at reading voltages (VR) of VGS = 0 V and VDS = 10 V, respectively. A visible decrease in IDS-1 was observed in the front period of 500 s, due to the release of the charges. After the equilibrium reached, both IDS-1 and IDS-1 maintained well with a slight decrease, during the 5000-s measurement. The excellent memory performance of our device is attributed to the inter-transfer of only holes between the active layer and floating-gate by the applied VGS, as schematically 13 ACS Paragon Plus Environment


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illustrated by the energy-band diagrams of the constituent layers shown in Figs. 5a and b. Although ambipolar charge transportation can occur at the P(NDI2OD-T2) channel due to its polymer backbone with alternating electron-donor and electron-acceptor moieties,4,25 only unipolar carriers (i.e., holes) are inter-transferred between P(NDI2OD-T2) and P3HT through the tunneling process due to the characteristics of the electron-donating P3HT. During the P process, a negative VP causes holes to accumulate at the interface of the active channel layer and blended film, biasing the energy-band. Simultaneously, the accumulated holes are injected and trapped in the P3HT nanodomain floating-gate by tunneling through the surrounding PS dielectric. The built-in electric field induced by the trapped holes causes more electrons to accumulate in the channel, giving rise to a large negative shift in the transfer characteristics. Therefore, the high-current state of the device is obtained, even at the reading state of VR = 0 V. When a VE is supplied, the holes that have been stored in the P3HT are detrapped and rejected back into the channel, causing the transfer characteristics to shift in the positive direction, resulting in the low-current state in the channel at VR = 0 V. As a result, the channel of the device is switched between the high- and low-current states upon the supply of VP and VE, respectively. Notably, a potential barrier of 0.6 eV, defined as the difference between the HOMO levels of P3HT (−5.0 eV) and P(NDI2OD-T2) (−5.6 eV), exists for hole movement from P3HT back to P(NDI2OD-T2); in contrast, no barrier to hole movement exists in the reverse direction. The barrier to hole movement can lead to the incomplete removal of the holes upon the erase process, causing a small amount of electrons to still be accumulated in the channel at the reading “0” state of zero VGS. The consequent negative Von-E requires an external VGS of −7 V to −3 V to completely deplete the electrons in the channel and to thus obtain the maximum on/off current ratio. It is apparent that the potential barrier for electron transfer from the LUMO (-4.0 eV) of P(NDI2OD-T2) to the LUMO (-3.0 eV) of P3HT is larger than that for holes transfer from the HOMO (-5.0 eV) of P3HT to the HOMO (-5.6 eV) of P(NDI2OD-T2) upon erasing (Figure 5b). The smaller energy barrier to the hole 14 ACS Paragon Plus Environment

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transfer makes the hole transfer more dominantly occur, consistent with the experimental results. It should be noted that compared with the OFET memories with polymer electrets,25 our non-volatile memory with an all-in-one tunneling:floating-gate layer in particular containing self-assembled semiconducting nanodomains holds several advantages including one-step preparation of both tunneling and floating-gate layer and self-forming nanodomains based on polymer crystallization. More importantly, the number of trapped charges can be in principle controlled by adjusting the energy level alignment between the energy structure of a semiconducting channel and that of a semiconducting floating-gate. To further widen the memory window while simultaneously achieving the maximum on/off current ratio at zero VGS to obtain low power consumption and reliable data storage, a floating-gate capable of trapping and de-trapping not only holes but also electrons is desirable.26,27 In the current system with a hole-accepting p-type semiconducting nanofloating-gate (P3HT), the incorporation of an electron-accepting semiconductor can be an efficient way to achieve the above goals. It would be even more beneficial if the n-type organic semiconducting floating-gate can be simultaneously developed with our P3HT nanodomains. For this purpose, we employed a representative solution-processible electronaccepting organic semiconductor PCBM based on the energy-band diagrams in Figure 5c and 5d. Although there is a small barrier of 0.3 eV, electrons can be injected and trapped in PCBM from P(NDI2OD-T2) by tunneling through the PS dielectric in the E process. The built-in field induced by the trapped electrons can shift the transfer curve in the positive voltage direction. The resulting depletion of the channel at zero VGS can minimize IDS, giving rise to enhanced memory on/off current ratio. The higher LUMO level of PCBM compared with that of P(NDI2ODT2) favors the transfer of electrons from PCBM to P(NDI2OD-T2). Thus, more electrons are de-trapped and transferred to P(NDI2OD-T2) by tunneling in the P process. As a result, many positive charges are stored in the floating-gate, which can induce many mobile electrons in the channel, even at zero VGS, resulting in a negative Von-P. Hole 15 ACS Paragon Plus Environment


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transfer from n-type P(NDI2OD-T2) to PCBM rarely happens due to the high potential barrier for hole transfer from the HOMO (-5.6 eV) of P(NDI2OD-T2) to the HOMO (-6.1 eV) of PCBM (Figure 5c). The energy-band diagrams of devices with both P3HT and PCBM floating-gates (Figure 5e and 5f) clearly show that both holes and electrons can be transferred from P(NDI2OD-T2) to P3HT and from PCBM to P(NDI2OD-T2), respectively, by tunneling during P operation, possibly giving rise to the larger ∆Von-P than ∆Von-E (indicating the shift value of the Von at the programmed and erased states relative to that at the initial state, respectively) with respect to the device that contains only a P3HT nanodomain floating-gate. It is also plausible that charge transfer can occur at the interface of P3HT and PCBM and consequently affect the memory performance. Considering that total amount of P3HT and PCBM in an all-in-one tunneling:floating layer is 30 wt%, the heterojunction interface does not seem prevalent in our memory. Even at the interfaces developed between P3HT and PCBM, charge transfer unlikely occurs due to the large energy barriers. The LUMO and HOMO of the P3HT are -3.0 and -5.0 eV, respectively. The LUMO and HOMO of the PCBM are -3.7 and -6.1 eV, respectively. Upon programming, holes trapped in P3HT are hardly transferred to PCBM due to the larger potential barrier between the two HOMO levels. In addition, electrons trapped in PCBM upon erasing are rarely transferred to P3HT due to the larger potential barrier between the two LUMOs. To validate our speculation based on the energy-band structures in Figure 5, we added PCBM to a PS:P3HT blended solution followed by the spin-coating of the solution. A blended thin film was then formed with both P3HT and PCBM nanodomains uniformly distributed in the PS matrix and successfully employed in an FG-OTFT-NVM as a double floating-gate of P3HT and PCBM nanodomains in which holes and electrons were trapped in P3HT and PCBM domains, respectively. The blend compositions were carefully controlled to maximize memory performance. We fixed the composition of PS at 70 wt% in the tunneling:floating-gate blended film and varied the relative amounts of P3HT and PCBM 16 ACS Paragon Plus Environment

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(10:0, 9:1, 7:3, 5:5, 3:7, 1:9, and 0:10) to examine the effect of PCBM on memory performance. All the ternary blended films with different P3HT and PCBM contents were smooth and uniform with RMS < 0.5 nm. The films exhibited the characteristic crystalline P3HT lamellae, and PCBM was well dispersed in the films (Figure 6a; also see Figure S4, SI). The 2D GIXD results also confirm the independent development of both P3HT and PCBM crystals in the ternary blended films (Figure S5, SI). For instance, the 2D GIXD pattern of a PS:[P3HT:PCBM (7:3)] film (Figure 6b) shows (h00) reflections arising from the edge-on P3HT crystalline lamellae as well as a broad reflection at approximately 1.3 A−1, corresponding to PCBM regions. It should be, however, noted that the PCBM regions were hardly visualized in real space in particular in transmission electron microscope due to their low electron beam contrast.28 All memory devices with double floating-gates (schematically shown in Figure 6c) exhibited excellent programmable/erasable properties with high device yield. In particular, the bidirectional shift of the programmed and eased transfer characteristics was successfully obtained with a PS:[P3HT:PCBM] double floating-gate. This clearly indicates that ambipolar charge trapping and de-trapping occurred as expected, as shown in Figure 6d and Figure S6 (SI). ∆Von-P and ∆Von-E as functions of the relative amount of PCBM were obtained with full sets of memory devices for each blended film, and the results are summarized in Figure 6e and Table 2. The increase in the positive shift of ∆Von-E with PCBM indicates that more electrons were trapped due to more trapping sites supplied with increasing PCBM content in the double floating-gate. In addition, the dependence of ∆Von-P on the relative amount of P3HT and PCBM in the double floating-gate was also observed. The results clearly show that the amounts of holes and electrons trapped in the double floating-gate can be adjusted by selecting the relative amount of P3HT and PCBM. The concave shape of the plot of average ∆Von-P vs. PCBM content (red line in Figure 6e) is apparent, and the memory window (∆Von)



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was maximized in the device with a double floating-gate PS:[P3HT:PCBM (5:5)] film (Figure 6f). In addition, the on/off current ratio was the largest for the blended composition (Figure 6g). The ∆Von-P as a function of the relative amount of PCBM was smaller than the ∆Von-E because both holes injected/trapped in P3HT from P(NDI2OD-T2) and electrons rejected/detrapped from PCBM to P(NDI2OD-T2) were responsible for the negative shift in Von-P. The contribution to the negative program voltage shift of both P3HT and PCBM resulted in the small Von-P variation as a function of PCBM. The experiment results demonstrate the usefulness of a double floating-gate in our memory devices. The IDS at zero VGS, induced by more negative Von-P in the devices with an appropriate double floating-gate, larger than that in the device with a PCBM-only floating-gate resulted in a sufficient on/off current ratio (Table 2) suitable for distinct multiple memory states as shown next. Multilevel flash memory, which is one of the most important challenges in memory technologies, offers a cost-effective route for ultrahigh density memory. To date, only a few multilevel FG-OFET-NVM devices have been achieved by combining optical and electrical signals for programming,29-31 utilizing an ambipolar active channel layer,32 and fabricating a vacuum-assisted double floating-gate.33 Multilevel data operation was also successfully realized in our FG-OFET-NVM with a double floating-gate of solution-processed donor P3HT and acceptor PCBM nanodomains (Figure 7). With the increase in VP and VE, the programmed and erased transfer curves of the device with a PS:[P3HT:PCBM (5:5)] blended film shifted further in the negative and positive directions, respectively, indicating an increase in both the holes and electrons trapped in the floating-gate with the applied voltages. The maximal ∆Von of >16.0 V was achieved at VP/VE = ±55 V, indicating complete charge trapping in the floating-gate. The memory ratio greater than 103 at VR = 0 V was achieved at VP/VE = ±55 V. It should be noted that due to the rather small memory ratio, in particular, at 0 V, the memory with only PCBM was hardly applicable for multi-level information storage. 18 ACS Paragon Plus Environment

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(Figure S7, SI) The memory ratio sufficiently large for multi-level data storage was obtained by optimally mixing P3HT and PCBM in an all-in-one tunneling:double floating-gate layer. (Figure S6, SI) In addition, switching between the programmed and erased states of our double floating-gate memory was fast, and the shift in the transfer curves upon switching was achieved even at a short VP/VE pulse of 5 ms (Figure 7b). The dependence of the location of Von-P/Von-E on the value of the supplied VP/VE as well as the sufficiently large on/off IDS level at zero reading voltage allowed for multilevel information storage. By carefully choosing multi-step VP and VE, four distinct reversible transfer characteristic states were achieved, and the IDS difference between two adjacent levels was greater than one order of the magnitude at VR = 0 V (Figure 7c). At VP/VE = ±55 V, the transfer characteristics exhibited the most negative and positive shifts, corresponding to the states of 11 and 00, respectively. The transfer characteristic at the 11 state was changed to the 10 state when a VE of 25 V was supplied; the 10 state was then changed to the 01 state with the application of a VE of 41 V. In reverse, the transfer characteristic at the 00 state was changed to the 01 state when a VP of −45 V was supplied and then to the 10 state with the application of a VP of −50 V. Excellent endurance characteristics were obtained in our double floating-gate memory device; both Von-P and Von-E at the 11 and 00 states, respectively, hardly varied under repetitive P/E endurance switching at VP/VE = ±55 V for up to 500 cycles (Figure 7d). Interestingly, even after 500 endurance cycles, the memory device still exhibited four distinguishable states upon the corresponding multi-step VP/VE operations, as shown in Figure 7e. For the practical application of multilevel memory, it is important to examine the random switching capability between any two levels of the multi-states. The dynamic behavior of IDS switching between two randomly chosen states of a multilevel memory was measured as a function of time, and the results are shown in Figure 7f. The distinguishable four levels of IDS at the reading voltage were achieved when any two memory states were arbitrarily switched. 19 ACS Paragon Plus Environment


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Note that the random switching performance of a multilevel memory has rarely been demonstrated before now, and our memory device clearly exhibits inter-switching between the two randomly chosen states, as schematically illustrated in Figure 7g, and the switching is reversible under appropriate VP/VE operation conditions. The retention characteristics of the multilevel states were also investigated by independently measuring four distinguishing IDS values as a function of time (Figure 7h). The memory exhibited very stable four-state retention characteristics under a constant reading condition of VDS = 10 V and VR = 0 V, and the current gap between the two adjacent current states was sufficient (approximately one order of magnitude) after the practical 5000-s measurement. The reliable program/erase cycle endurance, repetitive switching capability between the two randomly chosen memory states, and long data retention time of the four distinct states of our memory clearly suggest that the solution-processed non-volatile OFET memory with a double nanocrystalline domains floating-gate developed by spontaneous crystallization and phase separation during a one-step spin-coating process has great potential for cost-effective, high-density, non-volatile flash memory.

4. Conclusion We demonstrated that polymer crystallization involving characteristic hierarchical structures is a simple but robust route for developing nanometer-scale semiconducting polymer crystals evenly distributed in a tunneling dielectric matrix that are suitable as nano-floating-gates for high performance non-volatile polymer flash memory. The crystallization of P3HT occurs upon the one-step spin coating of a dielectric PS and semiconducting P3HT blend solution, leading to thread-like edge-on crystalline lamellae with thicknesses and lengths of approximately 20 and 1000 nm, respectively, in the PS matrix. The results clearly suggest that the crystalline lamellae were effectively isolated from each other by the PS matrix and successfully trapped and de20 ACS Paragon Plus Environment

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trapped the programmed holes upon corresponding gate voltage inputs, giving rise to a highly reliable FG-OFET-NVM. Our device with top-gate device architecture containing three stacked component layers that are sequentially solution-processed, a blocking layer, a single tunneling:floating-gate layer, and a semiconducting channel layer, exhibits a high performance NVM with a large threshold voltage window, a fast programmable/erasable switching time of less than 5 ms, a highly reliable write/erase switching endurance (>500 times), and good data retention. Moreover, the addition of n-type PCBM in the tunneling:nanodomain P3HT floating-gate layer allowed us to fabricate a p- and n-type double floating-gate capable of storing both holes and electrons in the P3HT and PCBM domains, respectively. The sufficiently large threshold voltage window arising from the solution-processed double floating-gate leads to a multilevel FG-OFET-NVM in which four highly reliable levels (two bits per cell) of charge trapping and de-trapping are successfully achieved by choosing the appropriate programming/erasing voltages.



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Table. 1. Memory characteristics of the FG-OFET-NVM devices with all-in-one floatinggate:tunneling (PS:P3HT) layers. PS:P3HT

Mobility [10-2 cm2V-1s-1]

Memory ratio

Memory window [V]

∆Von-P [V]

∆Von-E [V]

19:1

6.9 ~ 10.5 (9.16)a)

11 ~ 98 (48)

6.5 ~ 9.7 (7.45)

-12.1 ~ -8.7 (-10.51)

-5.9 ~ -1.5 (-3.12)

9:1

6.6 ~ 10.0 (8.20)

45 ~ 500 (142)

7.4 ~ 13.5 (9.60)

-15.1 ~ -10.6 (-12.78)

-6.0 ~ -1.4 (-3.74)

7:3

2.9 ~ 4.9 (3.85)

12 ~ 103 (45)

5.1 ~ 8.3 (6.70)

-11.68 ~ -7.62 (-9.53)

-5.35 ~ -0.4 (-2.58)

5:5

2.2 ~ 4.5 (3.55)

10 ~ 76 (25)

4.2 ~ 7.1 (5.12)

-9.8 ~ -5.1 (-6.86)

-4.4 ~ -0.5 (-1.24)

3:7

1.1 ~1.5 (1.25)

5 ~ 26 (14)

2.5 ~ 4.8 (3.41)

-6.4 ~ -3.2 (-4.8)

-2.1 ~ -0.4 (-1.37)

a) The values in the parenthesis mean an average value.

Table. 2. Memory characteristics of the FG-OFET-NVM devices with all-in-one double floating-gate:tunneling [(P3HT:PCBM):PS] layers. PS:[P3HT:PCBM]

Mobility [10-2 cm2V-1s-1]

Memory ratio

Memory window [V]

∆Von-P [V]

∆Von-E [V]

7.0 : [3.0 : 0.0]

2.9 ~ 4.9 (3.85)a)

12 ~ 103 (45)

5.1 ~ 8.3 (6.70)

-11.68 ~ -7.62 (-9.53)

-5.35 ~ -0.40 (-2.58)

7.0 : [2.7 : 0.3]

2.2 ~ 5.8 (4.12)

22 ~ 130 (65)

7.0 ~ 11.6 (10.19)

-10.86 ~ -6.36 (-8.30)

-3.06 ~ 2.93 (0.74)

7.0 : [2.1 : 0.9]

2.4 ~ 7.2 (5.17)

100 ~ 870 (350))

9.9 ~ 15.4 (12.33)

-12.45 ~ -7.24 (-9.55)

0.22 ~ 5.48 (2.45)

7.0 : [1.5 : 1.5]

3.5 ~ 7.9 (5.41)

530 ~ 2120 (1210)

11.0 ~ 18.1 (13.90)

-14.01 ~ -8.15 (-10.91)

0.8 ~ 4.68 (2.44)

7.0 : [0.9 : 2.1]

3.6 ~ 8.1 (5.56)

220 ~ 1050 (790)

12.2 ~ 16.3 (13.65)

-12.53 ~ -8.62 (-10.62)

0.66 ~ 3.84 (2.96)

7.0 : [0.3 : 2.7]

4.5 ~ 8.3 (5.92)

340 ~ 1350 (940)

10.7 ~ 14.9 (13.44)

-11.91 ~ -8.05 (-9.90)

2.15 ~ 5.27 (3.64)

7.0 : [0.0 : 3.0]

4.7 ~ 8.8 (6.40)

200 ~ 840 (620)

10.4 ~ 15.1 (13.15)

-12.25 ~ -5.31 (-8.43)

2.98 ~ 6.06 (4.23)

a)

The values in the parenthesis mean an average value.


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Figure 1. Schematic depicting the fabrication of the arrays of top-gate bottom-contact FGOFET-NVM devices with self-assembled semiconducting polymer nanodomain floating-gates.



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Figure 2. TM-AFM images (the area size of 5µm × 5µm) in phase contrast (a–e) and 2D GIXD (f–j) images of all-in-one tunneling:floating-gate layers comprising PS:P3HT with different proportions: (a,f) 19:1, (b,g) 9:1, (c,h) 7:3, (d,i) 5:5, and (e,j) 3:7. (k) Intensity profiles as a function of qz obtained from the 2D GIXD images. The inset shows the magnified profiles to highlight the (200) and (300) reflections. 24 ACS Paragon Plus Environment

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Figure 3. Transfer characteristics of the FG-OFET-NVMs with single tunneling:floating-gate (PS:P3HT) layers with different proportions: (a) 19:1, (b) 9:1, (c) 7:3, (d) 5:5, and (e) 3:7. (f) Variation in electron mobility, memory ratio, and memory window of the FG-OFET-NVMs with the proportions of PS and P3HT in the tunneling:floating-gate layers.



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Figure 4. Device performance of an FG-OFET-NVM with a single tunneling:floating-gate layer of PS:P3HT (9:1). (a) Transfer characteristics measured sequentially for the initial, E, P, and E states. (b) Evaluation of the programmed and erased Von with the P/E pulse time. (c) Switching endurance, and (d) retention properties.


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Figure 5. Schematic depicting the energy-band diagrams of FG-OFET-NVM devices upon programming and erasing: devices with a single tunneling:floating-gate layer of (a, b) PS:P3HT, (c, d) PS:PCBM, and (e, f) PS:[P3HT:PCBM].



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Figure 6. (a) TM-AFM image in phase contrast and (b) 2D GIXD image of an all-in-one tunneling:double floating-gate layer with a 7:[2.1:0.9] PS:[P3HT:PCBM] film. (c) Schematic illustration of the FG-OFET-NVM with an all-in-one tunneling:double floating-gate layer. (d) The representative transfer characteristics of an FG-OFET-NVM with PS:[P3HT:PCBM(7:3)]. Variation in (e) Von-P and Von-E, (f) memory window (∆Von), and (g) memory current ratio with the proportions of P3HT and PCBM in the double floating-gate memory devices. 28 ACS Paragon Plus Environment

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Figure 7. Multilevel memory performance of an FG-OFET-NVM with PS:[P3HT:PCBM(5:5)]. Transfer characteristics at different (a) VP/VE and (b) P/E pulse times. (c) Sequential evaluation of multilevel transfer characteristics at different VP/VE values. (d) Switching endurance at repeatable VP/VE operations. (e) Sequential evaluation of multilevel transfer characteristics at different VP/VE values after 500 switching cycles. (f) Dynamic switching behavior of the device between any two memory states randomly chosen out of four memory levels. (g) Schematic of the switching routes between two randomly chosen memory states at the corresponding VP/VE. (h) Retention characteristics of four-level IDS values as a function of time. 29 ACS Paragon Plus Environment


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ASSOCIATED CONTENT AUTHOR INFORMATION Corresponding Author *Tel -82-2-2123-2833. Fax -82-2-312-5375. E-mail [email protected]. ACKNOWLEDGMENT This research was supported by the third Stage of the Brain Korea 21 Plus Project in 2014 and the National Research Foundation of Korea (NRF) grant funded by the Korean government (MEST) (No.2014R1A2A1A01005046).

Supporting information: AFM images, and I-V characteristics results. This information is available free of charge via the Internet at http://pubs.acs.org/.

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Nonvolatile Transistor Memory with Self-Assembled Semiconducting

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