One-TransistorâOne-Transistor (1T1T) Optoelectronic Nonvolatile

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One-Transistor-One-Transistor (1T1T) Optoelectronic Nonvolatile MoS2 Memory Cell with Nondestructive Read-Out Dain Lee, Seongchan Kim, Yeontae Kim, and Jeong Ho Cho ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b07077 • Publication Date (Web): 14 Jul 2017 Downloaded from http://pubs.acs.org on July 16, 2017

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ACS Applied Materials & Interfaces

One-Transistor-One-Transistor (1T1T) Optoelectronic Nonvolatile MoS2 Memory Cell with Nondestructive Read-Out Dain Lee,1 Seongchan Kim,1 Yeontae Kim,1 Jeong Ho Cho1,2* 1

SKKU Advanced Institute of Nanotechnology (SAINT), 2School of Chemical Engineering, Sungkyunkwan University, Suwon 16419, Korea. *Correspondence and requests for materials should be addressed to Cho, J. H. (e-mail: [email protected])

Abstract Taking advantage of the superlative optoelectronic properties of single-layer MoS2, we developed a one-transistor-one-transistor (1T1T)-type MoS2 optoelectronic nonvolatile memory cell. The 1T1T memory cell consisted of a control transistor (CT) and a memory transistor (MT), in which the drain electrode of the MT was connected electrically to the gate electrode of the CT, while the source electrode of the CT was connected electrically to the gate electrode of the MT. Single-layer MoS2 films were utilized as the channel materials in both transistors, and gold nanoparticles (AuNPs) acted as the floating gates in the MT. This 1T1T device architecture allowed for a nondestructive read-out operation in the memory because the writing (programming or erasing) and read-out processes were operated separately. The switching of the CT could be controlled by light illumination as well as the applied gate voltage due to strong light absorption induced by the direct band gap of single-layer MoS2 (~1.8 eV). The resulting MoS2 1T1T memory cell exhibited excellent memory performance, including a large programing/erasing current ratio (over 106), multilevel data storage (over 6 levels), cyclic endurance (200 cycles), and stable retention (103 s).

Keywords: MoS2, one-transistor-one-transistor (1T1T), memory, optoelectronic, nondestructive read-out

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INTRODUCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Graphene has received considerable attention due to its exceptional properties, including a high carrier mobility, good thermal conductivity, excellent mechanical flexibility, and high optical transparency.110

Transistor devices have benefitted from the exceptional optoelectronic properties of graphene.11-14 Its

inherent lack of a band gap, however, has restricted the use of graphene as a channel material for switching circuits or photo-detecting devices, which require clearly defined on/off states.15-21 Given these characteristics, single-layer molybdenum disulfide (MoS2), a layered two-dimensional transition metal dichalcogenide (TMD), has drawn intensive attention due to its exceptional electronic and optical properties.22-30 Transistors prepared using mechanically-exfoliated MoS2 flakes as a channel material exhibit good transport properties, with a high carrier mobility exceeding 40 cm2V–1s–1 and a large on/off current ratio of ~108.22,

31-34

In addition to the superb electrical properties of MoS2, the absence of interlayer

coupling among electronic states at the Γ points of the Brillouin zone in single-layer MoS2 results in strong absorption and photoluminescence (PL) bands at ~1.8 eV (689 nm).24, 35-39 Therefore, single-layer MoS2 is suitable for applications in optoelectronic devices that operate at visible wavelengths. MoS2 phototransistors have displayed an ultrahigh photoresponsivity, exceeding 2,000 AW–1 at an illumination power of 1.3 Wm–2, and a fast response time of less than 50 ms. 40-44 The combination of these outstanding electrical and optical properties renders single-layer MoS2 a promising candidate for new optoelectronic devices. Exploiting the optoelectronic properties of single-layer MoS2, we fabricated a one-transistor-onetransistor (1T1T)-type optoelectronic nonvolatile memory cell comprising a control transistor (CT) and a memory transistor (MT). Mechanically-exfoliated single-layer MoS2 and gold nanoparticles (AuNPs) were utilized as the channel material in both transistors and the floating gate of the MT, respectively. The 1T1T memory cell was fabricated by electrically connecting the drain electrode of the MT to the gate electrode of the CT, while the source electrode of the CT was connected electrically to the gate electrode of the MT. The proposed 1T1T-type device architecture enabled the writing (programming or erasing) and read-out processes to be operated separately by replacing the memory capacitor (MC) used in commercial one-

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transistor-one-capacitor (1T1C) memory cells with a memory transistor, thereby overcoming the destructive 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

read-out process.45-47 Importantly, for a 1T1T memory cell to be integrated into a memory array architecture, it is essential that the CT is used to select a particular memory word. Moreover, our memory cell does not require two independent word lines for the writing and read-out processes. Switching of the CT was also controlled by the light illumination on the channel of the CT. The resulting memory cell showed good device characteristics such as 106 programming/erasing current ratio, 6 level data storage, 200 cycle stability, and 103 s data retention. The 1T1T-type MoS2 optoelectronic nonvolatile memory cell proposed in this study represents a significant step toward future optoelectronic devices based on 2D nanomaterials.

RESULTS AND DISCUSSION Figure 1a shows a schematic diagram of the procedure used to fabricate the 1T1T memory cell consisting of a CT and MT based on single-layer MoS2 semiconductor channels. First, Au gate electrodes with a thickness of 30 nm and a width of 60 µm were thermally deposited onto a SiO2/Si wafer. An Al2O3 film with a thickness of 50 nm was then formed by atomic layer deposition (ALD), providing the blocking gate dielectric layer. Gold nanoparticles (AuNPs) were thermally deposited onto only the Al2O3 region of the MT. The AuNPs, with an average diameter of 9 nm, acted as a charge-trapping layer in the MT. The tunneling gate dielectric layer was formed by depositing, via spin-coating, an approximately 10 nm thick cross-linked poly(4-vinylphenol) (cPVP) layer, which was subsequently thermally annealed to form crosslinks. A single-layer MoS2 flake was then positioned on the channel region of both CT and MT using a custom-built micromanipulation system. Figure S1 shows an atomic force microscopy (AFM) image and height profile of the transferred MoS2 flake. The thickness of the MoS2 flake was measured to be around 0.7 nm, corresponding to the thickness of single-layer MoS2.22, 48 The Raman spectrum of the transferred MoS2 flake is shown in Figure S2. The spectrum exhibited two characteristic peaks positioned at 388.8 and 408.5 cm–1, which were associated with the planar vibration (E12g mode) and the out-of-plane vibration (A1g mode) of the sulfides, respectively. The 19.7 cm–1 gap between the two frequencies corresponded to a single layer

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of MoS2, consistent with the AFM results.49-50 The source and drain electrodes of both transistors were 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

patterned using conventional e-beam lithography. The drain electrode of the MT was connected electrically to the gate electrode of the CT, while the source electrode of the CT was connected electrically to the gate electrode of the MT. The circuit diagram of the 1T1T memory cell is shown in Figure 1b. Figure 1c shows an optical top-down image of the resulting 1T1T memory cell based on a single-layer MoS2 flake channel. For commercial 1T1C memory cells, the source electrode of the CT was connected to the memory capacitor (MC), as shown in Figure S3. It is important to note that the voltage applied to the bit line (VBL) was utilized not only to enforce the state of the memory capacitor, but also to read the current associated with each state. Due to this read-out mechanism, this process was destructive, and any data must be rewritten into the cell. By contrast, the writing (programming or erasing) and read-out processes were operated separately in our 1T1T design by replacing the memory capacitor with an MT, as illustrated in Figure 1b. During the writing process, the voltage applied to the word line (VWL) was set to +10 V to turn on the CT, which allowed the VBL to transfer to the gate electrode of the MT. At the same time, +20 V (or – 20 V) was applied to the BL for programming (or erasing). On the other hand, the read-out process was conducted at VWL = –10 V, at which the CT was turned off and the BL was disconnected from the gate electrode of the MT. It is important to note that the current corresponding to each written state could be detected in the sensing line (SL), regardless of the VBL. First, the data storage operation of the MT with an AuNP floating gate was investigated. Figure 2a shows the hysteresis loop of the transfer characteristics (drain current (ID) versus gate voltage (VG)) of the MT. The curve exhibited a clear clockwise hysteresis, which increased as the gate voltage increased from ±10 to ±20 V. This behavior originated mainly from electron trapping in the AuNPs under gate voltage conditions. The shift in the transfer curves under various VG values is shown in Figure 2b. The dwell time for each VG step (i.e., the pulse width) was 1 s. Under a positive VG, the electron in the MoS2 channel was transferred and trapped in the AuNP floating gate via the tunneling through the cPVP gate dielectric layer.5154

The internal electric field induced by negatively-charged AuNPs partially screened the applied VG, which 4


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shifted the curve in the positive VG direction and decreased the drain current under the same VG conditions. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

The resulting current level set the ‘programmed state’ of the MT. The shift in the transfer curve was directly proportional to the applied VG pulses. Figure 2c shows the memory window, which was defined as the difference between the threshold voltages (VTH) of the programmed and the erased states, as a function of the programming VG. The memory window increased linearly from 7.0 to 14.3 V as the programming gate voltage increased from 12 to 20 V. The number of trapped electrons was calculated using the equation ∆n = CS·∆VTH/e, where CS and e are the specific capacitance of the dielectric layer and the elemental charge, respectively.55-56 Given this relationship, the number of trapped electrons was calculated to be 5.8 × 1012 cm– 2

at 12 V and 1.2 × 1013 cm–2 at 20 V. More electrons in the MoS2 were transferred into the AuNP floating

gate under the application of a higher programming VG. These results suggested that multilevel data storage is possible if precise programming VG values are applied to the gate electrode with a sufficient drain current reading margin. The operation speed of the memory device was examined, as shown in Figure 2d. As the gate pulse width was increased from 0.1 to 2 s, the transfer curve shifted in the positive VG direction up to 1 s and then saturated above 1 s. Thus, a gate pulse width of 1 s was selected to obtain the maximum memory window for subsequent measurements. The electrical properties of the CT based on a single-layer MoS2 channel without an AuNP floating gate were investigated. Figure 2e shows the transfer characteristics of the CT. The device exhibited an electron mobility of 18.9 cm2/V·s and an on/off current ratio of ~106. Note that no significant hysteresis was observed during the VG sweep from –10 to 10 V because AuNPs were not inserted between the cPVP and SiO2, in sharp contrast to the characteristics of the MT (see Figure 2a). The CT acted as a switch that connected or disconnected the BL to the gate electrode of the MT. In the on state, the VBL was transferred to the gate electrode of the MT, while in the off state, the VBL could not be transferred to the gate electrode of the MT. In the first investigation, the on and off states were controlled by the VWL. The application of VWL = +10 V turned on the CT, and the MoS2 channel of the CT became conductive, which enabled it to deliver the applied VBL to the gate electrode of the MT for the writing process. By contrast, to read the stored data, the 5



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CT was turned off by application of –10 V at the WL. In the second investigation, the on and off states of the 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

CT were controlled by photo-illumination onto the single-layer MoS2 channel. The direct band gap of single-layer MoS2 (~1.8 eV) enabled a high absorption coefficient and efficient exciton generation under illumination by visible light. The photoluminescence (PL) spectrum of a single-layer MoS2 flake (Figure S4) exhibited a single exciton peak positioned at 676 nm, corresponding to the interband recombination of the photo-generated excitons.35-36 Figure 2f plots the illumination-dependent transfer characteristics of the CT. A focused laser beam with a wavelength of 520 nm and an optical power of 1 mW was directed onto the MoS2 channel region of the CT. The photocurrent in the CT increased significantly under illumination. Incident light with energies exceeding the band gap of single-layer MoS2 excited electrons in the valence band to the conduction band. The photo-generated charge carriers were driven to each electrode by the electric potential applied between the electrodes. The photoresponsivity (R), which is defined as the ratio of the photocurrent to the optical power of the incident light, was calculated to be 0.18 A/W at 0 V and 0.42 A/W at 10 V (Figure S5). The photo-induced on/off current ratio at a fixed VG of 0 V was ~105. These results indicated that light illumination, instead of a voltage applied to the WL, could switch the CT on and off in the 1T1T memory cell for the writing (VWL = +10 V) and reading (VWL = –10 V) processes. The operational stability of the multilevel 1T1T memory cell, which is important for nonvolatile data storage, was investigated using both retention time and cyclic endurance tests. The retention time was characterized by conducting a time-domain measurement. The programming voltage (VBL = +20 V) and erasing voltage (VBL = –20 V) were applied to the BL, and the SL was grounded. The read-out current in each state was measured at VWL = –10 V as a function of the retention time. Figure 3a plots the highly reliable retention properties of five programming states and one erasing state, with retention over 103 s. Negligible degradation was observed after 103 s. Extrapolation of the measured data suggested that the memory window could be expected to extend to a retention time of one year. We performed cyclic endurance tests over repeated multilevel programming/erasing operations (VBL = +14, +18, and +20 V for programming, and VBL = –20 V for erasing, over 1 s pulses). Figure 3b plots the read-out current as a 6


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function of the number of programming/erasing cycles. The device exhibited four well-defined and 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

reproducible level cycles. The read-out current remained constant over 200 cycles with no breakdown. Note that each data storage level of the MoS2 1T1T memory cell was preserved, even after long retention times (exceeding 103 s) and repeated multilevel operations (over 200 cycles). Finally, the dynamic behavior of the 1T1T memory cell was investigated during multiple writing and reading processes. Figure 4 plots the multilevel data storage operation, including five programming states and one erasing state. The CT was switched on/off by controlling both the voltage applied to the word line (upper panel of Figure 4a) and light illumination on the MoS2 channel of the CT (lower panel of Figure 4a). First, +10 V was applied to the WL to turn on the CT (the MoS2 channel was made conductive). The voltage applied to the BL was transferred to the gate electrode of the MT. The VBL was charged to various positive voltages (+12, +14, +16, +18, and +20 V) for programming (Figure 4b). The read-out process was conducted when the CT was turned off (VWL = –10 V). As five programming VBL pulses were applied from +20 to +12 V, the read-out current increased stepwise. Note that the read-out current corresponding to each written state was not affected by the input voltage applied at the BL (indicated by the blue area) because the BL was disconnected from the MT during the read-out process. These results confirmed that the read-out process was independent of the writing process. A negative voltage of –20 V was applied to the BL for erasing at VWL = +10 V. Second, the on and off states of the CTs were controlled by light illumination onto the MoS2 channel of the CT. To turn on the CT, light with a wavelength of 520 nm and optical power of 1 mW was applied in a pulse over 1 s. At the same time, the VBL was charged to the corresponding voltages for the writing (programming/erasing) process. The read-out current was measured at the SL under no illumination. Six-level data storage was achieved over current levels spanning six orders of magnitude at various VBL values. Notably, light-controlled switching of the CT yielded a writing operation in the 1T1T memory cell similar to the voltage-controlled switching of the CT.

CONCLUSIONS

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In conclusion, we fabricated a 1T1T-type MoS2 optoelectronic nonvolatile memory cell consisting 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

of a CT and an MT. This device architecture enabled nondestructive read-out processes by replacing the MC with the MT. The switching of the CT was effectively controlled by both voltage application and light illumination. The resulting 1T1T MoS2 memory cell exhibited excellent memory characteristics: a large programing/erasing current ratio (>106), multilevel data storage (>6 levels), performance stability (>200 cycles), and stable data retention (>103 s). The 1T1T MoS2 nonvolatile memory cell proposed in this study represents a significant step toward future optoelectronic devices based on 2D nanomaterials.

METHODS Au gate electrodes with a thickness of 30 nm were deposited thermally onto a substrate of 300-nmthick SiO2/Si wafers through a shadow mask. An Al2O3 layer with a thickness of 50 nm was then deposited via atomic layer deposition (ALD) as a blocking gate dielectric layer. After cleaning the Al2O3 surface with UV/ozone treatment (254 nm and 28 mW/cm2) for 20 minutes, gold nanoparticles (AuNPs) were deposited thermally on top of the channel region of the memory transistor at a rate of 0.02 nm/s. AuNPs with an average diameter of 9 nm were used as the floating gate of the memory transistor. A solution consisting of 1 wt% poly-4-vinylphenol (PVP, Mw = 20,000 gmol–1) and 0.5 wt% poly(melamine-co-formaldehyde) (PMF, Mw = 511 gmol–1) dissolved in propylene glycol monomethyl ether acetate (PGMEA) was spin-coated onto the substrate. The as-coated film was annealed at 180°C for 150 minutes in a vacuum chamber to form a cross-linked network. A single-layer MoS2 flake (SPI Supplies) was then positioned onto the channel region of both control and memory transistors using a custom-built micromanipulation system. The source/drain electrodes (Cr/Au = 3/30 nm) were patterned by the conventional e-beam lithography technique. The drain electrode of the memory transistor was connected electrically to the gate electrode of the control transistor, and the source electrode of the control transistor was connected electrically to the gate electrode of the memory transistor. A tapping-mode AFM (D3100 Nanoscope V, Veeco) was used to investigate the surface morphology of the single-layer MoS2. Raman and photoluminescence (PL) spectra were measured using a 8


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confocal Raman microscope (Alpha 300R, Witec) and confocal Raman microscopy system (Witec Alpha 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

300 M+), respectively. The electrical properties of the memory cell were measured at room temperature using Keithley 2400 and 236 source/measure units. A monochromatic laser (LATECH) with a wavelength of 520 nm and a power of 1 mW was used as the light source for illumination.

ASSOCIATED CONTENT Supporting Information. The Supporting Information is available free of charge on the ACS Publications website at DOI:

Analysis of the mechanically-exfoliated single-layer MoS2, circuit diagram of 1T1C-type memory cell, and photoresponsivity of MoS2 CT.

AUTHOR INFORMATION Corresponding Author *E-mail: [email protected] Notes The authors declare no competing financial interest.

ACKNOWLEDGEMENTS This work was supported by a grant from the Center for Advanced Soft Electronics (CASE) under the Global Frontier Research Program (2013M3A6A5073177) and Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2017R1A2B2005790 and 2017R1A4A1015400).

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Figure 1. (a) Schematic fabrication procedure of the 1T1T memory cell consisting of a control transistor and memory transistor based on a single-layer MoS2 semiconductor channel. (b) Electrical circuit diagram of the 1T1T memory cell. Lower panel shows a table that describes the writing (programming and erasing) and read-out processes. (c) Optical top-view image and schematic cross-sectional image of the 1T1T memory cell.

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Figure 2. (a) Hysteresis behavior of the memory transistor in the 1T1T memory cell as a function of the VG sweep from ±10 to ±20 V. (b) Shift in the transfer curve after application of various VGs for 1 s. (c) Memory window as a function of programming VG. (d) Shift in the transfer curve after application of programming VG = 20 V for various gate pulse widths. (e) Hysteresis behavior of the control transistor in the 1T1T memory cell under dark conditions. (f) Transfer characteristics of the control transistor before and after light illumination with a wavelength of 520 nm and optical power of 1 mW.

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Figure 3. (a) Retention time and (b) Cyclic endurance tests of the 1T1T memory cell.

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Figure 4. Dynamic behavior of the 1T1T memory cell. (a) VWL and optical power inputs as a function of time (for controlling the control transistor). (b) VBL as a function of time (for programming and erasing). (c) Read-out current as a function of time.

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TOC Figure

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One-TransistorâOne-Transistor (1T1T) Optoelectronic Nonvolatile

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One-TransistorâOne-Transistor (1T1T) Optoelectronic Nonvolatile