Parallel Fabrication of Electrode Arrays on Single-Walled Carbon

Feb 17, 2010 - Parallel Fabrication of Electrode Arrays on Single-Walled Carbon Nanotubes using Dip-Pen-Nanolithography-Patterned Etch Masks...
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Parallel Fabrication of Electrode Arrays on Single-Walled Carbon Nanotubes using Dip-Pen-Nanolithography-Patterned Etch Masks Steve Park, Wechung Maria Wang, and Zhenan Bao* Department of Chemical Engineering, Stanford University, Stanford, California 94305 Received November 3, 2009. Revised Manuscript Received January 29, 2010 This article presents a novel application of using dip-pen nanolithography (DPN) to fabricate Au electrodes concurrently in a high-throughput fashion through an etch resist. We have fabricated 26 pairs of electrodes, where cleanly etched electrode architectures, along with a high degree of feature-size controllability and tip-to-tip uniformity, were observed. Moreover, electrode gaps in the sub-100-nm regime have been successfully fabricated. Conductivity measurements of multiple electrodes in the array were all comparable to that of bulk Au, confirming the reliability and the low-resistance property of the electrodes. Finally, as a demonstration of electrode functionality, SWNT devices were fabricated and the electrical properties of an SWNT device were measured. Hence, our experimental results validate DPN as an effective tool in generating high-quality electrodes in a parallel manner with mild, simple processing steps at a relatively low cost.

The fabrication of nanoscale metallic structures has been of great interest in the research community over the past several decades. Currently, there are many lithographic technologies capable of generating such nanoscale metallic features, each with their set of advantages and drawbacks. Photolithography,1 for instance, is a high-throughput lithographic technique most widely used in the commercial fabrication of transistors and integrated circuits, yet conventional photolithographic techniques suffer from numerous costly processing steps, with the resolution limitation imposed by the diffraction of light. An alternative lithographic method commonly used in the research community is e-beam lithography2 (EBL) because it exhibits a higher resolution limit. However, EBL is a serial lithographic process that is generally expensive to operate and requires substantial maintenance. Microcontact printing,3-5 on the contrary, is a low-cost fabrication technique that is capable of generating metallic features in a massively parallel fashion. However, microcontact printing suffers from a lower resolution limit compared to EBL and precise alignment and registration are difficult. Apart from such conventional techniques, many other unconventional lithographic techniques have been developed to simplify and lower *Address correspondence to [email protected].

(1) May, G. S. Fundamentals of Semiconductor Fabrication; John Wiley & Sons: New York, 2003. (2) Wallraff, G. M.; Hinsberg, W. D. Lithographic imaging techniques for the formation of nanoscopic features. Chem. Rev. 1999, 99, 1801-1821. (3) Kumar, A.; Whitesides, G. M. Patterned condensation figures as optical diffraction gratings. Science 1994, 263, 60-62. (4) Xia, Y. N.; Rogers, J. A.; Paul, K. E.; Whitesides, G. M. Unconventional methods for fabricating and patterning nanostructures. Chem. Rev. 1999, 99, 1823-1848. (5) Xia, Y. N.; Whitesides, G. M. Soft lithography. Angew. Chem., Int. Ed. 1998, 37, 551-575. (6) Dana Alina, S.; Pierpaolo, G.; Sorin, M.; Alexandru, V.; Constantin Augustin, D.; Stefano, Z.; Maria Carmela, I.; Fabio, B.; Massimiliano, C. Towards all-organic field-effect transistors by additive soft lithography. Small 2009, 5, 1117-1122. (7) Kawase, T.; Shimoda, T.; Newsome, C.; Sirringhaus, H.; Friend, R. H. Inkjet printing of polymer thin film transistors. Thin Solid Films 2003, 438, 279-287. (8) Sekitani, T.; Noguchi, Y.; Zschieschang, U.; Klauk, H.; Someya, T., Organic transistors manufactured using inkjet technology with subfemtoliter accuracy. Proc. Natl. Acad. Sci. U.S.A. 2008, 105, 4976-4980.

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processing costs, such as solution-processed additive soft lithography,6 inkjet printing,7-9 lamination,10 and metal-transfer printing,11 each with their set of advantages and disadvantages. Dip-pen nanolithography12-16 (DPN) is a relatively recent lithographic technique used to generate nanoscale metallic structures. DPN uses an “inked” atomic force microscopy (AFM) tip to transfer a material of interest directly onto a surface with sub-100-nm resolution and registration. Such a constructive direct-deposition mechanism under ambient conditions has comparatively milder and simpler processing conditions than other lithographic techniques such as photolithography and EBL, eliminating the need to expose the substrate to harsh conditions such as ultraviolet or e-beam irradiation. Such an attribute, along with its high resolution and low cost of usage,17 positions DPN as an exceptional lithographic tool. One of the most commonly used methods of fabricating metallic nanostructures via DPN is through the deposition of an etch resist. The two most well characterized etch resists used in DPN are 16-mercaptohexadecanoic acid (MHA) and octadecanethiol (ODT). These alkanethiols self-assemble into stable, (9) Gamerith, S.; Klug, A.; Scheiber, H.; Scherf, U.; Moderegger, E.; List, E. J. W., Direct ink-jet printing of Ag-Cu nanoparticle and Ag-precursor based electrodes for OFET applications. Adv. Funct. Mater. 2007, 17, 3111-3118. (10) Loo, Y. L.; Someya, T.; Baldwin, K. W.; Bao, Z. N.; Ho, P.; Dodabalapur, A.; Katz, H. E.; Rogers, J. A. Soft, conformable electrical contacts for organic semiconductors: high-resolution plastic circuits by lamination. Proc. Natl. Acad. Sci. U.S.A. 2002, 99, 10252-10256. (11) Wang, Z.; Yuan, J. F.; Zhang, J.; Xing, R. B.; Yan, D. H.; Han, Y. C. Metal transfer printing and its application in organic field-effect transisitor fabrication. Adv. Mater. 2003, 15, 1009-1012. (12) Hong, S. H.; Mirkin, C. A. A nanoplotter with both parallel and serial writing capabilities. Science 2000, 288, 1808-1811. (13) Hong, S. H.; Zhu, J.; Mirkin, C. A. Multiple ink nanolithography: toward a multiple-pen nano-plotter. Science 1999, 286, 523-525. (14) Liu, X. G.; Zhang, Y.; Goswami, D. K.; Okasinski, J. S.; Salaita, K.; Sun, P.; Bedzyk, M. J.; Mirkin, C. A. The controlled evolution of a polymer single crystal. Science 2005, 307, 1763-1766. (15) Piner, R. D.; Zhu, J.; Xu, F.; Hong, S. H.; Mirkin, C. A. “Dip-pen” nanolithography. Science 1999, 283, 661-663. (16) Haaheim, J.; Eby, R.; Nelson, M.; Fragala, J.; Rosner, B.; Zhang, H.; Athas, G. Dip pen nanolithography (DPN): process and instrument performance with NanoInk’s NSCRIPTOR system. Ultramicroscopy 2005, 103, 117-132. (17) Rosner, B. T.; Demers, L. M. Dip Pen Nanolithography: Applications and Functional Extensions; Taylor & Francis: 2005; pp 1-14.

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well-defined, controllable monolayer geometries onto various metallic surfaces such as gold, silver, and palladium,18 rendering them suitable etch-resistant materials. As a primary exhibition of this methodology, 3D nanoscale gold and silicon architectures were generated through the deposition of ODT using DPN, followed by multistage etching procedures.19 Subsequently, Zhang et al. demonstrated a degree of controllability in the size and geometry of the DPN-generated metallic features by constructing sub-50-nm gold structures of dots and lines using MHA as the etch resist.20 These results along with others21,22 have verified the fundamental feasibility of DPN as an effective tool for fabricating nanoscale metallic structures. In an effort to improve the throughput of DPN while maintaining its high-resolution capacity, parallel lithographic capabilities were engendered with the development of multipen arrays. DPN’s potential for high-throughput nanofabrication was initially demonstrated by the simultaneous generation of eight ODT line patterns on a gold substrate.12 Salaita et al. have successfully scaled up such a proof-of-concept methodology by generating 250 ODT line patterns on a gold substrate.23 Such an exposition of the high-throughput capacity of DPN-generated etch resist patterns brought forth a variety of novel applications. For example, multiple silicon nanostructures were fabricated concurrently using a 26-pen array, prepared by the DPN patterning of MHA with subsequent wet-chemical etching and reactive-ion etching.24 More recently, metal photomasks25 have been developed using the multipen array. In this report, we demonstrate a novel application of using the multipen array to fabricate multiple Au electrodes concurrently through an etch resist. Hence, we open up an alternative method of fabricating electrodes in a high-throughput fashion with a mild, simple processing step at a relatively low cost. Previously, we used DPN to locate SWNTs using a single AFM tip and fabricated electrodes between the SWNTs using MHA as an etch resist.26 The advantage of this approach is that it allowed us to characterize the SWNT to be measured whereas direct EBL on the SWNT typically leaves the SWNT buried under the photoresist. In contrast to this method, which is serial in nature, fabricating the electrodes in a parallel fashion enables the generation of numerous devices in a time-efficient manner, provided that the SWNT density and alignment can be controlled. However, before such a potential can be fully realized, we must consider some of the new challenges that must be addressed for multipen array (18) Zhang, H.; Mirkin, C. A. DPN-generated nanostructures made of gold, silver, and palladium. Chem. Mater. 2004, 16, 1480-1484. (19) Weinberger, D. A.; Hong, S. G.; Mirkin, C. A.; Wessels, B. W.; Higgins, T. B. Combinatorial generation and analysis of nanometer- and micrometer-scale silicon features via “dip-pen” nanolithography and wet chemical etching. Adv. Mater. 2000, 12, 1600-1603. (20) Zhang, H.; Chung, S. W.; Mirkin, C. A. Fabrication of sub-50-nm solidstate nanostructures on the basis of dip-pen nanolithography. Nano Lett. 2003, 3, 43-45. (21) Zhang, H.; Lee, K. B.; Li, Z.; Mirkin, C. A. Biofunctionalized nanoarrays of inorganic structures prepared by dip-pen nanolithography. Nanotechnology 2003, 14, 1113-1117. (22) Zhang, H.; Li, Z.; Mirkin, C. A. Dip-pen nanolithography-based methodology for preparing arrays of nanostructures functionalized with oligonucleotides. Adv. Mater. 2002, 14, 1472-1474. (23) Salaita, K.; Lee, S. W.; Wang, X. F.; Huang, L.; Dellinger, T. M.; Liu, C.; Mirkin, C. A. Sub-100 nm, centimeter-scale, parallel dip-pen nanolithography. Small 2005, 1, 940-945. (24) Zhang, H.; Amro, N. A.; Disawal, S.; Elghanian, R.; Shile, R.; Fragala, J. High-throughput dip-pen-nanolithography-based fabrication of Si nanostructures. Small 2007, 3, 81-85. (25) Jang, J. W.; Sanedrin, R. G.; Senesi, A. J.; Zheng, Z. J.; Chen, X. D.; Hwang, S.; Huang, L.; Mirkin, C. A. Generation of metal photomasks by dip-pen nanolithography. Small 2009, 5, 1850-1853. (26) Wang, W. M.; LeMieux, M. C.; Selvarasah, S.; Dokmeci, M. R.; Bao, Z. A. Dip-pen nanolithography of electrical contacts to single-walled carbon nanotubes. ACS Nano 2009, 3, 3543-3551.

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fabrication that had not been considered for single-pen lithography. For multipen array electrode fabrication, it is of great significance to have precise controllability and tip-to-tip uniformity of the electrode dimensions, along with a high degree of architectural quality and functionality for the entire array of electrodes. These criteria require stringently prepared surfaces and a precisely manipulated DPN deposition process. Hence, this article will address the dimensional manipulability and uniformity of the electrodes and some of the critical procedures for minimizing the number of defects in the electrodes. In addition, we will discuss the gap resolution of our technique. Furthermore, conductivity measurements of multiple electrodes in the array will be presented to affirm the consistency and reliability of the electrodes. Finally, as a demonstration of electrode functionality, the electrical properties of a SWNT device will be presented. We expect that the advancements made for this article will ultimately enable us to develop a generally applicable electrode fabrication methodology in which the gap distances can be controlled from several micrometers to sub-100-nm to generate electrical contacts to various nanostructures of different dimensions in a highthroughput manner.

Methods Substrate Cleaning and Preparation. A silicon oxide wafer with 300 nm thermally grown oxide layers (Silicon Quest International) was diced into 2 cm  1 cm rectangles. The substrates were sequentially sonicated in acetone, ethanol, and isopropanol for 10 min in each solvent. After sonication, the substrates were blown dry with N2 gas and were placed in a UV-ozone cleaner (model 42, Jetlight Company, Inc.) for approximately 45 min to 1 h. Immediately thereafter, the substrates were individually placed into clean glass vials containing 5 mL of a solution of 0.2 vol % 3-aminopropyltrimethoxy silane (APTMS) (Gelest, Inc.) in toluene for 1 h. Subsequently, the substrates were rinsed with toluene, were individually placed in clean glass vials containing 5-10 mL of toluene, and were sonicated again for 10 min to remove any APTMS multilayers. Finally, the substrates were blown dry once again with N2 gas and were placed in a vacuum oven at 90-100 °C for approximately 30 min. For the preparation of substrates without SWNTs, the substrates at this point were ready for Au evaporation. For the preparation of SWNT aligned substrates, first a solution of arc-discharge SWNTs was acquired using a previously developed method27 and was then diluted to 5 μg/mL in NMP (N-methyl-2-pyrrolidone, EMD). Thereafter, the APTMS-coated substrates were spun at approximately 3000 rpm and 30 μL of the aforementioned SWNT solution was dropped approximately onto the center of the spinning substrate using a pipette. After the SWNT solution was dropped, the substrate was allowed to spin for approximately 1 min. This step generated electrically isolated and radially aligned SWNTs on the substrate surface. (See the schematic depiction in Figure 1.) As the final step, the SWNT-coated substrates were placed in a vacuum oven for 2 to 3 h at a temperature of 90-100 °C to completely dry any solvent left on the substrates. The substrates were stored in airtight glass vials. Au Evaporation. Fifteen nanometers of Au was first thermally evaporated onto the substrates at a rate of 0.4-0.6 A˚/s. Thereafter, the substrates were taken out of the evaporator, and metallic shadow masks were clipped onto the substrates, ensuring that the shadow mask was in as close a contacting with the substrate as possible. Metallic shadow masks were rinsed with acetone and dried on a hot plate prior to use. The shadow masks consisted of rectangular patterns of 1 mm  0.1 mm aligned in (27) LeMieux, M. C.; Roberts, M.; Barman, S.; Jin, Y. W.; Kim, J. M.; Bao, Z. N. Self-sorted, aligned nanotube networks for thin-film transistors. Science 2008, 321, 101-104.

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Figure 1. Schematic outline of the parallel electrode fabrication process. First, the substrate was coated with a monolayer of APTMS as an adhesion layer (1). For SWNT device fabrication, SWNTs were applied to the APTMS-coated substrate via spin casting (denoted as an additional step). Second, a uniform layer of Au was deposited throughout the substrate (2), followed by additional Au deposition onto selective regions using a shadow mask (3). Next, MHA was deposited in a parallel manner using DPN (4), and wet-chemical etching was conducted to etch away the unpatterned areas selectively (5). Finally, the electrode pairs of interest were isolated using an x-y stage scriber. parallel along the lateral axis with a spacing of 50 μm. For the substrates with aligned SWNTs, the shadow mask was aligned crudely by hand so that the rectangular patterns were located approximately 0.5 cm from the center of the substrate lengthwise and roughly parallel to the aligned direction of the SWNTs. Finally, after the shadow masks were anchored onto the substrates, the substrates were placed back into the evaporator for an additional 60-70 nm of Au deposition. The resulting substrates had 15 nm of Au throughout with thicker 75-85 nm Au regions. The thicker gold regions later served as pads for electrical probing. Parallel DPN Etch-Resist Patterning. A 26-cantilever array (F-type, A-26 array purchased from NanoInk Inc.) with a tip-to-tip distance of 35 μm was cleaned in a UV-ozone cleaner for 20 min. The array was then submerged sequentially in a 5 mM solution of MHA in acetonitrile, deionized water, and back into the 5 mM MHA solution for a duration of 10 s for each immersion. Between immersions, the cantilever array was lightly blown dry with N2 gas. For the experiments where the same tip array was used repeatedly, the MHA on the cantilever array was cleanly washed and recoated for consistency. Cleaning of MHA on the array was conducted by submerging the array in acetonitrile for 5-10 min to dissolve away the MHA, drying with N2 gas, and by placing the array in the UV-ozone cleaner for 20-30 min. The cantilever array was leveled by observing the overall changes in the reflection of the cantilevers on the optical microscope as the tips contacted the surface and by adjusting the relative positions of the z motors to even out the degree of reflection visually throughout the array.23 Although this is a nonquantitative and subjective procedure, the levelness of the cantilever array was indeed sufficient from experiment to experiment. To be consistent with respect to the force exerted by the tips onto the substrate from experiment to experiment, lithography was conducted in constant-force mode. To attain feedback, the laser and photodetector were aligned to one of the two wider cantilevers on the ends of the array (designed to be wider so that the laser can easily be aligned with the cantilever surface). For a cantilever that is designated to be the feedback pen, through which constant force is monitored Langmuir 2010, 26(9), 6853–6859

during lithography and through which AFM images are taken, the term “reader pen” is also typically used. By using the reader pen, ink diffusivity was calculated by utilizing InkCAD’s inkcalibration (InkCal) feature. With the attained diffusivity constant, the software calculates the corresponding tip speeds for various feature sizes during lithography. The electrodes were designed using the boundary feature in the InkCAD software (employing all default parameters). The width and length of the electrodes were typically designed to be 2.1 and 30.2 μm, respectively, whereas the electrode gaps were designed to be in the range of 250 nm to 1 μm. The relatively large width of the electrodes was to ensure the high yield of our fabrication process. Finally, lithography was conducted with a set-point value of 6-9 V. Au Etching. A modified version of the Fe(NO3)3/thiourea solution28 was used for Au wet chemical etching prepared via a 1:1 mixture of 26.6 mM Fe(NO3)3 3 9(H2O) (J.T. Baker) and 40 mM thiourea (Alfa Aesar) in octanol-saturated H2O. This solution was adjusted to pH 2 by the addition of HCl (15 μL of HCl for a 5 mL Fe(NO3)3/thiourea solution). Au was etched with this solution for approximately 6 min under constant stirring at 100 rpm. Thereafter, the substrate was taken out of the etchant every 20 s, rinsed thoroughly with deionized water, lightly dried with N2 gas, and placed under an optical microscope for visual inspection. Such a meticulous procedure was followed to ensure that the areas in the vicinity of the electrodes were cleanly etched away while maintaining high-quality electrode architectures. Device Characterization. A contact-mode AFM tip with a spring constant of 0.041 N/m (Type A S-1 probe, NanoInk Inc.) was used to image electrodes after the fabrication process. A typical scan range and rate were 5 μm and 10 μm/s, respectively. The AFM images were processed using NanoRule (Pacific Nanotechnology). The devices were isolated using a tungsten scriber on an x-y positioner. The electrical measurements were made using a Keithley 4200 SC semiconductor analyzer. (28) Geissler, M.; Wolf, H.; Stutz, R.; Delamarche, E.; Grummt, U. W.; Michel, B.; Bietsch, A. Fabrication of metal nanowires using microcontact printing. Langmuir 2003, 19, 6301-6311.

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Results and Discussion Surface Treatment and Au Deposition. The quality of the electrodes generated using the multipen array is very dependent on the cleanliness of the substrate before and after Au deposition as a result of the large-area coverage of the patterns. Hence, it is imperative that the substrates are cleaned in a meticulous manner. Contaminants on silicon oxide substrates prevent the homogeneous deposition of Au, which eventually leads to defects on the electrodes. Furthermore, contaminants on the Au surface may prevent the close-packing of the MHA self-assembled monolayer, which enables the chemical etchant to penetrate the MHA patterned areas and cause electrode defects. Prior to the deposition of Au, an adhesive layer must be coated onto the silicon oxide substrate. We have observed that Au deposited directly onto a bare silicon oxide substrate spontaneously delaminates during the wet-chemical etching process. As an adhesive layer, we have coated the silicon oxide surface with a monolayer of 3-aminopropyltrimethoxyl silane (APTMS), where the exposed amine groups adhere to the Au. APTMS is also a material commonly used to adhere SWNTs onto silicon oxide substrates because it enhances the absorption of nanotubes29 and improves the performance of isolated SWNT thin-film transistors as sensors.30 Thus, for the fabrication of SWNT devices, SWNTs were applied to the APTMS-coated substrate via spin casting. The spin-casting methodology, previously developed by our group,27 radially aligns the SWNTs from the initial solution/substrate contact point. Regarding Au evaporation, the purpose of depositing a uniform layer of Au first was to ensure that the DPN-fabricated electrodes made firm electrical contact with the gold pads. Wang et al. have determined that evaporating Au onto pre-existing Au patterns resulted in discontinuities at the edges between the prepatterned and DPN-fabricated electrodes.26 Moreover, the reason for generating such a large height difference between the uniform Au layer and the thicker Au regions was to prevent the complete degradation of the gold pads during the etching procedure. Because a dense array of tips is used for parallel fabrication, there exists MHA vapor in the vicinity the patterning area, yielding a higher degree of nonspecific MHA absorption. Therefore, to etch away the areas between the electrodes sufficiently, the substrates were subject to longer times in the etchant than what was specified by the etching rate of bare Au. Leveling of the Multipen Array. Prior to the DPN lithography process, it is essential to level the multipen array properly onto the substrate to ensure that all pens make firm contact with the substrate and to minimize the variability in the contact force exerted by each tip. As reported previously,23 leveling was conducted by tilting the multipen array using the z motors while monitoring the changes in the color of the cantilevers on the optical microscope, which correspond to the degree of cantilever bending as the tips make contact with the substrate surface. Previous report indicates that the cantilevers in the array are not all in the same plane;23 hence, it is important that a large force is exerted by the reader pen onto the substrate to ensure that all of the tips on the array are making contact with the substrate during lithography. In this regard, we have observed that 6 to 9 V on InkCAD’s setpoint setting exerted sufficient force on the substrate to generate the electrodes consistently in a parallel fashion. (29) Liu, J.; Casavant, M. J.; Cox, M.; Walters, D. A.; Boul, P.; Lu, W.; Rimberg, A. J.; Smith, K. A.; Colbert, D. T.; Smalley, R. E. Controlled deposition of individual single-walled carbon nanotubes on chemically functionalized templates. Chem. Phys. Lett. 1999, 303, 125-129. (30) Auvray, S.; Derycke, V.; Goffman, M.; Filoramo, A.; Jost, O.; Bourgoin, J. P. Chemical optimization of self-assembled carbon nanotube transistors. Nano Lett. 2005, 5, 451-455.

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Feature Size Controllability and Tip-to-Tip Uniformity. The ability to control the feature size accurately is especially important in the fabrication of electronics. Therefore, it is of paramount significance to understand the ways in which the dimensions of the features can be accurately controlled for the parallel DPN fabrication process. Previous work in generating etch resist patterns using DPN has been commonly conducted under ambient humidity and temperature,18,20,23 suggesting that ambient conditions are well suited to feature-size controllability. We have determined that the optimal ambient humidity and temperature of our experimental apparatus was approximately in the range of 40-50% RH and 25 ( 3 °C, respectively. The range of ink diffusivity under these ambient conditions was roughly 0.021-0.050 μm2/s. It is important to note here that the ink diffusivity values did not always correspond to particular values of temperature and humidity. We hypothesize that factors such as the uniformity of ink coating on the tip and the substrate surface quality (i.e., roughness16 and cleanliness) also contributed to the diffusivity value attained. At diffusivities above the optimal range, the dimensions of the electrodes could not be well controlled because of the overdiffusion of MHA. In addition, conducting lithography under high diffusivity resulted in a high level of nonspecific MHA absorption between the electrodes because of the overdiffusion of MHA, rendering it difficult to attain cleanly etched electrode architectures. Similarly, for low diffusivities, not only was the patterning time-inefficient but extensive dwell time over the same area also resulted in a high degree of nonspecific MHA absorption, rendering it difficult to generate clearly resolved electrode architecture. To verify the degree of feature size controllability under the aforementioned ambient conditions, electrodes have been fabricated three times on different substrates using the same multipen array (successively cleaning and recoating the tip before conducting lithography) under different ambient conditions. The resulting ink diffusivities for the three different experiments were 0.024, 0.037, and 0.047 μm2/s, corresponding to the lower end, middle, and upper end of the optimal ambient diffusivity range. The diffusivities were obtained by calculating the ink diffusivity of the reader pens using the ink-calibration feature (InkCal) in the InkCAD software. While calculating the ink diffusivities, we have noticed that the calibration features generated by the reader pen increased over time because of the heating of the cantilever surface by the aligned laser. Therefore, after an extended period of time (∼1 to 2 h), calibration features generated by a pen other than the reader pen should be measured or the reader pen itself should be changed to another pen in the array before ink calibration is conducted. Both methods effectively circumvented the issue and resulted in relatively accurate calibration features. Figure 2B depicts the electrode design used for these experiments. These designs were made using filled-in polygons (i.e., boundaries) in the InkCAD software; default filling parameters were used where parallel 100 nm lines were patterned at a spacing of 100 nm from center to center. The electrode width was designed to be 2.1 μm. Figure 2 also shows the optical images of the multipen-generated electrodes at an ink diffusivity of 0.037 μm2/s (A1, A2) and a topographic image of one of the electrodes (A3). Evidently, the electrodes for the most part were evenly and cleanly etched; similar results were obtained when using the other two ink diffusivities. Figure 2A4 is the height profile of the topographic image, which was attained by averaging three line profiles at various places along the image. This profile demonstrates the smoothness of the electrode surface, confirming that the MHA patterns have been densely self-assembled, effectively shielding Au from the chemical etchant. Langmuir 2010, 26(9), 6853–6859

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Figure 2. (A1, A2) Optical images of the electrodes fabricated using a 26-pen array at a diffusivity of 0.037 μm2/s. (A3) Topographic image of one of the electrodes in the array and (A4) the height profile of the topographic image. (B) Depiction of the electrode design generated with the InkCAD software (NanoInk Inc.). The width of the designed electrode was 2.1 μm, and the length was 30.2 μm. The lateral gap between the electrodes was designed to be 400 nm.

After the electrodes were fabricated, the widths of the electrodes on each of the arrays were measured using AFM. We have obtained average electrode widths of 2.150, 2.137, and 2.188 μm for the three different arrays patterned at ink diffusivities of 0.024, 0.037, and 0.047 μm2/s, respectively. This demonstrates DPN’s capability to attain relatively accurate feature dimensions generated in a parallel manner. The slight deviation of the average feature dimensions from the design dimensions (2.1 μm) may be due to the fact that the ink diffusivity calculated from one of the tips in the array is not necessarily the average ink diffusivity of all of the tips on the array, which intrinsically generates inaccuracy in the dimensional predictability of the parallel lithographic process. In addition, error could have occurred during the ink-calibration procedure (i.e., in measuring the line widths), which would result in an imprecisely attained ink diffusivity constant. Hence, an increase in the overall electrode dimensions would have resulted from the overlapping of the MHA patterned areas, which causes the diffusion of a second layer toward the unbound gold binding sites, on top of the already immobilized first layer.31,32 Nevertheless, experimental results indicate that the dimensional increase in the electrodes is minor and is reasonable for feature-size controllability. The standard deviations of the electrode widths generated by each tip in the array were 0.044, 0.039, and 0.061 μm for ink diffusivities of 0.024, 0.037, and 0.047 μm2/s, respectively. Furthermore, the standard deviations of the electrode widths generated from two other cantilever arrays were calculated to be 0.104 and 0.074 μm. This yields a standard deviation in the range of approximately 1-5% of the designed pattern widths for the three cantilever arrays that we have tested. Such tip-to-tip feature size variability can be attributed to the variability in the Au (31) Basnar, B.; Willner, I. Dip-pen-nanolithographic patterning of metallic, semiconductor, and metal oxide nanostructures on surfaces. Small 2009, 5, 28-44. (32) Jang, J. Y.; Hong, S. H.; Schatz, G. C.; Ratner, M. A. Self-assembly of ink molecules in dip-pen nanolithography: a diffusion model. J. Chem. Phys. 2001, 115, 2721-2729.

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etching process, tip morphology, and ink coating.33 Nevertheless, our results indicate reasonable variability in the feature dimensions from tip-to-tip, validating the geometrical consistency of the patterns generated in a parallel manner. Gap Resolution of the Parallel Electrodes. It is of great interest to know the resolution limit of the DPN-generated electrode gaps fabricated in a parallel manner. In contrast to the previously attained nanogaps that have been fabricated by spacing two patterns aligned along the same axis,20 we have acquired gaps in the lateral direction from two electrodes aligned along two parallel axes. In an attempt to obtain gaps in the sub100-nm regime, the electrode gap was designed at 250 nm to account for the slight increase in the electrode widths due to the overdiffusion of MHA. In this regard, the design gap was roughly estimated on the basis of the previously attained average percent increase and the standard deviation of the electrode widths. Figure 3 shows electrodes with some of the smallest gaps attained, the minimum being 35 nm. Overall, the average gap distance for all 26 electrodes in the array was 110 nm with a standard deviation of 37 nm, where 5 of the 26 electrodes were shorted. Our experiment verifies DPN’s fundamental capability in attaining lateral gaps in the sub-100-nm regime. Nevertheless, it was challenging to obtain clearly resolved sub-100-nm gaps for all of the electrodes in the parallel array. Such a limitation in attaining clearly resolved sub-100-nm gaps for the entire array was first due to the inexactness in the feature-size predictability and the variability of the feature dimensions from tip to tip; as the gaps got smaller, the inaccuracy in such factors became more of an issue, resulting in some of the electrodes in the array being shorted. Second, the gap resolution was limited by the asperity of the electrodes. We speculate that the asperity originates from the nonlinearity of the MHA patterns at the edges of the electrodes, the roughness of the Au layer, and the unevenly etched Au layer. (33) Salaita, K.; Wang, Y.; Fragala, J.; Vega, R. A.; Liu, C.; Mirkin, C. A. Massively parallel dip-pen nanolithography with 55 000-pen two-dimensional arrays. Angew. Chem., Int. Ed. 2006, 45, 7220-7223.

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Figure 4. (A) Optical image of a DPN-fabricated Au line. The dimensions of the Au line were measured, where the width, length, and thickness of the electrode were 2.1 μm, 37.45 μm, and 16.25 nm, respectively. (B) Corresponding IDS vs VDS curve.

Figure 3. AFM images of some of the smallest lateral gaps fabricated via DPN, with a minimum lateral gap of 35 nm. The electrodes were designed to be 1 μm in width. The scale bars are 1 μm. These results demonstrate the fundamental capability of DPN to attain sub-100-nm electrode gap resolution.

Functionality of the Electrodes. To verify the low resistivity of the electrodes, 26 Au lines (fabricated continuously without a gap) with a design width of 2.1 μm were fabricated in parallel between two large gold pads. Subsequently, each of the Au lines was isolated using an x-y stage scriber. Figure 4A is an optical image of one of the Au lines that was fabricated and isolated. Thereafter, conductivity measurements were taken on 10 of the 26 electrodes selected at random. For each electrode, the dimensions were measured and the resistances were calculated using 6858 DOI: 10.1021/la904170w

their corresponding IDS versus VDS curves. The attained average conductivity was 2.27  107 S/m with a standard deviation of 2.87  106 S/m. This conductivity was in the range of 2  107-3  107 S/m for the 10 electrodes that were measured. Such a conductivity range was similar to the conductivity of bulk gold at 20 °C, 4.09  107 S/m, affirming the low-resistivity property of the electrodes. In addition, a high degree of consistency in the conductivity values is evident, confirming the dependability of the electrodes fabricated in a parallel manner. To generate SWNT devices, the electrodes were designed with a lateral gap to allow SWNTs to connect the gaps probabilistically (the electrodes depicted in Figure 2). Figure 5A,B depicts a topographical image of an SWNT device and its corresponding IDS versus VDS curve, respectively. The inset within the topographical image is the corresponding error image that further verifies the SWNT contact between the electrodes. Also, on the topographical image, the radial alignment of several SWNTs is evident, verifying the efficacy of the SWNT spin-casting process. In considering the IDS versus VDS plot, although the current was modulated by VG, the device did not turn off even at VG = 10 V, indicating semimetallic behavior. Using the IDS versus VG plot (Figure 5C), the transconductance for this device was calculated (dIDS/dVG) to be 1.71  10-8 S at VDS = -0.5 V. This value is an order of magnitude higher than the previously attained transconductance value for a single SWNT device fabricated via e-beam lithography,34 suggesting that our device is composed of a bundle of SWNTs. Upon AFM analysis near the SWNT area, the z range was at approximately 3.5 nm. Hence, we speculate that the SWNT device is composed of a bundle of two to three SWNTs. The results presented above validate the reliability and the lowresistivity property of the electrodes and their applicability in measuring the electrical properties of SWNTs. Regarding SWNT (34) Martel, R.; Schmidt, T.; Shea, H. R.; Hertel, T.; Avouris, P. Single- and multi-wall carbon nanotube field-effect transistors. Appl. Phys. Lett. 1998, 73, 2447-2449.

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between SWNTs. Here, the advantage is that one can target a specific SWNT on a substrate. Alternatively, with parallel electrode fabrication methodology, SWNT devices are generated by probabilistically placing one SWNT between each of the electrode pairs. Therefore, although it is not possible to target specific SWNTs using the multipen array, the parallel fabrication methodology can generate numerous devices per lithographic event by properly adjusting the SWNT linear density and the relative positions of the electrode pairs. This poses a great advantage over serial single-pen methodology where the number of devices fabricated proportionally increases the fabrication time. Efforts are currently underway to improve our fabrication process further. For example, using parylene shadow masks,35 a clearly resolved channel length of 10 μm between large gold pads is possible, which would reduce the patterning time. Such spatial resolution would also enable the gold pads to be separated laterally along the direction of the tip array, removing the need to isolate the devices physically using a scriber. Moreover, the statistical optimization of SWNT devices is currently underway to enable the generation of numerous SWNT devices in a highthroughput fashion.

Conclusions In this report, we have demonstrated parallel electrode fabrication using dip-pen nanolithography. We have verified that cleanly etched electrodes can be fabricated concurrently with a high degree of feature-size controllability and with a low level of electrode defects. The optimal diffusivity range was determined to be 0.021-0.050 μm2/s, where the feature dimensions deviated slightly from the design dimensions. The standard deviation of the feature dimensions from different tips in the array was determined to be 1-5%, confirming a relatively low degree of variability in the feature dimensions from tip to tip. Regarding the gap resolution, sub-100-nm lateral gaps have been fabricated, with a minimum lateral gap of 35 nm. Conductivity measurements, conducted for multiple electrodes in the array, were determined to be in the range of 2  107-3  107 S/m, which is comparable to the conductivity of bulk Au. In addition to the electrode conductivity measurements, a semimetallic SWNT device was located and characterized, validating both the reliability of the electrodes and their applicability in measuring SWNTs.

Figure 5. (A) AFM topographical image of an SWNT device. The inset within the topographical image is the corresponding error image. The scale bar is 1 μm. (B) Corresponding IDS vs VDS curve and (C) IDS vs VG curve. The channel length for this device was 728 nm.

device characterization, similar results have been obtained previously26 using a single pen to locate SWNTs on a substrate and subsequently using MHA as an etch resist to generate electrodes

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Acknowledgment. We thank M. LeMieux and S. Barman for providing the carbon nanotube solutions. We also thank R. Stoltenberg for helpful discussions. This work is supported by a Stanford Graduate Fellowship, an NSF Graduate Research Fellowship, and the NSF-NIRT program. (35) Selvarasah, S.; Chao, S. H.; Chen, C. L.; Sridhar, S.; Busnaina, A.; Khademhosseini, A.; Dokmeci, M. R. A reusable high aspect ratio parylene-C shadow mask technology for diverse micropatterning applications. Sens. Actuators, A 2008, 145, 306-315.

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