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Patterned Peeling 2D MoS off the Substrate Jing Zhao, Hua Yu, Wei Chen, Rong Yang, Jianqi Zhu, Mengzhou Liao, Dongxia Shi, and Guangyu Zhang ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.6b04896 • Publication Date (Web): 17 Jun 2016 Downloaded from http://pubs.acs.org on June 21, 2016
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ACS Applied Materials & Interfaces
Patterned Peeling 2D MoS2 off the Substrate Jing Zhao1,2†, Hua Yu1†, Wei Chen1,3, Rong Yang1, Jianqi Zhu1, Mengzhou Liao1, Dongxia Shi1 and Guangyu Zhang1,4,5* 1
Beijing National Laboratory for Condensed Matter Physics and Institute of Physics,
Chinese Academy of Sciences, Beijing 100190, China 2
Beijing Institute of Nanoenergy and Nanosystems, Chinese Academy of Sciences,
Beijing 100083, China 3
College of Physics and Electronic Information, Gannan Normal University, Ganzhou,
Jiangxi 341000, China 4
Collaborative Innovation Center of Quantum Matter, Beijing 100190, China
5
Beijing Key Laboratory for Nanomaterials and Nanodevices, Beijing 100190, China
†
Authors contributed equally to this work.
* Authors to whom correspondence should be addressed. E-mail:
[email protected].
Abstract: The performance of two-dimensional (2D) MoS2 devices depends largely on the quality of the MoS2 itself. Existing fabrication process for 2D MoS2 relies on lithography and etching. However, it is extremely difficult to achieve clean patterns without any contaminations or passivations. Here we report a peel-off pattering of MoS2 films on substrates based on a proper interface engineering. The peel-off process utilizes the strong adhesion between gold and MoS2 and removes the MoS2 film contact with gold directly, leading to clean MoS2 pattern generation without residuals. Significantly improved electrical performances including high mobility ~17.1 8.3 cm2/Vs and on/off ratio ~5.6
3.6
106 were achieved. Such clean fabrication
technique paves a way to high quality MoS2 devices for various electrical and optical applications. Keywords: MoS2, chemical vapor deposition, peel-off, interface engineering, field effect transistors
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Two-dimensional (2D) materials emerge as a new class of materials containing a single layer of atoms. Representative 2D materials are graphene and transition metal dichalcogenides (TMDCs), which have attracted the most attention so far in this community.1-10 Due to their extraordinary mechanical, electrical and optical properties, 2D materials show great promise for a wide range of device applications.11-20 The realization of such devices usually requires a micro-fabrication process in which patterning and etching are commonly involved. An etching process, either wet or dry, is used to remove unwanted layers from the substrate surface during manufacturing. An ideal etching process targets to a complete removal of the materials without damaging the underlying or masking layers; however, such process is extremely challenging. Besides, it is also very difficult to achieve clean patterns without any contaminations or passivations in commonly used etching process,21-23 e.g. the reactive ion etching (RIE); while these contaminations or passivations are the well-known source of the quality degradation for various 2D materials in a device due to their ultra-thin nature. Considering a 2D material on certain substrates (e.g., SiO2), the interaction between them is usually referred to as van de Waals interaction. This weak Van de Waals interaction has been widely used to facilitate the exfoliation of various 2D materials from their bulk forms.24,25 In principle, we could also peel a 2D material off the substrate using an overlay layer if the interaction between them is larger than that between the 2D material and the substrate. In this paper, we introduce a selective peel-off of the monolayer or few layer MoS2 for patterning to bypass the commonly used etching process. Based on proper interface engineering, this selective peel-off process can completely remove the unwanted MoS2 with a nanometer scale precision while not cause damages to the underneath substrates. This fabrication process is also dry and clean, avoiding contaminations or edge passivations to MoS2; as a result, the performance of the MoS2 field effect transistors improves significantly including the mobilities and on/off ratios. In this study, we choose MoS2 for experiments because: 1) MoS2 and graphene are the only two 2D materials available so far for large scale fabrication; 2) MoS2 is much weaker than graphene in terms of the in-plane mechanical strength, facilitating a easier tearing off along certain crystallographic orientation. Our MoS2 film samples were grown on 300nm-SiO2/Si(heavily p doped) or sapphire substrates by the CVD method.26,27 These films are polycrystalline with the average grain size of ~1 µm (refer
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to the atomic force microscope (AFM) image shown in Figure S1). Such clean, 100% coverage, uniform and large scale MoS2 films on SiO2 substrates are thereafter used for selective peel-off. The selective peel-off process is depicted in Figure 1. Firstly, 60nm-thick poly(methyl methacrylate) (PMMA) is spin-coated on a continuous MoS2 film grown on the SiO2 substrate (Fig. 1a-b); a standard electron beam (e-beam) lithography is then followed to produce a mask pattern (Fig. 1c). Secondly, 20nm-thick gold film is deposited on the mask by e-beam evaporation (Fig. 1d). After metal deposition, a thermal release tape (NITTO) is stuck to the surface smoothly and then peeled off (Fig. 1e). To ensure the tape completely contact to the metal film, we need to stick the tape to the sample surface along one direction slowly and press the tape by fingers gently. Note here the peel-off is carried out in ambient conditions. After peel-off, those areas with MoS2 directly contacted with Au can be completely removed from the SiO2 substrate; while the MoS2 pattern under the PMMA resist mask remains (Fig. 1f). This selective removal of MoS2 from the substrate is resulted from the competition of binding energy (f) between different interfaces; in the present case, fAu-MoS2 > fSubstrate-MoS2 > fPMMA-MoS2. Fig.1 g&h show the optical images of the sample surface after process d and e, respectively. We designed a series of MoS2 stripes with width varying from 100 nm to 1 µm and the peel-off process can be always successfully achieved. In Fig. 1i the AFM image shows that the width of ribbons is ~100 nm, which is consistent with the designed width of 100 nm. In addition to gold, we also tested other metals in the patterned peel-off process and find that the success is case dependent. For example, we tried Ti but failed (Figure S2). It is also worth noting that, after peel-off, the PMMA resist on the surface of the MoS2 is also removed completely, leaving a clean MoS2 surface. In contrast, PMMA resist residues can be clearly seen on the MoS2 surface if using a standard e-beam lithography and RIE etching technique for patterning; the AFM image of a typical sample from such fabrication process is shown in Fig. S1(b). To fabricate the MoS2 field effect transistors (FET), another lithograph followed by 2nm Ti/30nm Au deposition and acetone lift-off process formed source-drain electrodes. As we all know that the Raman and photoluminescence (PL) spectrum are sensitive to the quality of monolayer MoS2. Fig. 2a and b showed the contrast Raman and PL spectra of MoS2 before and after patterning. The two major Raman peaks at ~385 cm-1 (E2g) and ~404 cm-1 (A1g) have no obvious changes, suggesting a preserved
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quality of the film after patterning. The frequency difference between A1g and E2g modes △~19 cm-1 is a clear signature of the single layer.28,29 Besides, the PL peak positions at ~1.9 eV and have no shift, separation and broadening after pattering, which is also a clear indicator of no residuals on the MoS2 surface after Au peel-off process. In contrast, the PL of the sample from RIE-based patterning process shows clear quenching and red shift, which possibly caused by the adsorption and damage during the RIE and photoresist removal process.30 To confirm this method is not limited by the shapes and sizes of the pattern, we fabricate a series MoS2 patterns with the line width varying from sub-100 nm to tens of microns (Fig. 2(c)). The zoom-in image of Fig. 2 (d) and (e) shows an “IoP” logo with smooth edges after peel-off. The Raman and PL mapping of this logo is shown in Figure 2(f) and (g). The spatially uniform signals also confirm that our method is clean and efficient. To confirm the high quality of MoS2 after peel-off patterning, we thus fabricated a series of FET devices. Similar devices were also fabricated by standard lithography and RIE process for control samples. In order to exclude the sample-to-sample variations, we cut the raw MoS2/SiO2 film into two pieces and excute the same device fabrication process except for the patterning step. Electrical measurements were performed by Agilent 4156C semiconductor parameter analyzer at room temperature. Prior to measurements, devices were annealed at 300 ℃ in Ar atmosphere for 2h to remove the surface adsorptions. Fig. 3(a-d) show the typical transport characteristics of two different devices in which (a) and (b) are from control samples. For the output characteristic curves shown in (a) and (c), the source-drain current changes linearly with the voltage (Vsd) under the gate voltage (Vg) varying from 70V to -70V, demonstrating nearly ohmic contact for both devices. In addition, the current saturation of these two devices can be easily obtained at Vsd
