Polymer-Based Gate Dielectrics for Organic Field-Effect Transistors

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Review

Polymer-based Gate Dielectrics for Organic Field-effect Transistors Yuxin Wang, Xingyi Huang, Tao Li, Liqiang Li, Xiaojun Guo, and Pingkai Jiang Chem. Mater., Just Accepted Manuscript • DOI: 10.1021/acs.chemmater.8b03904 • Publication Date (Web): 11 Mar 2019 Downloaded from http://pubs.acs.org on March 11, 2019

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Chemistry of Materials

Polymer-based Gate Dielectrics for Organic Field-effect Transistors Yuxin Wang1, Xingyi Huang1*, Tao Li2*, Liqiang Li3, Xiaojun Guo4, Pingkai Jiang1 1Department

of Polymer Science and Engineering, Shanghai Key Laboratory of Electrical Insulation and Thermal Ageing, Shanghai Jiao Tong University, Shanghai 200240, China 2Department of Chemistry, Shanghai Jiao Tong University, Shanghai 200240, China 3Institute of Molecular Aggregation Science, Tianjin University, Tianjin, 300072, China. 4Department of Electronic Engineering, Shanghai Jiao Tong University, Shanghai 200240, China *Corresponding to X.H. (E-mail: [email protected]) or to T.L. (E-mail: [email protected]) Abstract: Polymer-based gate dielectrics have received growing attention due to their important role in field-effect transistors (OFETs). This review article aims to present the recent progress of polymer dielectrics for high-performance OFET applications. We first discuss the requirements for polymer dielectrics in tailoring the overall performance of OFETs from the perspective of both bulk material properties and surface characteristics of the polymers. On this basis we introduce the design strategies and desired processing techniques of polymer dielectrics for optimizing the charge transport and stabilizing the operation of OFETs. Then we highlight the recent advances in polymer-based dielectrics by classifying and comparing different categories of polymeric materials as well as polymer nanocomposites, and focus is also given to elucidating the critical relationships between polymer structures, gate dielectric properties and OFET performance. Finally, a perspective of future research directions and challenges for polymer dielectrics is provided.

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1. Introduction Organic field-effect transistors (OFETs) are key units to construct flexible and printable devices for applications including flexible displays, chemical sensors, wearable devices, radio frequency identification (RFID) tags, etc.1-6 They have attracted ever-growing attention over the past several decades. Figure 1 illustrates four typical device structures of OFETs. Among them, bottom-contact structures are more commonly used, and they are more applicable for large-scale production.7-9

Figure 1. Schematic of four typical OFET structures. Dielectric layers in OFETs play a very important role in the functioning of the devices. A variety of dielectric materials including inorganic, organic and self-assembled mono-/multilayer dielectrics have been studied and the interested readers can refer to earlier reviews on research progresses.9-13 Among diverse materials for choice, polymer-based gate dielectrics with functional molecular structures and intrinsic flexibility offer natural compatibility with both organic semiconductors and plastic substrates in constructing OFETs. And beyond that, they can be processed with more energyefficient methods such as solution-processing techniques at low temperatures11, 14-15 compared with their inorganic counterparts that normally need to be processed by e-beam or sputtering methods.16-17 More significantly, the structure of polymers can be easily tailored by molecular design and chemical 2


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synthesis, which enables easy functionalization of the dielectric layer to serve wide varieties of purposes, such as bio-sensors, stretchable electronics and so on. This characteristic of polymer dielectrics also offers the feasibility of comprehensive mechanism studies of device physics by only a slight modulation of chemical structures.18-19 On the other hand, however, polymer dielectrics generally exhibits more complexity because of their randomly-ordered structures and much complicated physical properties such as molecular weight (MW), crystallinity, packing mode, glass transition under certain temperatures, etc. And all of them could exert influence on the dielectric properties. At the same time, the surface characteristics of polymer layers will largely determine the growth mode of semiconductors on top of them and thus the charge transport process in devices. To date, it is still highly challenging to accurately clarify how each of the above-mentioned factors influences the OFET performance by ruling out all the other variables. All the above discussion state the importance of a timely and comprehensive review on both design strategies and working mechanisms of polymer-based dielectrics, including the chemical structures, surface physics, dielectric and electrical properties, processing techniques, etc. The polymers to be discussed mainly consist of two types, dielectrics made of pure polymers and the polymer nanocomposite dielectrics. In section 2 and 3, we demonstrate the requirements of polymer gate dielectrics. How the bulk and surface properties of dielectric layers tailor the OFETs’ performance by affecting the charge transport in the semiconductors is highlighted in these sections. After that, processing techniques to achieve high quality polymer dielectrics are discussed in section 3. In Sections 4, we review state-of-the-art progress in polymer-based gate dielectrics, including synthetic polymers (categorized in high-k polymers and low-k polymers), bio-polymers and polymer nanocomposites. Design strategies of chemical structures and mechanism investigation on how they influence charge transport and operational stability are also addressed. The concluding remarks and our perspective on the further development of new polymer-based gate dielectrics are given in the end. Inorganic dielectrics, hybrid dielectrics and self-assembled mono- and multilayer dielectrics are not

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the main focus of this review.

2. Requirements for of Polymer Materials as Gate Dielectrics 2.1 Role of Gate Dielectrics in Modulating Charge Transport Under an applied gate voltage (VG), a conductive channel forms due to accumulation of carriers near the semiconductor-dielectric interface. Then, under an applied source-drain voltage (VDS), the carriers are injected into the semiconductor layer from the source electrode and transport to the drain electrode through the channel, where a source-drain current (IDS) is generated. Although organic semiconductors form the main functional layer in OFET devices, the charge transport occurs in the first few molecular layers the near surface of the gate dielectric, which in consequence plays an important role in influencing charge transport and to a great extent determines OFET performances.2022

Specifically, interfacial behaviors between the dielectric and semiconductor, including surface

properties, dipole disorder and surface charge-trapping sites all have direct influence on the charge transport at the interface.23-24 Surface morphology of gate dielectrics can tune the molecular orientation and crystal growth of organic semiconductors. Functional groups and surface dipoles can trap the injected charges, and dipole disorder can increase the density of states (DOS), which all lead to hysteresis behavior and reduction of mobility. Some surface effects are originated from the bulk properties, and thus can be tuned by changing polymer structures, including composition, packing structure, molecular weight (MW), etc. In addition, the bulk ions or ionic impurities in the bulk are also the source of leakage and hysteresis which should be eliminated. Under some circumstances, however, the ions are introduced purposefully for the electrochemical doping effect. The roles and effects of the gate dielectrics are depicted in Figure 2. The requirements for polymer-based dielectrics are discussed based on these effects.

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Figure 2. (a) Schematic of the semiconductor/dielectric interface and how the dielectric layer influences charge transfer, in which (b) illustrates the bulk properties of the gate dielectrics including polymer matrix and ions in the bulk; the difference in the composition and structure of polymer will also affect the interfacial behavior; (c) illustrates the influence of surface morphology on mobile charge carriers; (d) illustrates random dipoles at the interface of high-k polymers, which may broaden the density of states and (e) indicates the charge trapping sites brought by some functional groups, which will impede charge transport in the semiconductor. 2.2 Dielectric and Electrical Properties If a dielectric material is placed under an electric field, polarization will occur, in which the electrical charges shift from their original positions toward the electric field direction. During this process, there is a delay of the polarization with respect to the changing electric field. This process is named as dielectric relaxation, which gives rise to the dielectric loss (tan δ). Dielectric loss can be viewed as the energy dissipation that comes from dipole relaxation or leakage current.11,

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application in thin-film transistors (TFTs) favors low dielectric loss of the gate dielectrics (typically < 0.01). Both k and tan δ are frequency-dependent, and can be characterized by the dielectric spectroscopy, which probes the interaction of the sample with a time-dependent electric field. Measurement of tan δ is essential not only for the dielectric property, but also for direct characterization of hysteresis. Typically, dielectrics with lower dielectric constants (low-k dielectrics) have lower dielectric loss in comparison with the high-k ones, due to the lower dipole density or the weaker

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polarizability. However, high k dielectrics with low dielectric loss can also be obtained by tailoring the molecular structure or introducing high-k nanodomains, etc.26-27 Dielectric constant is an indication of the capacitance of the dielectric layer (Ci) using twoparallel-plate model: Ci = kε0 / d (1) where ε0 is the vacuum permittivity, k is the dielectric constant of the dielectric, and d is the thickness of the gate dielectric. It can be seen that reducing d or increasing k are two routes to achieving a high Ci. For low-power applications, the critical demand of gate dielectrics is to realize a high output under a low-voltage operation. Equation (2) shows the drain current in the saturation region:28 𝑤

IDS = 2𝐿μCi (VG - Vth)2 (2) In saturation region, drain current (IDS) is proportional to the applied gate voltage (VG) and capacitance, where Ci is the capacitance of the dielectric layer. Since the threshold voltage (Vth), channel width (W), channel length (L) and saturation mobility (μ) are fixed parameters, to effectively reduce VG while achieving a high output, it is important to increase Ci. Efforts have been made to reduce the thickness of the dielectric layer. To overcome the drawbacks accompanied with decreased film thickness, such as decreased film uniformity and pinholes that lead to substantial leakage current, the use of SAMs29-30 and SANDs31-32 were reported. However, the full coverage of an ultrathin self-assembled layer requires additional processing controls and depends strongly on the outside environment and surface corrugation. Furthermore, in the case of solutionbased deposition, the gate dielectric should maintain sufficient thickness to suit the large-area coating technique. In theory, it is easier to increase the capacitance by employing high-k materials as dielectrics. However, there exist some problems in practical applications. For instance, dipole disordering, which occurs in a polar surface, is an important factor that affects the carrier mobility.33 The presence of random dipoles at the semiconductor/dielectric interface broadens the DOS and leads to more tail states 6


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impeding the transfer of charges. It can be explained by the dipole polarization that localizes mobile charges during transport.34 An analytical model was demonstrated by Richards et al.10, 35 to study the interaction of charge and the dielectric environment. They calculated the DOS broadening as a function of the distance from the surface and found that the effect of dipole polarization on mobile charges was most dependent on the nearest dipoles. It was suggested that the use of high-k dielectrics might bring larger disorder and thus result in a decrease in mobility.36 In a recent study by Noh et al. on a carbon nanotube (CNT) network transistor, it was further proved that the mobility decreased from 6.8 to 1.9 cm2 V−1 s−1 along with a decrease in operational stability when using the highly polarizable dielectric P(VDF-TrFE-CTFE) when compared with a fluoropolymer CYTOP because of randomly oriented dipoles37. Different relationships between dielectric constant and carrier mobility appear due to different charge transport mechanisms. Yu’s group38 carried out a systematic comparison of the relationship between carrier mobility and dielectric constant in two different systems, polymer TFTs and singlecrystal OFETs. They used liquids with varying dielectric constants, from oil to ionic liquids, to examine the charge transport under a wide range of capacitances, and the results showed that in polymer-based TFTs, the carrier mobility increased with an increase in gate capacitance, whereas an opposite behavior was observed in single-crystal OFETs. This may be attributed to the different structural orders of polymers and organic semiconductor crystals. Desirable electrical properties of the gate dielectrics include high breakdown strength, low leakage current, etc. A good insulating property is prerequisite for the dielectric layer to ensure the functioning of the OFET. A higher breakdown strength enables a higher electric field to be applied to the device and prevents the electrical breakdown of the material, which is especially important for ultrathin films. Employing gate dielectrics with a good insulating property can also effectively restrict leakage current from the gate and decrease the off-current (Ioff) to reduce the power dissipation of the device.

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Small amount of leakage, even orders of magnitude smaller than the source-drain current will cause irreversible degradation in single-crystal FETs.39 Achieving a large on-off ratio (Ion/Ioff) is essential in desirable performance and operational stability of devices, especially in logic circuit applications.40 Leakage current is generally inevitable, and are related to numerous factors such as the dielectric layer characteristic (e.g. dielectric constant, polymer tacticity), dielectric thickness, electrical property of the semiconductor (e.g. the doping concentration), device structures, etc.41-43 Generally speaking, other desirable properties such as higher dielectric constant and scaling down of dielectric thickness will harm the insulating property. To address this issue, approaches such as using self-assembled monolayers (SAMs) were reported for improvement of thin dielectrics, in which the SAM chains can be viewed as surface-attached electrostatic dipoles that serve as a barriers to reduce the leakage current.44 2.3 Surface Properties The structure of the dielectric/semiconductor interface strongly influences the growth and crystallinity of the semiconductor, and further modifies the charge transfer behavior. Figures 3 and 4 show the molecular structures of organic semiconductors and polymer dielectrics mentioned in this review, respectively.

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Figure 3. Organic semiconductors mentioned in the review.

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(a) Non-cross-linked gate polymer dielectrics

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(b) Cross-linked gate polymer dielectrics Figure 4. Chemical structures of selected dielectric polymers discussed in this review: (a) Non-crosslinked and (b) cross-linked polymer dielectrics.

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It is found that pentacene is very susceptible to surface roughness. Increased surface roughness is detrimental to device performance and can lead to a sharp decrease of mobility. In a study using pentacene as the semiconductor, a decrease in mobility from 0.31 cm2 V−1 s−1 to 0.02 cm2 V−1 s−1 was observed when the roughness increased from 0.2 nm to 1.5 nm rms.45 This phenomenon can be explained by the favorability of molecule surface diffusion on a smooth surface. The long travelling distance of molecules can reduce the number of nuclei formed at the surface, thus generating larger grains.46 A rougher surface is found to result in smaller pentacene crystals, which in turn leads to increased gaps and crystal boundaries, and impedes charge transfer.47,48 The introduction of fluorine atoms in the PI system is reported by Baek et al.49 to improve the crystalline morphology of the semiconductor. The presence of fluorine can enhance the chemical inertness and reduce the polarity of the PI system. As shown in Figure 5, the dielectric film without fluorine atoms exhibited a larger roughness (0.391 nm) than did the other two with six and eighteen fluorine atoms per repeat unit (0.195 and 0.196 nm, respectively). Thus, a large grain size of 950-1000 nm was observed in the fluorinated polymers, compared with a small grain size of 450-450 nm for the non-fluorinated polymer. As a result, the ΔVth under a bias stress was found to be inversely proportional to the number of fluorine atoms, with a minimum of -0.50 V for 6FDA−CF3Bz−PDA PI (Figure 5).

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Figure 5. AFM images of pentacene films of a 50 nm thickness on PI dielectrics: (a) BPDA−PDA−PDA PI, (b) 6FDA−PDA−PDA PI, and (c) 6FDA−CF3Bz−PDA PI. (d)-(f) AFM images of the PI dielectrics according to the order above. (g) IDS−VG transfer characteristics of triethylsilylethynyl anthradithiophene (TES-ADT)-based OFETs with the three dielectrics before and after an applied gate-bias stress of VG = −3V (VDS = 0) for 3 h in N2. (Adapted with permission from ref. 49. Copyright 2014 American Chemical Society) A smooth film morphology without pinholes or defects is preferable to suppress the leakage current and increase mobility. The improved performance is demonstrated for many dielectric selfassembled monolayers or multilayers (SAMs) and self-assembled nanodielectrics (SANDs) because of their well-ordered structures.31-32, 50-54 Polymer-based nanocomposites have larger surface roughness compared to polymer materials due to the presence of nanoparticles (NPs). This is one problem that sets back the application of nanocomposites for their application in FETs. As for possible solutions, the size of the NPs should be as small as possible. Furthermore, an additional layer can be added if necessary. In the work of Kim et al,55 an additional poly(vinyl phenyl) (PVP) polymer buffer layer was employed on a TiO2 nanocomposite dielectric layer to create a smoother surface. The leakage current was effectively suppressed by the buffer layer. In addition to surface roughness, the surface energy or hydrophobicity, surface glass transition temperature (Tg), and phase separation of a blended polymer dielectric also have significant influence on the semiconductor morphology.30, 56-58 The effect of surface energy on semiconductor grain growth has been recognized. However, the direct relationship between surface energy and semiconductor performance is still under debate due to the difference in semiconductor types and fabrication methods, and the complexity of how grain size and boundaries can impact charge transport. Some reports stated that the surface with a lower surface energy led to smaller grain sizes of pentacene, with more interconnections between the grains to enhance charge transport.59 Yang et al.60 reported an increase in pentacene mobility from 0.11 to 0.56 cm2 V−1 s−1, with a decrease in surface energy of 18 mN m−1. Liu et al.61, however, claimed that the deep and dense ground boundaries (in small grains) resulted from low surface energy would decrease the mobility. MW is directly related to the surface energy as shown in Equation 3, where γ is the surface energy 13



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and γ∞ is the dielectric constant under infinite MW, γe is the surface energy of chain ends and m is the molecular weight of one repeat unit. ke = (γ∞-γe)(2m)2/3 𝑘𝑒

γ = γ∞-𝑀𝑛2/3

(3) 62

Liu et al.61 modified the SiO2 dielectric surface with 10 different polystyrene (PS) with MWs ranging from 1.3 kDa to 650 kDa to create samples with varied interface energies. They found that the surface heterogeneity brought about by MW can change the mobility up to 2 orders of magnitude. Moreover, it was reported that different MW would bring about difference in polymer chain ends. However, after eliminating the influence of dielectric surface on semiconductor growth by applying the top-gate architecture in TFTs, Orgiu et al.63 reported that MW only had a subtle influence on major device parameters. Poly(methyl methacrylate) (PMMA) and PS with MW of 4, 50 and 500 kg mol-1 respectively were used in the ambipolar F8BT TFTs. Given that the semiconductor has already been deposited on the same substrate, the surface properties of the dielectric will not affect semiconductor deposition. As a result, they found out that mobility, as well as threshold voltage and other electrical parameters were not influenced notably by MW. Only a general but minimal reduction of ΔVG was found with higher MW. Surface Tg can influence semiconductor microstructure under certain deposition temperatures(TD), which is known as the viscoelasticity phenomenon. A bilayered structure was employed, and glassy polymers with varying bulk Tg were chosen as gate dielectrics, including three kinds of PS with different molecular weights, PMMA and poly(t-butylstyrene) (PTBS).64 In the thermal deposition process of the pentacene semiconductor, a direct correlation was found between TD and mobility. An abrupt drop of μ appeared when TD was near the surface Tg for all dielectrics applied, independent of the dielectric thickness. A drop in carrier mobility of more than 10 times was observed within a narrow TD range for the PS1 dielectric (approximately 59°C). This could be attributed to increased chain mobility of the polymer dielectrics in their rubbery states, which disrupted the growth and ordered 14


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texture of pentacene crystals. In addition to the crystalline behavior of pentacene, there are studies on the relationship between surface energy and crystallization of the solution-casted polymer films.65-66 A D-A conjugated semiconducting polymer DPP2T-TT was studied by Ying et al.66 They found that the impact of surface energy on crystallization lay in the free energy barrier of heterogeneous nucleation. A critical factor ΔGA, the excess free energy per surface area between the surface and nucleus, was introduced to represent the penalty of nucleation. The dependence of ΔGA on other pairwise interfacial free energies is as the following equations: ΔGA= γpolymer-solvent + γsubstrate-polymer - γsubstrate-solvent (4) where γ represents the free energies between nucleus, substrate, and solvent. It was found through experiments that ΔGA decreased with decreasing surface energy of the substrate, which meant a lower free energy barrier to nucleation. This explained the increased crystallinity of DPP2T-TT and the increased hole-mobility by one order of magnitude with the decrease of substrate surface energy from 67.2 to 20.5 mN/m. 2.4 Hysteresis and Bias Stress Effect Bias stress effect describes the change of channel current and shift of Vth under an applied bias. When an electric field is applied perpendicular to the channel direction, charge carriers will migrate to localized states in the dielectrics during prolonged operation periods. As a result, the number of free carriers will decrease and lead to the bias stress instability, which is a critical issue in the device performance, and it sets back the real application of TFTs and their commercialization. The main origins of bias-stress instability are charge injection/trapping (including charge-trapping in semiconductor layer, dielectric layer or at the interface), mobile ions in the dielectric bulk and environmental effects (e.g., water molecules).67-69 Energy barrier between the nearest molecular orbital levels (i.e., the highest occupied molecular orbital, HOMO and the lowest unoccupied molecular orbital, LUMO) of semiconductor and dielectric

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limits the charge transfer from the conductive channel to the dielectric surface under gate-bias stressing. Park et al. 67 studied different gate dielectrics, poly(4-methoxystyrene (PMOS), poly(4-methylstyrene) (PMS) and poly(pentafluorostyrene) (PFS), and applied ultraviolet photoemission spectroscopy (UPS) to characterize the surface electronic structures. As shown in Figure 6 (a)-(c), the PFS sample, which was fluoro-functionalized, showed the highest energy barrier of 3.35 eV compared with the unfluorinated ones. The high energy barrier for charge transfer resulted in a relatively low mobility (0.33 cm2 V−1 s−1), but at the same time, it was responsible for the better gate-bias stability. The ∆Vth was -5.05 V for the PFS-based OFET, while -13.14 V and -9.18 V for the PMOS-and PMS-based OFETs, respectively.

Figure 6. (a)-(c) Band diagram of the interface between semiconductor (pentacene) and the dielectrics. (d)-(f) Transfer characteristics of the OFETs under nitrogen conditions with PMOS, PMS, and PFS dielectric surfaces under VG = –60 V (VDS = 0) from 0-12 h. (Adapted with permission from ref. 67. Copyright 2014 John Wiley & Sons, Inc.). Hysteresis reveals the shifts of threshold voltage during the cyclic sweeps in the transfer curves. With the change of electric field during the on-off process, the remaining polarization affects the charge carriers in the semiconductor and thus influences the channel current, which results in IDS-VG

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mismatch in the forward and reverse gate-bias sweeps (I-V hysteresis). This phenomenon is detrimental to stable and predictable device performance. Firstly, the ferroelectric effect of the dielectrics is one of the origins that contribute to hysteresis. The ferroelectric effect depends on the intrinsic dielectric properties of the gate dielectric, which is determined by the responding time of dipole relaxation versus the field sweep rate. The ferroelectric behavior is unfavorable for OFETs operation, except for the application as dielectric layers in memory devices, such as ferroelectric-gate field-effect transistors (Fe-FETs).70 Cheung et al. managed to separate the ferroelectric behavior from other origins of hysteresis by using a polar polymer, 2,2-bis(3aminophenyl)hexafluoropropane+2,2-bis[4-(4-aminophenoxy)phenyl] hexafluoropropane (LaRCCP1) as the gate dielectric.68 Due to its high Tg (~ 260 ℃), the polymer will not show ferroelectric behavior under room temperature because it lacks spontaneous polarization. By using the low-pressure chemical vapor deposited (LPCVD) n-type poly-Si semiconductor and the 15 nm thick spin-cast polymer film to construct the Fe-FETs, they proved that ferroelectric polarization occurred under elevated temperatures, while at low temperatures the hysteresis was largely dominated by charge trapping and mobile ions. In polymer dielectrics without intrinsic ferroelectric properties, hysteresis is mainly attributed to the charge trapping, like bias stress instability.71-72 The polar groups bring about shallow traps on the interface and can trap charges according to their energy levels. The efficiency of interface charge trapping increases with stronger polarity of functional groups. OFET characteristics of six organic semiconductors on four different SiO2-polymer bilayer dielectric structures were systematically investigated by Yoon et al.73 The electron trapping capability of different functional groups was evaluated and compared to that of hexamethyldisilazane (HMDS)-functionalized and pristine SiO2 dielectrics (Figure 7). Among them, the PSn top layer showed significant reduction in interface traps, which could possibly be explained by the stabilization of charge carriers by aromatic cores. The PSOx displayed the highest trap density with all kinds of semiconductors studied (>1013 cm2), higher than

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the bare SiO2 surface (~1012 cm2). They also found that the electron trapping is related to the LUMO energies of n-type semiconductors and ambient sensitivity. The moisture-absorption ability of the functional groups will also influence charge trapping behavior.

Figure 7. Schematic diagram of functional group electron trapping efficiency on various bilayered dielectrics. Adapted with permission from ref. 73. Copyright 2006 American Chemical Society. Polymer backbone structures as well as the pinholes and defects that are introduced during film formation could also serve as charge trapping sites. Lee et al.74 investigated the OFET operation stability as a function of polymer stereostructures. In the study, isotactic, syntactic and atactic poly(methyl methacrylate) (PMMA) with identical MW and polydispersity were selected as the dielectric. A sustained VG of −40 V and VDS of −5 V were applied to the devices for over 2 h. The isoPMMA showed most stable device operation under bias stress. It had an ID decay of 51% from the initial value compared to 71% and 88% in the syn- and a-PMMA, respectively. The results indicated that using polymers with more closely-packed chains can improve the operation stability, because a more regular stereostructure have less free volume that can serve as charge-trapping sites. The charge trapping behavior of polymer branched segments was investigated by Lee et al.75 In the study, a branched polystyrene (b-PS) and a linear polystyrene (l-PS) were compared. Timedependent ΔVth tests were carried out to study the charge trapping mechanism under a bias stress, and deeper traps were found in the PS with a higher density of branched segments. Same as the

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stereostructure-dependence, the branched segments in a polymer chain created more disorder and free volume that produced intrinsic charge-trapping sites around them in addition to the surface charges (Figure 8). Because the density of chain ends is inversely proportional to the MW, using polymer dielectrics with high MW can improve the bias stress stability.

Figure 8. (a) Chemical structures of l-PS and b-PS used in the study. (b) Schematic diagram of the charge trapping at the branched segments in polymer gate dielectrics. (c) Time-dependent ΔVth for pentacene FETs based on gate dielectrics with different blending ratios: b-PS/l-PS = 0/100 (B0L100), 50/50 (B50L50), and 100/0 (B100L0). A bias stress and then a recovery process were performed under vacuum. (Adapted with permission from ref. 75. Copyright 2015 American Chemical Society.) Besides, the transport of charges in the bulk of the dielectrics are also responsible for those instable effects.63 Mobile ions in dielectrics may defuse into the semiconductor layer under an applied voltage and alter the performance of the device, resulting in bias stress instability.76-77 Egginger et al.78 investigated the influence Na+ in poly(vinyl alcohol) (PVA) dielectrics. They compared two different grades of PVA as gate dielectric, including an “electronic-grade” PVA with a NaAc content < 0.09 wt %, and a further purified PVA with the NaAC content < 0.004 wt %. The cyclic transfer curves of the C60 transistors confirmed the direct increase of hysteresis with increasing impurity ion levels. To cope with the charge injection into the PVA bulk, Park et al.

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proposed a deposited SiO2

layer by PECVD technique between a crosslinked PVA dielectric and the gate electrode. The SiO2 served as a charge blocking layer to prevent the charge injection from the gate electrode. Furthermore, they tested the pentacene OFETs with varying SiO2 layer thickness of 100, 350, 700 and 1000 Å for 19



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the minimized hysteresis.80 The most effective charge block was found with the SiO2 thickness of 350 Å. It was interpreted that the SiO2 with thickness of 100 Å was insufficient in blocking the injected charges, and a positive Vth shift remained. And when the blocking layer gets thick enough, the trapped holes may take the primary role and result in increased negative Vth shift. As a brief conclusion, the hysteresis and gate-bias instability can be mitigated by creating a more inert surface, reducing the dipole concentration of the polymer, applying polymers with higher MW, lower density of mobile charges and less free-volume structures.

3. Processing Techniques Achieving smooth and pinhole-free dielectric layers is very important in the fabrication of highperformance OFET devices. Benefiting from low cost production of large-area films under mild conditions, solution methods are the most widely used processing techniques for polymer-based dielectric films. Of all the solution-processing methods, spin-coating is applicable to almost all kinds of polymer materials. The production of high-quality films with ideal thickness and flatness by spincoating calls for the proper choice of solvent, spinning speed and solution concentration according to the characteristics of both the substrate and dielectric material. To be specific, careful choice of orthogonal solvents for both good solubility of the polymers and processing compatibility with the neighboring layers (e.g., semiconductors) during the layer-by-layer deposition is particularly important.81 Another promising solution processing technique is ink-jet printing. It is a highly adjustable and flexible method for various tailor-made devices and scalable production.6 In order to develop suitable ink and to modulate the process, dynamics of jet formation (including the surface and viscosity of the ink) and ink rheology need to be taken into consideration. These aspects are more thoroughly discussed in the book chapters of large area and flexible electronics by Noh et al.82 More importantly, ink-jet printing is an indispensable way to realize patterned dielectrics.83-84 Patterning of the dielectric layers

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enables the accurate ink-jet printing of the upper semiconductor layer and helps realize an exact channel length.85 Patterning for the channel layers can eliminate parasitic leakage and benefit the circuit integration application of thin film transistors.86 Various patterning techniques were demonstrated, such as laser patterning,87 self-organization88 and dry-etching.89 Recently, Guo et al.88 reported a patterning process for all-solution processed OTFT dielectric layers in a BG-BC organic thin-film transistor (OTFT) architecture by controlling the wettability of the dielectric surface. It was a simple process to realize accurately printed electrodes and well-patterned channels at the same time. A novel dry-etching patterning without the removal of a CYTOP protective layer was also reported90 which increased the ON/OFF ratio to approximately 108. In addition to the solution methods, chemical vapor deposition (CVD), which is commonly known as the processing method for semiconductor materials (small molecules and materials insoluble in organic solvents), can also be used for the preparation of polymer dielectric layers.91 The CVD technique can realize the production of ultrathin pinhole free films with good uniformity. The basic idea of the CVD-related techniques for polymers is to let the monomers polymerize at the same time with the deposition process. As a result, ultrathin films can be obtained with higher quality compared to those from solution methods. Meanwhile, the application of this technique has theoretically no limits regarding the polymer types, as long as the polymerization condition can be screened to suit the equipment and processing route. The most widely studied class of CVD-coated polymers is parylene and its derivatives. Shtein et al.92 reported the chemical vapor jet deposition of parylene polymers, which resulted in conformal coverage of features at room temperature and under air condition. This process included the vaporization and pyrolysis of the di-p-xylylene (parylene dimer) in a single compact nozzle, producing a jet of monomer that polymerized into a film towards the substrate in contact. Various examples of CVD-processed polymer thin films have been reported, including conjugated polymers (e.g., poly(pyrrole) and poly(thiophene)),93 poly(ethylene glycol) (PEG) for biological application,94 poly(isobenzofuran) and polymers of other kinds.95

21



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Initiated chemical vapor deposition (iCVD) technique is a technique particularly applied to the polymers that can be synthesized by free radical polymerization. It is beneficial to low-k dielectrics (detailed discussion of low-k polymers is provided in Section 4.1.2), with which a thin film (e.g., a few tens of nanometers thick) is normally needed for high capacitance.96-99 Figure 9 (a) depicts the mechanism of the iCVD polymerization process: (i) the introduction of vaporized monomers and initiators, (ii) the thermal dissociation of initiators into radicals by contact with filaments (red lines) heated at ∼200°C, (iii) the adsorption of the monomers and initiator radicals onto the surface of a cooled substrate (40°C), and (iv) free-radical polymerization to form poly(1,3,5-trimethyl-1,3,5trivinyl cyclotrisiloxane) (pV3D3) thin films. This process is widely applicable to various classes of free radical polymerizations.100-103 The Im group also took advantage of the iCVD process to prepare a pV3D3 ultrathin dielectric layer for flexible electronics.99 The iCVD process allowed the layer to be thinned to 6-7 nm and a conformable pinhole-free film to be produced, which was essential for lowpower functioning because of the low dielectric constant of pV3D3 (k ≈2.2). The capacitance reached up to 250-300 nF/cm2 by applying the ultrathin film.

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Figure 9. (a) Schematic of the mechanism of iCVD process. (b) |ID| versus VG (solid lines) and |IG| versus VG (dotted lines) characteristics of a bottom-gated C60 FET with a pV3D3 gate dielectric, and the schematic of the device structure. (c) Photographs of Al/pV3D3/Al MIM devices fabricated on PET substrates under tensile (left) and compressive (right) bending tests. (d) Ji measured at 3 MV cm−1 for various values of bending radius (R) and corresponding strain (S) calculated using the relation of S=dsub/2R, in which dsub is the thickness of the substrate. (Adapted with permission from ref. 99. Copyright 2015 Nature Publishing Group.) A room-temperature plasma-enhanced chemical vapor deposition (PECVD) technique was developed by Silva et al.104 to realize the low-temperature growth of a polymer-like carbon dielectric layer. The carbon film was deposited from the hydrocarbon acetylene (C2H2) in a high-pressure, radiofrequency (RF) plasma. The formation of methyl radicals in this technique followed a distinctive lowenergy mechanism C2H2 + CH3*→−[HC*−CH(Me)]−. Carbon radicals were generated at low temperatures, and the polymerization reaction was induced at the same time, which enabled the deposition of an even, non-defective film.105 The high-quality film rendered the excellent performance of the device with a mobility of 1.2 cm2 V−1 s−1 in a 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) OFET, and the leakage current was as low as 10-12 A.

23



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Apart from the film-processing methods mentioned above, the direct grafting of ultrathin polymer films on the substrate using in situ polymerization also appears to be a way of fabricating high-quality polymer nanodielectrics.106-109 A surface-initiated atom-transfer radical polymerization (SI-ATRP) was adopted by Hu et al. to grow a PMMA brush on the surface of a silicon wafer. The densely packed polymer brushes allowed for the formation of a pinhole-free film with a thickness of 10 nm. Operational voltages ≤ 2.0 V were achieved using CuPc single-crystalline nanoribbons as the semiconductor. Meanwhile, the grafted PMMA dielectrics showed a leakage current of approximately 4 × 10-8 A cm-2, which was significantly lower than that of a spin-coated PMMA dielectric with the same thickness.110

4. Representative Polymer Dielectrics 4.1 Synthetic Polymer Dielectrics Various polymers have been investigated for their use as gate dielectrics (chemical structures of representative polymer dielectrics were listed in Figure 4), and they are commonly classified as high-k and low-k polymers. Low-k polymers, commonly known to have a dielectric constant below that of silicon oxide (k~3.9), include crosslinking systems of PMMA, PS and polyimide (PI) and so on. The commercially available high-k polymers such as PVA, poly(vinyl phenyl) (PVP) and cyanoethylpallulan (CYPEL), normally have dielectric constants ranging from 4.6-18.5.10 This review paper mainly adopts the dielectric constant-based classification. Another way for classification or choice of dielectrics is their adaptability with different types of semiconductors (e.g. some dielectrics are better suited for p-type devices while some are better for the n-type). This has been well-studied for the inorganic devices, considering their bandgap-match with the semiconductors. The offsets of the dielectric valence band maximum should >1 eV compared to those in the metal oxide semiconductor, and the same is true for the conduction band minimum in an n-type transistor.11, 111 For polymer dielectrics, fewer studies have been carried out regarding the band

24


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structure. However, there are researches providing important insights. The hole/electron transport capability of organic semiconductors can be tuned by different kinds of interface dipoles.112 Noh et al.9 investigated poly{[N,N9-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]alt-5,59-(2,29-bithiophene) (P(NDI2OD-T2))}, an ambipolar semiconductor with n-channel characteristics and very low hole transport ability. It was found that by using fluorinated dielectrics, (e.g., P(VDF-TrFE)), the hole mobility reached ~0.11 cm2 V-1s-1, which was 100 times more than those using non-fluorinated polymer dielectrics (PMMA, PS, etc.), and electron mobility slightly decreased.113 The dielectric dipole-semiconductor molecule orbital (MO) interactions can modulate the MO energy. Using dielectrics with C−F dipoles, the HOMO and LUMO energy levels of the semiconductor can be pulled up, and thus the accumulation of positive charge carriers at the interface is enhanced. Polymers with C-H dipoles have the opposite effect, and are more beneficial for n-channel semiconductors. 4.1.1 High-k polymers As was stated above, higher k values are often preferred to achieve a larger capacitance. However, as discussed above, the effect of using high-k dielectrics on field-effect mobility is still under debate. On one side, some devices with high-k dielectrics show a field-enhanced current leading to a high field-effect mobility.114 While on the other hand, high-k dielectrics generally have a high polarity at the interface, which traps the charge carriers and reduces the mobility. Thus, a higher dielectric constant does not necessarily result in a better performance. The interfacial effect should also be carefully considered. Table 1 summarizes the dielectric and OFET properties for some recently developed high-k polymer gate dielectrics. PVA and PVP are both commonly used high-k dielectric material in OFET fabrication. However, they have the drawback of containing moisture sensitive hydroxyl groups that inhibit moisture endurance and performance stability. Thus, crosslinking is applied to tackle the problem and enhance the overall insulating properties. Pristine PVA has dielectric constant of ~7. One effective way of PVA 25



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crosslinking is the photo-crosslinking by ammonium dichromate (AD).115 The dielectric constant of PVA decreased slightly to ~6 after crosslinking. It was found that the ratio of 25% AD: 75% PVA was optimal for device performance with highest mobility of 0.12 cm2 V-1 s-1 and lowest leakage of 1.2×10-9 A at -5 V using poly(3-hexylthiphene) (P3HT) semiconductor.116

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Table 1. Dielectric and OFET properties for selected recently developed high-k polymer gate dielectrics Dielectric

k

D (nm)

Ci (nF cm-2)

Structure

OS

µ (cm2 V-1 s-1)

ION /IOFF

ref

Crosslinked PVP (HDA)

4.1

22

166

TC

pentacene

0.7

9.5 × 104

117

Crosslinked PVP (EAD)

4.4

20-25

159

TC

pentacene

1.23

4.0 × 105

117

Crosslinked PVP (BCD)

4.5

20-25

156

TC

pentacene

0.9

1.2 × 105

117

PVPAlkylene−4T

3.1

50

58

BG-TC

pentacene

0.135 (±0.013)

8.15 × 104

118

Crosslinked PVA

6.2

250

22

BC

P3HT

0.126

TC

pentacene

0.23 (±0.06)

7.0 × 104

119

p-6P/VOPc

0.8

105

120

CPVP_IPWL 4-HMB-4-C

7.2

CEP-SCL

12.3

pentacene

8.62

105

121

CEP-EDT

13.6

pentacene

0.65

5 × 104

121

P(VDF-TrFE-CFE)

∼60

pBTTT-C16

0.43

127

P(NDI2OD-T2)

0.2−0.5

126

rubrene single crystals

12

128

P(VDF-TrFE)/PMMA Crosslinked

8.4

350

18.0

116

250-260

20

7.2× 103

1.0

BG-TC

P(VDF-BTFE) 27


Chemistry of Materials 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Bilayered PAN

3.7

Page 28 of 79

DH4T

1.37 × 10-2

103

141

PHPMA/PEI

120

1400

TC

P3HT

0.16

38PVN/P(VDF-TrFE)

70/350

∼ 15.8

TG

PC12TV12T

0.061

107

148

5.3–6.1

400

12.45–13.25

C60

0.13

104

198

6.1

420

30

pentacene

23.2

3 × 104

194

104

104

P3HT

1.7 ± 0.3

105

163

500

103

P(NDI2OD-T2)

0.008

2 × 103

164

P3HT

1.4

105

162

TG-BC

DPPT-TT

1.0

BG-TC

Pentacene

0.66

Crosslinked

40

albumen Silk fibroin P(VDF-HFP)/ [EMI][TFSA] PS-PIL-PS/ TFSI

TG

SOS/N3 [EMI][TFSI] P(VDF-TrFE)-g-PMMA

~7-9

230

poly(MSEMA-co-GMA)

~9-12

200-400

~19-32

BG= bottom gate device, TG= top gate device, TC= top contact device, OS= organic semiconductor

28


131

105

123

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One conventional way to construct cross-linked PVP systems is through esterification reaction, which requires a high temperature and cannot fully remove the hydroxyl groups that may act as electron traps leading to large hysteresis and a high leakage current. Also, high-temperature processing may not be compatible with many plastic substrates. To solve this problem, novel crosslinking systems have to be developed to reduce the curing temperature and achieve more complete removal of the hydroxyl groups. For example, Mark et al. investigated the role of crosslinking agents (bifunctional anhydrides, acylchlorides, and carboxylic acids, summarized in Figure (4)) in the crosslinking of PVP.117 In their study, the lowest crosslinking temperature of 60°C was achieved by suberoylchloride (SC) or ethylenediaminetetraacetic dianhydride (EAD) crosslinking agents, while the dianhydrides required a curing temperature of 120°C. The 4,4’-(hexafluoroisopropylidene)diphthalic anhydride) (HAD)-crosslinked PVP resulted in the best OFET performance, showing a carrier mobility as high as 3 cm2 V−1 s−1 for pentacene. Then, Wang et al.118 reported a low-temperature processed, hydroxyl-free PVP dielectric layer by thio-ene reaction that successfully decreased the curing temperature to 60°C. The study also overcame the limitation of the high density of hydroxyl groups in typical PVP-based cross-linking systems by employing new cross-linkable side chains. This PVP-4T gate dielectric demonstrated an electron mobility of (1.0×10−2 cm2V−1s−1) in copper hexadecafluorophthalocyanine (F16CuPc) devices, which was one order of magnitude higher than the reported value using PVP-HDA dielectrics. A better air and water stability were also demonstrated. Furthermore, an instantaneous pulsed-light cross-linking was reported for PVP-based gate dielectric using cross-linking agent poly(melamine-co-formaldehyde) (PMF) under intensely pulsed white light (IPWL) irradiation.119 The IPWL method is more energyefficient compared to the thermal crosslinking and continuous light radiation, and high temperature 29



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only occurred in the near-surface region of the polymer. Besides the PVP system, polymers with cyano groups are extensively investigated as high-k dielectrics due to the high polarity of cyano groups. By introducing polar groups in various polymer backbone structures, novel high-k dielectric materials can be developed. Berndt et al.40 developed a new methacrylate copolymers using free radical and RAFT polymerization. Polar terminal cyano groups were introduced in the liquid crystalline methacrylate comonomer to increase the dielectric constant. The liquid crystalline self-organizing side chains were, for the first time, incorporated into the copolymer dielectric layers to form a well-ordered interface morphology. Together with the ordered packing of the side chains and improved solvent resistance, the dielectric breakdown strength increased to 4.0 MV cm-1 compared with 0.3 MV cm-1 for a non-crosslinked PMMA dielectric. Two novel high k cross-linkable polymers were synthesized by Cui et al. that contain a biphenyl structure with cyano groups.120 Their dielectric constants can be tailored to 6.8 and 7.2 with different ratios of cyano groups. Dielectric layers fabricated from the two polymer films exhibited excellent insulating properties with a leakage of 10−7 A cm−2 and an on/off current ratio >104 because of the low free volume and smooth surface morphology. The charge carrier mobility reached 0.8 and 0.5 cm2 V−1 s−1, respectively. Many reports stated that a high-k dielectric is incompatible with a high theoretical mobility because of the surface dipole disorder. Accordingly, approaches were taken to deal with the problem of dipole disorder. Rhee et al.121-122 investigated the quasi-ordering of surface dipoles of cyano groups in the high-k polymer, cyanoethyl pullulan (CEP), which originated from the hydrogen bonding of C≡N…H−C−C≡N, as conformed by XPS and molecular simulations. The dielectric layers were baked in a vacuum oven at different temperatures of 50°C, 100°C and 150°C. At a low baking temperature, 30


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the ordered dipole can direct the deposition of the overlying pentacene semiconductor, leading to the formation of vertically aligned pentacene clusters. However, this effect was disrupted at high temperatures because of the breaking of hydrogen bonding. The best OFET performance was observed at the lowest baking temperature (50°C), with a mobility of 4.9 cm2 V−1 s−1 compared with 0.81 and 0.51 cm2 V−1 s−1 at 100°C and 150°C, respectively. The corresponding subthreshold slope (S) values were also enlarged from 0.062 V dec-1 to 0.360 V dec-1 and 0.503 V dec-1. Furthermore, other crosslinking agents of CEP were investigated.122 It was found that in the case of the suberol chloride crosslinking agent, the ester groups formed after curing were able to knit up the gaps between the selfassociated dipoles, and the 2D layer-by layer growth of pentacene layer was observed. The mobility was further increased to ~8.6 cm2 V−1 s−1 with an on/off current ratio of 105.121 Sulfone-group based dipolar glass polymers are another category of high-k gate dielectrics. Sulfone groups have large dipole moments of ~ 4.3 D and strong dipole interactions, which contribute to the high dielectric constants and high Tg of sulfone-containing polymers. Huang et al.123 reported a series of poly(2-(methylsulfonyl)ethyl methacrylate-co-glycidylmethacrylate) (poly(MSEMA-coGMA)) copolymers containing sulfone side chains and epoxy groups for crosslinking. Due to the dilute dipole densities, the copolymer showed slight hysteresis, with dielectric constants ~10. P-type organic semiconductors (OSC) including DNTT and pentacene were tested in OFETs, and low operation voltage of 4 V was achieved with mobility of 0.22 cm2V-1s-1. Meanwhile, Zhu et al.124 designed a sulfonylated poly(2,6-dimethyl-1,4-phenylene oxide)(SO2 -PPO) high temperature dipolar polymer by post-polymer functionalization. The highest k value reached 8.2 for SO2 -PPO52 at room temperature. High-k ferroelectric polymers (e.g. poly(vinylidenefluoride) (PVDF)-based polymers) have promising high dielectric constants. However, as discussed in Section 2.4, the main challenge of 31



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applying them as gate dielectrics lies in their large hysteresis brought by the ferroelectric effect. As a result, a novel type of ferroelectric polymers, the relaxer ferroelectric polymers was reported to be an option. The relaxer ferroelectric polymers, compared with ferroelectric polymers, showed a lower ferroelectric dipole density because of having separated ferroelectric domains dispersed in a matrix of paraelectric phase. Thus, an ultrahigh dielectric constant and low hysteresis can be achieved due to the interfacial polarization between the nanodomains and the matrix. They can have substantially higher dielectric constants (k values up to 40-70 can be achieved by modulating copolymer ratios) than common high-k dielectrics (usually below 20).125 The most common types of relaxer ferroelectric polymer are the poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE))-based terpolymers and PVDF-based polymer blends.25, 126 Yan’s group127 first applied a poly(vinylidenefluoride-trifluoroethylene-chlorofluoroethylene) (P(VDF-TrFE-CFE)) terpolymer with a copolymer ratio of 56/36.5/7.5 mol% as the dielectric layer with a k value higher than 60 at low frequencies. The poly(2,5-bis(3-dodecylthiophene-2yl)thieno[3,2-b]thiophenes)-C16 (pBTTT-C16) OFET device fabricated using the P(VDF-TrFE-CFE) dielectric showed a mobility of 0.4 ± 0.2 cm2 V-1 s-1, higher than that of the devices using PMMA and PS as dielectrics with mobilities of 0.15 ± 0.05 cm2 V-1 s-1 and 0.09 ± 0.03 cm2 V-1 s-1, respectively. Gomez

et

al.128

also

used

a

high-k

fluoropolymer,

poly(vinylidenefluoride-

bromotrifluoroetheylene) (P(VDF-BTFE)), for the purpose of chain conformation control. The study of chain conformation showed that the crosslinked P(VDF-BTFE) copolymer had the highest percentage of TTTG conformation (T: trans, G: gauche) and that the chain twisting was largely reduced due to the incorporation of the BTFE moiety. As a result it showed superior properties compared to the counterpart (P(VDF-TrFE)). The trend of mobility change in different PVDF-based 32


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copolymers corresponded to the change in TTTG conformation (also known as the γ phase) content. An ultrahigh charge mobility exceeding 10 cm2 V-1 s-1 was achieved single-crystal rubrene FETs. The Noh group examined the effect of a fluorinated surface with different PMMA blending ratios using a broader range of p-type and n-type semiconductors, including eight types of polymers, carbon nanotubes and metal oxides.112, 129 It turned out that for some semiconductors with low polarizabilities and large bandwidths, such as carbon nanotubes (CNTs) and indium gallium zinc oxide (IGZO), the electron mobility increased strongly along with the increase of hole mobility. However, for polymer dielectrics, the interfacial polar groups took a more dominant role, and the simultaneous increase of hole and electron mobilities required low surface dipole densities.130 Based on the above concept, the Noh group studied the surface-directed phase separation in the P(VDF-TrFE)/PMMA blends. Commonly, the components in the blend with a low surface energy tend to migrate to the surface during spin-coating. They spin-coated a P(VDF-TrFE)/PMMA blend and found that the F intensity decreased sharply from the surface to the dielectric-semiconductor interface by using secondary-ion mass spectrometry (SIMS). Thus, the interface with a lower dipole density was achieved. The best ambipolar performance was realized under the blending ratio of 9:1. The OFET showed a µe of 0.21 cm2 V-1 s-1and a µh of 2.15 cm2 V-1 s-1 with a DPPT-TT semiconductor. Furthermore, the Noh group directly grafted PMMA chains on P(VDF-TrFE) backbones via atom transfer radical polymerization (ATRP) and applied the polymer dielectric in DPPT-TT OFETs.131 It showed the grafting of a small amount of amorphous insulator can effectively improve the hysteresis compared to using bare P(VDF-TrFE) dielectric while maintaining low operation voltage. The ∆Vth of OFETs using 9 mol% grafted polymer was −0.35 V after 100 times bias sweep circles, while that of bare P(VDF-TrFE) dielectrics was −12.2 V. 33



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Self-healing materials are being extensively investigated because of the capability to partially or completely heal damage inflicted on them. In recent years there has been intense interest in incorporating self-healing materials in flexible, stretchable and conformable electronics.132 Selfhealing dielectrics using a self-aligned metal oxide have been previously demonstrated.133-134 To take this concept a step further, Katz’s group 135 reported a self-healable polymer dielectric blend with an ultrahigh capacitance of 1400 nF cm−2 at 20–100 Hz (120 nm thick) that can heal both under mechanical and electrical breakdown. The healing ability lies in the reversible bonding of hydrogen bonds within the poly(2-hydroxypropyl methacrylate)/poly(ethyleneimine) (PHPMA/PEI) blends (Figure 10).

Figure 10. (a) Healing test of transistor behavior (I–V characteristics). (b) An illustration of the selfhealing process of the PHPMA/PEI system due to robust hydrogen bonds between the severed surfaces. (c) A schematic of the self-healing OFET devices. The damage in gate electrode layer (carbon paint) can be partially healed together with the self-healing process of gate dielectric layer. (Adapted with permission from ref. 135. Copyright 2015 John Wiley & Sons Inc.).

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Bilayered Polymer Gate Dielectrics: Despite the merits of newly explored high-k polymeric materials, the dipole disorder caused by the polar surface still remains a challenge. To address this issue, bilayered gate dielectrics employing a low-k polymer buffer layer were developed to avoid direct contact between the semiconductor and polar moieties.136-138 Bilayered structures are especially useful to eliminate the mobility degradation due to dipole contact with the semiconductor.

Figure 11. (a) Cross-section schematic of bilayered OTFT with a dielectric polymer as buffer layer. (b) Electron mobility as a function of the dielectric constant of the polymer dielectric buffer layer. The dashed line is a fitting equation: μ=A exp(-Bk), where k is the dielectric constant and A and B are preexponential factors that define how highly the mobility depends on k (c) Multicycle stability and airdurability of n-channel OTFTs: Overlays of transfer curves of poly(benzobisimidazobenzophenanthroline) (BBL) OTFTs without and (d) with a 43.0 nm PS buffer layer. (Adapted with permission from ref. 139. Copyright 2011 American Institute of Physics). Various buffer layers with a hydrophobic surface character and low dielectric constants were studied. Jenekhe’s group139 investigated a series of low-k buffer layers inserted between the n-type poly(benzobisimidazobenzophenanthroline) (BBL) semiconductor and SiO2 gate dielectric. The mobility decreased with an increased dielectric constant of the buffer layer, as shown in Figure 11 (b). 35



Page 36 of 79

The use of a PS buffer layer, with the lowest dielectric constant of 2.5, led to the highest mobility of 0.03 cm2 V−1. The insertion of the buffer layer also stabilized the voltage shift and hysteresis. As shown in Figure 11 (c) and (d), a significant reduction in hysteresis after the multicycle test was observed, among which the largest of 4 V was observed using a poly(vinylcarbazole) (PVK) layer and the smallest of 0 V with a PS buffer layer. Besides, Wang’s group also investigated different types of low-k buffer layers. They carried out experiments using PS, PVN and PMMA as top layers on a high-k PVA bottom layer. 140 All devices with a top layer showed decreased IDS hysteresis and leakage current and increased bias stability in a short-time period. However, among the top layers used, the π-groupfree polymer (i.e., PMMA) manifested the most improved bias-stress stability, with a Vth shift of < 4% after a 3 h of stress time. The inferiority of the π-group was attributed to its slow charge trapping under bias stress. Ko et al.141 inserted a low-k PS-P123 block copolymer blend buffer layer between the polyacrylonitrile (PAN) gate dielectric and the semiconductor. The k value for the bilayer dielectric was 3.7, between that of the PAN and the PS-P123 blend. The buffer layer changed the surface energy and reduced the hydrophilicity caused by polar −CN groups. The device showed a stabile performance in atmosphere. Guo et al.142 also applied a CYTOP buffer layer to the high-k (P(VDF-TrFE-CFE)) dielectric to minimize the broadening of the DOS and to increase mobility. The dielectric without a bilayer showed a mobility of 0.3 cm2 V-1 s-1, while it was raised to 1.4 cm2 V-1 s-1 after the addition of the buffer layer. High-k Polymer Dielectrics for Memory Devices: The application of OFETs in non-volatile memory devices calls for some unique properties of gate dielectrics.143 The most important one is the desirable or purposefully introduced hysteresis for the memory characteristics. The gate dielectrics used for memory devices can mainly be divided into three types. The first 36


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one is the floating-gate memory device, which incorporates metallic nanoparticles that can act as a floating gate to store and release charge in the dielectric layer matrix.144-145 Charges injected into the floating gate can be stored as a memory because of the separation of the nanoparticles from the channel. Recently, different from the traditionally used nanoparticles or nanocrystals as floating gate, Chen’s group developed a distinctive organic nano-floating gate structure. By using a star-shape core-shell structure composed of a copper phthalocyanine (CuPc) core and four polystyrene arms, the controlled distribution of charge trapping sites are realized due to the CuPc-PS4 structure (Figure 12). The device showed a flash-type memory with a high memory current ratio > 107.146

Figure 12. (a) Schematic of OFET memory device with a nano-floating gate and (b) the chemical structure of the CuPc-cored star-shaped polystyrene. (c) Endurance characteristics of the CuPc-PS4embedded memory device under different programming/erasing cycles. (d) Retention characteristics of the CuPc-PS4-based memory device. (Adapted with permission from ref. 146. Copyright 2016 John Wiley & Sons, Inc.). The second type consists of charge-trapping polymer electrets, which are operated by the reversible charge trapping and releasing in the polymer electret dielectric. In this sense, hysteresis 37



Page 38 of 79

behavior or ferroelectricity is not desired for the gate dielectric. The memory performance, revealed by the shift of Vth, is gained through the chargeable dielectric layer. On applying an electric field, the carriers are injected into the dielectric and trapped. The memory ability is determined by the surface charge trapping ability and by the HOMO-LOMO level match between the semiconductor and the dielectric for effective charge injection.147 Noh et al.148 first fabricated the printed organic NAND flash device using a full polymer chargetrapping dielectric memory layer. The dielectric layer they used was composed of a poly(2-vinyl naphthalene) (PVN) or PS chargeable electret and a P(VDF-TrFE) buffer layer. In their contribution, the P(VDF-TrFE) was intentionally annealed to eliminate the ferroelectric β phase, and only served as a high-k buffer layer without the ferroelectric memory behavior. The PVN, with a smaller band gap because of the conjugated structure, showed good memory performance (the memory window >90 V) compared with the PS counterpart, which had a memory window of only ∼34 V under a bias voltage of more than ±90 V. Figure 13 (c) illustrates the charge-trapping mechanism and performance of the memory devices. By applying a positive voltage, electrons were transferred to the electret and then trapped and stored there. They served to accumulate holes at the PVN/semiconductor interface. Then, under the application of a reversed bias voltage, the electrons were detrapped, and the holes then transferred to the PVDF/PVN interface.

38


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Figure 13. (a) Structure of Top gate-buttom contact OFET-based memory device. (b) Schematic of the charge transfer and trapping mechanisms. (c) Reversible bias hysteresis during sequential dualgate voltage sweeps from ± 50 V. (d) A schematic illustration of the memory operation mechanism under each bias condition. (Adapted with permission from ref. 148. Copyright 2012 John Wiley & Sons, Inc.). Polymers with hydroxyl groups are also promising candidates because of their dipole orientation behavior.149 Chen’s group150 successfully applied glucose-based oligo- or polysaccharides in the nonvolatile memory device. The retention time could be more than 108 s. Tung et al.151 synthesized a crosslinkable

high-k

copolymer

poly(n-(hydroxymethyl)

acrylamide-co-5-(9-(5-(dieth-

ylamino)pentyl)- 22-(4-vinylphenyl)29H-fluorene) (P(NMA-co-F6NSt)), combing a fluorene charge trapping block with an NMA crosslinking moiety. Efficient charge trapping was achieved at a low voltage of ±5 V because of the high dielectric constant, leading to a large memory window of up to 4.13 V. The self-crosslinking ability also granted the polymer with a tight network structure and realized the separation of trapping sites. 39



Page 40 of 79

The third one is non-volatile ferroelectric memory devices.152-153 The remnant polarization in a ferroelectric polymer results in the hysteretic change of drain current with changing gate voltage and thus lead to the non-destructive readout process. The ferroelectric behavior can be demonstrated by the IDS-VG curve. Park et al.70 reported a Fe-FET using a typical ferroelectric polymer P(VDF-TrFE). A multi-level memory cell (MLC) device was adopted in the study. The precise control of remnant polymerization was achieved with a retention time of more than 105 s. Furthermore, P(VDF-TrFECTFE) and P(VDF-TrFE)/P(VDF-TrFE-CTFE) polymer blends applied as memory dielectrics in the MLCs were also investigated.154 Electrolyte-gated Transistors (EGTs): Another emerging group of high-k dielectric is polymer electrolytes. Electrolyte-gated transistors (EGTs), which employ electrolytes with high capacitance as the dielectric layer are promising candidates for flexible displays and bioelectronic sensors.155 The large capacitances of the electrolyte-based dielectrics result from the formation of electrical double layers (EDLs) at the semiconductor-electrolyte interface. As a result, the use of ionic liquid as gate dielectrics has the advantage of high dielectric constants, high carrier mobility, low contact resistance and inherent printability.156 In EGTs, ions are incorporated purposefully by using the ionically conductive and electronically insulating electrolytes. If the semiconductor is impermeable to the ions used, the ions will migrate and accumulate at the gate/dielectric and dielectric/semiconductor interface, and EDLs will form at the two interfaces.157 In this impermeable mode, the EGTs can be viewed to operate in the similar mechanism as normal FETs. And due to the polarizability of the ions, a capacitance value an order of magnitude larger than the conventional dielectrics can be attained in most cases.158 On the other hand, if the semiconductor is permeable to the ions, the ions will diffuse into the semiconductor under applied voltage, and the process of electrochemical doping happens.157 40


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In this case, the transistors operate in the reversible doping and de-doping process upon the application and removal of electric fields. This allows for larger driving currents in the transistors due to the threedimensional channel brought by penetrating ions. To provide both good ion transport and mechanical properties, Lodge et al.159 fabricated polymer ion-gels using polymer networks swollen with different kinds of ionic liquids. The gelation can be achieved by both chemical160 and physical161 crosslinking processes. They used the self-assembly of a poly(styrene-b-ethyl acrylate-b-styrene) (SEAS) triblock copolymer in the ionic liquid 1-ethyl-3methylimidazolium bis(trifluoromethylsulfonyl)amide ([EMI][TFSI]) to form the physically crosslinked ion-gels, of which the conductivity and modulus could be simultaneously increased by tuning the midblock size.162 In the case of chemical crosslinking, the functionalization of crosslinking side chains on polymer backbones can lead to multiple crosslinking networks. In addition, a mechanically robust ionic gel dielectric material that could be cut and stuck was developed.163 The ionic liquid [EMI][TFSA] was blended with the structuring polymer, P(VDF-HFP). Free-standing and flexible films were obtained, as demonstrated in Figure 14 (e), and could be easily twisted due to their mechanical strength. The solvent-free films were laminated directly onto the device, thus, eliminating the possible contamination of channels during solution processing (Figure 14 (b)). The films had large capacitances of 10 µF cm–2 even with a thickness of 10 µm, which was greater than those of common high-k polymers. With the high hole density induced by the ion gel, mobility of 2.3 ± 0.2 cm2 V−1 s-1 was generated using P3HT semiconductor.

41



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Figure 14. (a) Cross-sectional schematic of an ion gel-gated organic thin-film transistor (Gel-OTFT) (b) Optical image of the cut-and-stick Gel-OTFT. (c) Quasi-static IDS-VDS characteristics and (d) Quasi-static IDS-VG characteristics of a Gel-OTFT. The gate voltage was swept at a rate of 25 mV s−1. (e) Optical images of the free-standing ion gel based on P(VDF-HFP) and [EMI][TFSA]. (Adapted with permission from ref. 163. Copyright 2012 John Wiley & Sons, Inc.) More recently, polyelectrolytes or poly(ionic liquid)s (PILs) were synthesized using ionic liquid monomers. For example, PS-PIL-PS triblock copolymers were recently developed for gate dielectrics.164-165 The copolymers were composed of PS blocks, and polymerized 1-[(2acryloyloxy)ethyl]-3-butylimidazolium bis(trifluoromethylsulfonyl)imide blocks which are the PILs. Because the cations are covalently anchored to the main chain but the counterions are mobile, the copolymers were unipolar polyelectrolyte and could find application with n-type semiconductors. The polarization schematics for unipolar polyelectrolytes and bipolar polyelectrolytes and their characteristics are presented in Figure 15. As illustrated in Figure 15 (b), a 2D electric double layer was formed at the electrolyte/semiconductor interface in the unipolar system. However, for the bipolar polyelectrolyte, some mobile cations could penetrate into the semiconductor, whereas others left with 42


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the immobilized polycations and accumulated at the interface. As a result, a 3D channel was created. Nonetheless, the solid electrolyte gates show larger leakage current and dissipation factor compared with traditional insulating dielectrics, which need further optimization in future developments.

Figure 15. (a) Schematic of the Au/PS-PIL-PS/Au capacitor used to measure impedance properties. The cations were covalently tethered to the polymer backbone, while the anions (TFSI) were mobile. (b) Cross-section schematic illustrating the polarization in unipolar (neat PS-PIL-PS) and bipolar (ILdoped PS-PIL-PS) EGTs using an n-type semiconductor. (c) The IDS-VG characteristics and (d) IG-VG characteristics of an n-type transistor P(NDI2OD-T2) with neat PS-PIL-PS and IL ([EMI][TFSI])doped PS-PIL-PS dielectric. (Adapted with permission from ref. 164. Copyright 2015 American Chemical Society.) 4.1.2 Low-k Polymers High-k dielectrics are desirable in achieving higher capacitance to reduce operating voltages. 43



Page 44 of 79

However, as stated above, the existence of polar dipoles and their relatively slow polarization results in unstable device performances and hysteresis that cannot be eliminated. A polar surface can also be occasionally unsuitable for the growth of the semiconductor layer. Thus, low-k dielectrics still possess irreplaceable merits, and new advances are in demand. Devices that are fabricated using various low-k polymer gate dielectrics or dielectric buffer layers have been reported 139 The prospect of novel low-k dielectrics lies in the following aspects. First, new techniques on dielectric layer fabrication are adopted, such as vapor phase deposition and photolithography, to meet the need of ultrathin and well-functionalized films. Second, insights into the influence of surface behavior on the grain formation of the semiconductor layer are highlighted. Third, novel polymers are reported that could suit low-temperature solution processing, while various crosslinking methods are adopted to enhance the insulation property in thin films. Table 2 summarizes the dielectric and OFET properties for selected recently developed low-k polymeric gate dielectrics.

44


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Table 2. Dielectric and OFET properties for selected recently-developed low-k polymeric gate dielectrics and bio-polymer dielectrics Dielectric

k

pEGDMA

D (nm)

Ci (nF cm-2)

Method

OS

µ (cm2 V-1 s-1)

3.02

iCVD

Pentacene

0.142

103

pIBA

2.61

iCVD

Pentacene

0.159

103

pPFDA

2.74

iCVD

Pentacene

0.044

103

TIPS-pentacene/PS

0.19

86

Patterned FOTS-PVA

ION /IOFF

ref

CYTOP

Dry etching

C16IDT-BT

0.88

1.1 × 108

88

PLC

PECVD

TIPS-pentacene

1.2

106

104

6FDA−

∼30

78.11

Spin coating

pentacene

0.15

1.27 ×104

49

6FDA−CF3Bz−PDA PI

∼30

76.77

Spin coating

Pentacene

0.23

7.23 × 103

49

PAA-PI copolymer

~160

20 (at 20 Hz)

Spin coating

Pentacene

5.6

1.4× 106

174

PDA−PDA PI

PMS

2.62

Spin coating

Pentacene

1.07

67

PFS

2.64

Spin coating

Pentacene

0.33

67

pV3D3

2.2

iCVD

C60

1.69

53

45


>105

99

Chemistry of Materials 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

A-10-YMA/

Page 46 of 79

∼6

∼40

∼18

Spin coating

Pentacene

∼0.5

105

175

co-PMMA2

3.7

410

8.0

Spin coating

TIPS- pentacene/PS

0.59

∼105

180

co-PS2

2.8

400

6.2

Spin coating

TIPS pentacene/PS

0.14

∼103

180

19.3

Spin coating

TIPS-pentacene/PS

0.22

>105

188

CuPc

0.12

3.3 × 103

110

HB-ant-THT

0.31

104

193

TIPS-pentacene/PS

0.4

105

183

VOPc

0.13

104

234

copolymer

Photo-crosslinked PMMA PMMA brush (SI-ATRP)

1.8

220

Photo-crosslinked DNA SU8

3.9

1.16 × 103

2.97

Photo-crosslinked PU

3.2

690

4.1

Spin coating

OS= organic semiconductor

46


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Polyimide (PI) materials have been widely investigated in the electronic industry as packaging materials. They are also found promising as low-k dielectrics due to their excellent thermal stability and electrical insulating properties.166 In developing new types of low-k dielectrics, creating preferable surface for semiconductor growth is one focus. A popular way for surface modification of polyimides is the incorporation of fluorinated substituents. Fluorinated PIs are usually designed for low dielectric constant applications due to the small polarizability of −C−F and large free volume of CF3 groups.167 Park et al.49 introduced different numbers of fluorine atoms into the PI backbone and found an increase in carrier mobility and a positive shift of the threshold voltage (from −0.38 to +2.2 V) with increasing the number of fluorine atoms (from 6 to 18 atoms per repeat unit) in both pentacene and TES-ADT OFETs. The presence of fluorine atoms can create an inert surface and impede trap formation, through which an improved stability under bias stress can be achieved.168-169 Besides reports on various PI materials with different functional groups,170-172 poly (amic acid) (PAA), the precursor of PI, was found to allow more ordered packing of pentacene on the surface.173 The hydrogen bonding leads to a self-rippled surface of PAA, and the –COOH and –CONH– polar groups can aid the vertical orientation of pentacene. In this situation, the strong polar surface of the dielectric can optimize the compatibility between semiconductor and gate dielectric, enhance crystallinity and decrease interfacial traps. However, without full imidization, PAA shows relatively lower insulation property and chemical stability. To tackle with the problem, Hu et al. created a random copolymer with controlled amount of imidization of PAA by low-temperature treatment.174 The new polymer shared the merits of both PAA chain structure and the phenyl rings and alicyclic rings of PI for high stability and ideal insulating property. The pentacene OTFTs showed mobility up to 5.6 cm2 V-1s-1 under operating voltage of 3 V. 47



Page 48 of 79

Different types of low-k polymer dielectrics were developed to further study the surface effect on the growth of pentacene grains. Despite the former findings that heterogeneity in the dielectric surface had an adverse effect on the OFET performance, Liu et al.61 intentionally created a surface with heterogeneous states by employing blended dielectrics of polyphenylene oxide (PPO) and PS and proposed a “heterogeneity-employed” mechanism for an increased mobility. Two kinds of interfacial lacunas of pentacene grains appeared on the PPO/SiO2 dielectric surface that resulted in a relatively low mobility. Additionally, the incorporation of polymer blends/SiO2 dielectric was found to enhance the inter-grain connection of the semiconductor and reduce the inner-grain defects simultaneously and increased the mobility up to∼ 3.6 cm2 V-1 s-1. Cui et al.175 also tried to optimize the compatibility between semiconductor and dielectric. They synthesized a dielectric copolymer containing a novel monomer, anthracen-10-ylmethyl methacrylate anthracene. The anthracene unit, which had a similar structure to that of pentacene, could provide a crystal nucleus for the pentacene semiconductor, and thus enabled the study on the variation of mobility with semiconductor grain size. Despite the common recognition that a larger grain size results in increased mobility, they found that the inter-grain connection provided by the presence of small grains among large grains could lead to the highest mobility of 0.7 cm2 V−1 s−1. Novel Crosslinking Routes: With regard to novel low-k dielectric materials, new crosslinking routes including thermal crosslinking and photo crosslinking are being adopted to enhance the electrical robustness of the dielectric layers, as well as improve their solvent resistance to enable the solution processing for different device structures.118, 176-179 In consideration of crosslinked dielectrics, it is highly desirable to develop low-temperature, energy-efficient and additive-free crosslinking strategies. A thermal azide–alkyne cyclo-addition (TAAC) reaction was adopted by Zhang et al.180 for the 48


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styrenic polymer blends as a low temperature cross-linking route at 100°C. The TAAC reaction served as a click crosslinking strategy that produces no byproducts.181 They then further developed a bifunctional copolymer system with PMMA and PS bearing both propargyl and azido groups on the same polymer chain.182 During crosslinking, the two moieties were attached to the same polymer chain so as to prevent phase separation. The bifunctional process substantially increased crosslinking efficiency and hence improved the solvent resistance compared with the former studies. Guo et al.183 applied a commercially available low-k SU8 material to make a micrometer thick dielectric layer. Despite its low capacitance, the low-voltage operation was realized by reducing the sub-gap DOS in the channel. The mobility was approximately 0.4 cm2 V−1 s−1 under a low gate electric field of 0.02 MV cm −1 in TIPS-pentacene-based OTFTs, which was more than one order of magnitude lower than previous work with the same semiconductor. Furthermore, the OTFT was used to build logic circuits, which could be run faster while consuming less power.184-186 Photo crosslinking has also been adopted as an efficient and robust crosslinking route. Kwark et al.

utilized

the

photoactivated

thio-ene

reaction

for

the

crosslinking

of

the

poly[(mercaptopropyl)methyl-siloxane] (PMMS) dielectrics. UV radiation of 254 nm was needed for the crosslinking and meanwhile it made possible the photopatterning of the gate. The photocrosslinked PMMS showed reliable operation stability under curvature radius of 5.5-9.5 mm.187 Zhang et al.188 adopted a novel photo crosslinker BBP-4 under 365 nm UV light, which is applicable to a wide range of commercial methacrylate and styrenic polymer dielectrics (e.g. PMMA, PiBMA, PMS). All solution processed bottom-gate OFETs investigated were fabricated with TIPS-pentacene/PS OSC. The crosslinked gate dielectrics exhibited highly-improved solvent-resistance in chlorobenzene (blended solution of TIPS-pentacene/PS). The devices showed Ion/Ioff around 2 × 106 with the 49



Page 50 of 79

methacrylate polymers. 4.2. Bio-Polymer Dielectrics In recent years, more emphasis has been placed on green-processing, ease of fabrication and commercially competitive dielectric materials. Biomaterials are recognized as good candidates because of their wide resources, low toxicity, degradability and ease of production. The combination of bio-materials with OFET devices serves two main purposes. The first is the application of bio-based materials on the existing dielectric layer for surface modification and bio-sensing, and the second one is to make use of the bulk character of bio-materials as gate dielectrics.189 In the first part, the bio-modification of the dielectric interface grants the dielectric layer an optimized surface and biological sensing properties. Inserting bio-functional layers to construct OFETbased bio-sensors and their behaviors were thoroughly reviewed elsewhere.18 Herein, we focus primarily on tuning the interface through biosystems. The bio-engineering of a dielectric interface was reported to optimize the surface and control Vth. A peptide material, quartz binding polypeptides (QPBs) were reported by Dezieck et al.190 as a surface modifier for the SiO2 dielectric surface. Because of the pH response of this polymer by hydrogen bonding of its amino acid sequence, different dipole formations and orientations occurred at the interface. As a result, in an acidic solution, a positive shift of Vth was observed, while a negative one occurred in a basic solution. Cellulose was applied as an interlayer in a bilayered dielectric composed of Al2O3 and trimethylsilyl cellulose (TMSC).191-192 The smooth TMSC surface led to the growth of pentacene grains with the size between 150 and 300 nm. When combined with the high-k Al2O3 bottom layer, low-power functioning was realized with an operation voltage below 4 V. Both p-type and n-type transistors were produced, and the pentacene device showed a saturation mobility of 0.22 cm2 V−1 s−1. 50


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Figure 16. (a) Molecular formula of CTMA and the schematic of DNA–CTMA forming by the addition of CTMA surfactant groups to the backbone of DNA. (b) Energy level diagrams, without taking into account the interface dipole layers of the respective materials, for use in the fabrication of a p-type BioFET and an n-type Bio-FET. (c)-(d) The output and transfer characteristics of the n-type BioFET with PCBM semiconductor. (Adapted with permission from ref. 193. Copyright 2010 Springer). In addition to surface modification, biomaterials have been directly applied as bulk gate dielectrics to form a uniform layer to take the place of conventional synthesized polymer materials. Bio-macromolecules including DNA, proteins and other naturally occurring materials were investigated,

with

typical

examples

of

nucleobases,182

silk194

and

DNA-

hexadecyltrimethylammmonium chloride (DNA-CTMA)195 (Figure 16). DNA-based dielectrics are the most commonly studied bio-dielectric materials because of their inherent outstanding mechanical properties and tunable insulating behavior. The DNA-cetyltrimethylammonium (CTAM) complex was first studied as dielectric and exhibited a μsat of 0.05 cm2 V−1 s−1 in a pentacene-based device.193 51



Page 52 of 79

However, the main challenge of DNA-based dielectrics lies in the large hysteresis caused by the mobile charges, an inherent nature of the material. To address this issue, crosslinked DNA-CTMA films196 and hybrid DNA films197 were later developed. A natural protein, albumen, was reported by Guo’s group198 as a high-quality gate dielectric, and it can be obtained directly from eggs free of any extraction process. Figure 17 shows the crosslinking process of albumen. Hydrogen bonds formed in the denaturation process, where interchanges of amino acid side chains happened in protein molecules. Upon thermal treatment, an additional coagulation process occurred in which disulfide bridges formed between the protein molecules. They served as an additive-free self-crosslinking process that can greatly eliminate hysteresis and add to surface hydrophobicity. No hysteresis was found in the C60- and pentacene-based OFETs, and the output current reached 1.7-5×10−6 A at a gate voltage of ±25 V.

52


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Figure 17. (a) OFET device structure fabricated with chicken albumen gate dielectric and the separation of chicken albumen. (b) Illustration of albumen protein denaturation and crosslinking reaction under heat. (c) The output characteristics of a pentacene-based OFET. (d) The transfer characteristics of a pentacene-based OFET under forward and backward bias directions. (Adapted with permission from ref. 198. Copyright 2011 John Wiley & Sons Inc.) An ultrahigh field mobility up to 23.2 cm2 V−1 s−1 in a pentacene OFET device using silk fibroin dielectric was reported.194 Silk fibroin is a natural material featuring a highly ordered 3D secondary structure of β-pleated sheets formed by the hydrogen bonding within its amino acid sequences. The high mobility was made possible by the smooth dielectric surface, with a trap density of ca. 3.12×1011 cm−2eV−1. The presence of silk fibroin encouraged the formation of the orthorhombic phase of 53



Page 54 of 79

pentacene instead of the amorphous one and hence strengthened the charge transport.

5. Polymer Nanocomposite Gate Dielectrics The use of polymer nanocomposites as gate dielectrics is a combination of nanoscale inorganic materials (mostly ceramic nanoparticles (NPs)) and polymers. Among the high-k polymers studied, the further increase of the dielectric constant is limited by solely tuning the polymer structures. Inorganic materials, while having a large permittivity, suffer from poor mechanical properties and require a high-temperature deposition process, which is harmful to OFET substrates. Thus, by incorporating ceramic NPs into polymer matrix, the merits of inorganic ceramics and polymers can be combined to acquire a material with a high dielectric constant that exceed the upper limit of high-k polymers while retaining the flexibility and solution-processability at the same time. In addition to the increase in dielectric constant, decreases in both hysteresis and the leakage current were also observed when certain NPs were added. This could be attributed to the interfacial effect and the interaction between the metal oxide and polymer.58, 199-205 The most important issues concerning polymer nanocomposites are the uniform dispersion of NPs and their dielectric properties, which are affected by a number of factors such as the particle type, surface modification, loading and particle size. Meanwhile, the role of a polymer matrix with a high dielectric constant and mechanical robustness should also be taken into account. The high-k NPs investigated include titanium dioxide (TiO2),206-207 barium titanate (BTO),208 aluminum oxide (Al2O3),209 barium strontium titanate (BST),210 barium zirconate oxide (BZ),207 strontium titanate (SrTiO3)211 and zirconium oxide (ZrO2).212 The overall dielectric property of the composite is determined by particle size, loading, dispersion and the polymer matrix. In addition to the ceramic fillers, conductive NPs, such as carbon nanotubes and metallic particles, are also investigated to realize 54


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a high dielectric constant under a low particle loading, which are mostly applied to memory devices.147, 213-214

The size of the NPs determines the bulk dielectric constant of the ceramics due to the differences in crystal structures and polarization. Taking BTO nanoparticles at room temperature as an example, the dielectric constant increased with decreased particle size down to approximately 1000 nm and then decreased again below this size. The remnant polarization was determined by the size, which contributed to the increase of the dielectric constant above 1000 nm. Below this size, however, a change in the crystal structure was observed as the percent of tetragonal structure decreased with smaller size, and only a cubic or pseudocubic structure with a low dielectric constant remained at approximately 100 nm.79 Additionally, a similar trend was observed for TiO2 NPs at low frequencies with the maximum k value appearing at a size of approximately 17.8 nm.215 Taking advantage of the size effect, Takoudis et al.216 prepared a bimodal nanocomposite by using BTO particles of two different sizes (200 nm and 1000 nm) in an epoxy matrix. One merit of the bimodal nanocomposite was a doubled k value compared with the unimodal one under the same loading, with a capacitance density of 62 pF/mm2 (60% BTO loading). The high capacitance allowed for the preparation of a thick dielectric layer of 12 μm. Furthermore, using particles of different sizes also prevented large-scale agglomeration and increased the breakdown strength to 2.3 MV cm-1 at 1000 Hz. Particle loading is another factor in tuning the dielectric property. Generally, a higher loading generates a higher overall dielectric constant, but problems such as a decrease of the breakdown strength, higher leakage current and hysteresis inevitably arise. Meanwhile, the roughness caused by the increased loading content disrupts the transfer characteristics of the OFET devices. As a result, adjusting the NP content to an appropriate level is essential for device fabrication. 55



Page 56 of 79

In the study by Watkin et al.,212 using modified ZrO2 particles in a CYELP polymer, the increased particle loading showed a combined advantage of both decreased leakage current and higher k values. This effect was attributed to a binding reaction between ZrO2 particles and residual functional groups in the CYELP matrix, where the particles served as physical crosslinking sites. Additionally, the reaction minimized residual charge trapping groups (hydroxyl groups) to reduce hysteresis. A reduction of ΔVth from 1.2 ± 0.2 V to 0.2 ± 0.1 V was accompanied with increasing particle loading from 0 wt % to 70 wt %. The highest mobility of 8.0×10−2 cm2 V−1 s−1 was achieved under 50% loading using P3HT semiconductor. Another key factor in constructing nanocomposites lies in the homogeneous dispersion of the NPs. The NPs suffer from agglomeration when blended with polymers, which deteriorates the dielectric performance. As a result, efforts were made in the surface engineering of NPs to enhance the compatibility and uniform dispersion. Commonly used surface modification strategies include the coating of surfactants, chemical reactions with organic modifiers such as phosphonates,217 silane coupling agents,218 constructing self-assembled monolayers, and surface-initiated in situ polymerization.200, 208, 210, 219-222 The optimized dispersion brings about advantages including reduction of the leakage current, the potential of increasing nanoparticle loading, and control over the frequency dependence of dielectric constant. Roy et al.223 functionalized aluminum titanate (AT) NPs by n-octadecylphosphonic acid (ODPA) via a chemical bond between phosphonic acid groups and surface hydroxyl groups and then dispersed them into a PVP matrix. The ODPA was also found to consume the hydroxyl groups on the nanoparticle surface and eliminate the charge trapping sites. TFTs using both p-type pentacene and ntype F16CuPc were fabricated, with mobilities of ~0.4 cm2 V−1 s−1 and ~5×10-3cm2 V−1 s−1, respectively. 56


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The devices exhibited good mechanical robustness and flexibility, which enabled their application in bendable devices. The bending test showed that the mobilities of both TFTs increased approximately 15% under compressive strains (S=2.5%) and decreased by 17% under tensile strain (s= −2.5%).224 Recently, Halik et al.217 reported an ecofriendly chemical modification method that was universal for different metal oxide core-shell nanocomposites, such as TiO2, AlOx, Fe3O4, ITO, and CeO2, also using phosphonic groups via their coordination with the metal oxide surface. They modified the NPs with a self-assembling chain molecule (2-ethyl)phosphonic acid [CH3(OC2H4)3-PA] in which a hydrophilic tail enhanced the dispersion in green aqueous solution, as well as other polar solutions such as methanol, ethanol, and 2-propanol. The device performance employing different NPs was analyzed, with the best performance obtained with AlOx NPs yielding a mobility of 0.66 cm2 V−1 s−1 in a 2-tridecyl[1]benzothieno[3,2-b][1]benzothiophene (C13-BTBT) transistor (Figure 18). Devices on a bendable substrate polyethylene naphthalene (PEN) were also fabricated to evaluate the behavior under different bending modes.

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Figure 18. (a) Molecular structure of CH3(OC2H4)3-PA1 and the illustration of surface functionalization. (b) The molecular structure of the semiconductor C13-BTBT and a schematic of the OTFTs devices with the NP dielectric. (c) Transfer character of the OTFTs employing different NP dielectrics on a silicon wafer with 100 nm thermally grown oxide . (d) Pictures of concave bending test of the devices. (e) Transfer characteristics of the devices with the AlOx NP dielectric fabricated on a PEN substrate under different bending modes. (Adapted with permission from ref. 217. Copyright 2015 John Wiley & Sons Inc.). Oleic acid was reported to be a common surface modifier for TiO2 nanofillers.225 However, a further modification step is needed to achieve desired hydrophobicity and compatibility with a given matrix. Diethyl (2-cyanoethyl)phosphonate (DCP) can react with the oleic acid functional groups to achieve DCP-TiO2, and the processability of the NPs in polar solvents can be improved.206 Furthermore, the PS-modified TiO2 NPs were obtained through a ligand-exchange reaction with oleic acid and phosphonate terminated PS. The modified NPs were dispersed into a PS matrix with good affinity. An 58


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average mobility of 0.18 ± 0.03 cm2 V−1 s−1 was achieved in a pentacene device with pure TiO2-PS particles as the gate dielectric.226 Introducing chemical bonding directly between the fillers and matrix is another effective way to improve the overall uniformity. In this sense, photo-induced crosslinking or photo-patterning in dielectrics raised increasing interest due to the low processing temperature and more thorough reaction compared with thermal crosslinking. Park et al.227 reported a novel zirconium tetraacrylate (ZrTA) photo-crosslinkable hybrid gate dielectric, where the four acrylate groups can crosslink with each other to embed the Zr element in an organic matrix. The material exhibited favorable interfacial characteristics for the growth of a pentacene layer, and thus a relatively high mobility of 0.50 cm2 V−1 s−1 was displayed with low hysteresis. M.Shahbazi et al.228 used the sol-gel method with different amounts of 3-(trimethoxysilyl)propyl methacrylate (TMSPM) as the coupling agent to produce a PVP– SiO2–TMSPM hybrid nanocomposite. The in situ chemical bond formation between the filler and matrix led to an enhanced compatibility. According to the IDS-VG measurement, the mobility increased with decreased dielectric constant. The optimum mobility was found to be 0.058 cm2 V−1 s−1 with a sample dielectric constant of ~11.4. The role of the polymer matrix and its interaction with the nanocomposite should not be neglected either. New dielectric polymer matrices with a high dielectric constant and mechanical robustness are being explored. Cyanoethyl cellulose (CEC) is a promising candidate due to its high dielectric constant (~14) after substitution. It has good stability and low hysteresis compared with PVDF.229 The addition of BST NPs to CEC was found to increase the saturated mobility from 0.6 cm2 V−1 s−1 of pure CEC to 1.1 cm2 V−1 s−1 in a p-channel DPPT-TT OFET. Additionally, an additional PVP capping layer with a thickness below 50 nm suppressed leakage current to below 10-7 A cm-2 at ±3 V without a significant 59



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loss of capacitance.230 Amaratunga et al.231 reported cyanoethylated cellulose based dielectric nanocomposites with ultrahigh dielectric constants exceeding 100 with TiO2 NP loadings of 10% to 30%. The high dielectric constants, which exceed both the embedded nanofillers (TiO2) and the polymer matrix, were attributed to the specific HOMO-LUMO energy alignments between TiO2 and the cyanoethylated cellulose. It was hypothesized to play an important role in enhancing the charge transfer

in

the

interfacial

regions

of

the

nanocomposites.

The

elastomeric

polymer,

polydimethylsiloxane (PDMS), is also a good candidate as the polymer matrix due to its excellent stretchability and compatibility with elastomeric substrates. Wang et al. fabricated intrinsically stretchable OFET devices using the PDMS/BTO nanocomposite with BTO volume content up to 26%. The devices could be stretched beyond 50% strain along either two channel directions without degradation of performance after thousands of circles.232 Finally, it is worth noting that there are some novel concepts and approaches in the area of nanocomposite dielectrics. Wang et al.233 found that the spin-coating of polymers on sputtered C NPs was a novel route to achieve ultra-thin hybrid films, which was different from traditional inorganicorganic hybrid dielectrics as it did not require a high annealing temperature for the inorganic layer. The incorporation of C NPs enabled the formation of smooth, pinhole-free films because the strong interaction between the C NPs and polymer reinforced the adhesion of the polymer dielectric to the substrate. A surface roughness of 0.22 nm was found for a PS/C/SiO2 surface. Moreover, The C NPs combined with the polymer could enhance the mechanical properties. Thus a bendable device was fabricated on a flexible PET substrate, as shown in Figure 19. A mobility of 0.3 cm2 V−1 s−1 was achieved with a pentacene semiconductor, and highly stable IGS and IDS were observed under a long operation time of up to 3 × 104 s (Figure 19 (c) and (d)). 60


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Figure 19. (a) Scheme of a bendable pentacene-based OFET fabricated on flexible PET substrate. Inset is a photograph of the device. (b) Transfer characteristics (r VDS = −0.2 V) and (c) output characteristics of a pentacene-based flexible OFET with a PS/C dielectric. (d) Bias stress test demonstrating the operating stabilities of both IDS (left) and IGS(right). (Adapted with permission from ref. 233. Copyright 2016 John Wiley & Sons Inc.).

6. Summary and Perspectives Employing polymer-based gate dielectrics is a promising route to develop low-cost and flexible OFET devices attributed to their ease of processing and excellent mechanical flexibility. Because the charge-accumulation occurs in only a few nanometers from the semiconductor/dielectric interface, the gate dielectric layer plays a vital role in charge transport. To promote the development of polymerbased gate dielectrics toward practical applications, polymer dielectric materials, processing techniques, and relevant device physics all call for deeper and more comprehensively investigations. Regarding the materials, several kinds of polymer-based dielectrics have been considered as promising candidates. To achieve low-voltage operated OFETs, polymer dielectrics with high dielectric constants are pursued. Relaxor ferroelectric polymers and electrolyte-gated polymers are 61



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both investigated. However, dipole disorder and surface roughness still exist as major challenges in polar polymers and have a negative effect on the mobility and stability. Many researches focus on developing new high dielectric constant polymer structures to eliminate charge trapping by chemical modification, and searching for ways to enhance bias stability. In comparison, OFETs using low-k polymers show better stability and less leakage, while the challenge lies in the fabrication of ultra-thin and pinhole-free films. As a result, there are researches dealing with surface behaviors that affect growth and packing of overlying semiconductors. Novel crosslinking routes including lowtemperature thermal crosslinking and photo-crosslinking are developed. To combine the merits of polymer materials and traditionally used ceramic dielectrics, polymer nanocomposites are also promising candidates for gate dielectrics of OFETs. In addition to developing new polymer matrices and NPs, exploring facile and universal surface modifications of the NPs are also important for uniform dispersion and stable functioning. As for the processing techniques, low-temperature and energy-efficient solution-processing methods are desired. However, the performance of solution-processed OFETs need to be further optimized. Meanwhile, new techniques make it possible for the precise patterning and the scaling down of the devices using polymer materials. For example, the iCVD technique or the direct grafting of polymers onto the gate material help to achieve ultrathin and pinhole-free films with low leakage. Additionally, the dielectric-related device physics still needs to be further investigated. Some interfacial phenomena such as the diverse influences of dielectric surface on different semiconductors are waiting to be fully understood. More general and widely applicable conclusions are needed. The study of polymer-based dielectrics is an interdisciplinary field, therefore progress depends critically on more effective collaboration between areas including polymer science, physical chemistry, 62


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nanotechnology, and bioscience. Further optimization of OFET performance is needed as preferably the combination of high mobility, low operation voltage, high on/off ratio, and good bias-stability. Furthermore, the stability of some polymer dielectrics under ambient conditions (moisture and air sensitivity) should also be optimized to suit practical applications. Finally, rational modulation of polymer structures by synthetic methods toward multi-functional dielectrics is of vital importance for emerging memory devices, self-healing systems and stretchable electronics.

AUTHOR INFORMATION Corresponding Author *E-mail: [email protected] *E-mail: [email protected] Notes The authors declare no competing financial interest. ACKNOWLEDGEMENTS The authors thank National Natural Science Foundation of China (nos.51877132, 51522703, 51477096, 51673114) and National nKey Research and Development Program of China (2017YFA0207500). AUTHOR CONTRIBUTIONS X.H. conceived of the presented idea. Y.W. drafted the manuscript with input from all authors.

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