pubs.acs.org/NanoLett
Programmable Direct-Printing Nanowire Electronic Components Tae Il Lee,† Won Jin Choi,† Kyeong Ju Moon,† Ji Hyuk Choi,† Jyoti Prakash Kar,† Sachindra Nath Das,† Youn Sang Kim,‡ Hong Koo Baik,† and Jae Min Myoung*,† †
Department of Materials Science and Engineering, Yonsei University, Seoul, Korea, and ‡ Department of Nano Science and Technology, Graduate School of Convergence Science and Technology, Seoul National University, Seoul, Korea ABSTRACT In order for recently developed advanced nanowire (NW) devices1-5 to be produced on a large scale, high integration of the separately fabricated nanoscale devices into intentionally organized systems is indispensible. We suggest a unique fabrication route for semiconductor NW electronics. This route provides a high yield and a large degree of freedom positioning the device on the substrate. Hence, we can achieve not only a uniform performance of Si NW devices with high fabrication yields, suppressing deviceto-device variation, but also programmable integration of the NWs. Here, keeping pace with recent progress of direct-writing circuitry,6-8 we show the flexibility of our approach through the individual integrating, along with the three predesigned N-shaped sites. On each predesigned site, nine bottom gate p-type Si NW field-effect transistors classified according to their on-current level are programmably integrated. KEYWORDS Nanowire, programmable, direct printing, dielectrophoresis, visual inspection
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The vertically aligned Si NWs, synthesized by using an aqueous chemical-etching technique,18 are perfect single crystalline NWs, as shown in Figure 2. Commercial Si wafers (p-type, 〈100〉 oriented, 5-10 Ω cm) were cut to 1 × 2 cm pieces and were washed with trichloroethylene, acetone, isopropyl alcohol (IPA), and deionized water. They were then etched by using a 5% HF aqueous solution for 5 min at room temperature. The fresh Si surfaces were then H-terminated. The Si wafers were immediately dipped into an Ag coating solution containing 10% HF and 0.02 M AgNO3. The solution was slowly stirred for 1 min under air ambient. After a uniform layer of Ag was deposited, the wafers were washed with water to remove any extra Ag+ ions and the wafers were then immersed in an etchant composed of 10% HF and 0.6% H2O2 at 50 °C. After 120 min of etching in the dark at room temperature, the wafers were washed by using 10% HF to remove the oxide layer, and then the wafers were cleaned by using water. The wafers were then dried under a 6N-grade N2 flow. The Si NW arrays were characterized by using scanning electron microscopy (SEM) (JEOL, JSM7001F) equipped with EDX and high-resolution transmission electron microscopy (HRTEM) (JEOL, JEM 2100F). In Figure 2b, the HRTEM image is magnified from the white circle in the inset bright-field image. From the bright-field image, we can observe the noncircular cross section of the Si NWs. The electron diffraction pattern indicated that the NW was of single crystalline Si. To purify the Si NWs synthesized on the mother wafer, after being cut the NWs were dispersed into IPA by using sonication for 5 min and then the two-step centrifugation method was executed: first at 3000 rpm for 5 min and then at 4000 rpm for 5 min. Finally, we obtained a
ne-dimensional nanostructures including semiconductor nanowires (NWs), nanotubes, and quantum wires exhibit physical and chemical properties that make them promising building blocks for nanoscale electronic and optoelectronic devices.9-12 To realize such applications, researchers must overcome the fundamental and economic limitations of conventional lithography-based fabrication routes. There have been many reports of individual or arrays of NW devices prepared by dispersion and finding, electric field directed assembly,13 flow-assisted alignment,14 selective chemical patterning,15 and up to assembly of NWs using the Langmuir-Blodgett16 and blown bubble films techniques.17 However, a technique representing attractive building blocks for hierarchiral assembly of functional nanowire devices that could be fabricated on intentionally organized systems as we please is still required. Our key strategy for the programmable fabrication of NW devices is a three-step sequence involving the production of dielectrophoretic (DEP) arrays of NWs, visual inspection, and individual decaling on predesigned positions as shown in Figure 1. Unlike earlier reported methods,13-17 our approach to obtaining high yield fabrication with positioning freedom includes three aspects: automatic electrodes addressing, preliminary inspection of the active parts of the device, and programmable integration of the device.
* Corresponding author: Professor Jae Min Myoung, 134 Shinchon-dong, Seodaemoon-gu, Yonsei University, Seoul, Postal # 120-749. Telephone, (82-2)2123-2843. Fax: (82-2)312-5375. Corresponding author e-mail,
[email protected]. Received for review: 12/17/2009 Published on Web: 01/28/2010 © 2010 American Chemical Society
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DOI: 10.1021/nl904190y | Nano Lett. 2010, 10, 1016–1021
FIGURE 1. Overall process sequence of programmable NW device fabrication. Schematic diagrams show the overall sequence of NW device fabrication. There are four main steps in this diagram. On the PDMS block, the 10 µm electrode gap is defined as a source and drain pattern, as shown in the inset figure in this step. The second step is the DEP process, which involves scanning the bias probe tips continuously after suspending in the NW dispersed solution. NWs successfully attached between electrodes gap are shown in an inset figure of the second step. Many of Si NW bridges on the PDMS blocks were inspected by using optical microscopy at 1000 power magnification in the third step. Three groups were classified according to the number of NWs; 1-2 (red), 4-5 (green), and 7-9 (blue). The fourth step starts with the preparation of the predesigned gate electrode pattern by using thermal evaporation on the glass substrate. The PVP is then coated onto the substrate by using spin coating. After the perfect curing of the PVP, a second spin coating of PVP is executed as an adhesive and as a dielectric layer. The DEP method is used to buildup the arrays of the Si NWs automatically addressed between the electrodes on each PDMS block, then the structure of the registered NWs is converted into the Si NW transistor by using decaling, as described in the inset diagram of the fourth step. The well-sorted Si NW bridges on the PDMS blocks are decaled onto this substrate along the N-shaped gate electrode patterns. After all NW bridges are converted into bottom gate NW field-effect transistors, the source and drain pads are deposited by using thermal evaporation.
FIGURE 2. Si NW characteristics. (a) After the 2 h etching, the Si wafer is changed into vertically aligned rough Si NWs of about 100 µm. (b) The synthesized Si NW has a rough surface, and the near surface region contains about 1 nm of silicon dioxide, as shown in the TEM image. The synthesized NW has a single crystalline quality, and the direction of its axis is 〈100〉.
solution of NWs of 185 ( 20 nm diameter (see Supporting Information 1). On a cleaned 1 × 1 cm glass slide, a 5 mm thick poly(dimethylsiloxane) (PDMS) Dow Corning Silgard 184 (10:1, cured for 4 h at 80 °C) layer was formed as a contact © 2010 American Chemical Society
printing agent. To define the electrode gaps on this soft buffer layer, an 8 µm tungsten wire stencil was used. With a thermal evaporator, arrays of gold 10 µm gap electrodes were deposited onto each block of the PDMS surface. In the case of a thin gold layer (
