Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide

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Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide Transistors Yuan Liu, Jian Guo, Ye-Cun Wu, Enbo Zhu, Nathan O. Weiss, Qiyuan He, Hao Wu, Hung-Chieh Cheng, Yang Xu, Imran Shakir, Yu Huang, and Xiangfeng Duan Nano Lett., Just Accepted Manuscript • DOI: 10.1021/acs.nanolett.6b02713 • Publication Date (Web): 31 Aug 2016 Downloaded from http://pubs.acs.org on September 1, 2016

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Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide Transistors Yuan Liu†, Jian Guo†, Yecun Wu‡, Enbo Zhu†, Nathan O Weiss†, Qiyuan He‡, Hao Wu†, Hung-Chieh Cheng†, Yang Xu‡, Imran Shakir§, Yu Huang†,|| and Xiangfeng Duan*,†,|| †

Department of Materials Science and Engineering, University of California, Los

Angeles, CA 90095, USA; ‡Department of Chemistry and Biochemistry, University of California, Los Angeles, CA 90095, USA; §Sustainable Energy Technologies Centre, College of Engineering, King Saud University, Riyadh 11421,Kingdom of Saudi Arabia; ||California Nanosystems Institute, University of California, Los Angeles, CA 90095, USA. Abstract: Two-dimensional semiconductors (2DSCs) such as molybdenum disulfide (MoS2) have attracted intense interest as an alternative electronic material in the postsilicon era. However, the ON-current density achieved in 2DSC transistors to date is considerably lower than that of silicon devices, and it remains an open question whether 2DSC transistors can offer competitive performance. A high current device requires simultaneous minimization of the contact resistance and channel length, which is a non-trivial challenge for atomically thin 2DSCs, since the typical low contact resistance approaches for 2DSCs either degrade the electronic properties of the channel or are incompatible with the fabrication process for short channel devices. Here we report a new approach towards high-performance MoS2 transistors by using a

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physically assembled nanowire as a lift-off mask to create ultra-short channel devices with pristine MoS2 channel and self-aligned low resistance metal/graphene hybrid contact. With the optimized contact in short channel devices, we demonstrate sub-100 nm MoS2 transistor delivering a record high ON-current of 0.83 mA/ µm at 300 K and 1.48 mA/ µm at 20 K, which compares well with that of silicon devices. Our study, for the first time, demonstrates that the 2DSC transistors can offer comparable performance to the 2017 target for silicon transistors in International Technology Roadmap for Semiconductors (ITRS), marking an important milestone in 2DSC electronics. Keywords: MoS2 transistor, large current density, low contact resistance, short channel, self-alignment. TOC


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With a relatively large bandgap, atomically thin body and superior immunity to short channel effect, two-dimensional semiconductors (2DSCs) such as MoS2 are of particular interest for low power and high-speed electronic applications1-7. In general, the performance (e.g., the switching speed) of a transistor is largely dictated by the ONcurrent density (ION) that it can deliver. However, the reported ON-current density of MoS2 transistors is far from ideal, and it remains an open question for the community whether 2DSC transistors could ever deliver an electronic performance comparable with today’s silicon devices. To achieve a high performance transistor requires minimization of the contact resistance (Rc) and the channel length at the same time, which remains a critical challenge for atomically thin 2DSCs to date. Considerable efforts have been devoted to reducing the contact resistance of MoS2 transistors in the past few years. Early attempts focused on using low work function metals8 or the formation of metal-MoS2 bonding911

to enhance the electron injection and decrease the Rc. However, these approaches are

largely limited by Fermi level pinning and non-negligible Schottky barrier at the metal−MoS2 interface, regardless of the work function of the contact metals used8,12, delivering a typical contact resistance over 1 kΩ µm and a highest ON-current density of 0.24 mA/µm8, lagging behind that of state-of-art silicon devices (Rc105 can be observed when Vds3 µm). Figure 3a presents the contact resistance of Ni/graphene hybrid contact to a 10layer MoS2 device as a function of gate voltage at different temperature, demonstrating that Rc can be tuned by the back gate voltage, in agreement with previous reports12,24,27. The smallest Rc measured is 0.54 kΩ µm at a gate voltage of 25 V at room temperature, which shows ~10 times improvement over the control sample with Ni/MoS2 contact (~3-7 kΩ µm as shown in Supplementary Fig. S5). Compared with conventional metalMoS2 system, the insertion of graphene buffer layer offers two advantages. First, as a van der Waals physical buffer layer, graphene can protect the fragile MoS2 surface and minimize the evaporation-induced damage, thus greatly reduce the middle gap defect states and prevent Fermi level pinning effect. Secondly, as an electronic buffer layer, the positive back-gate voltage not only electrostatically dopes MoS2, but also moves the Fermi level of the graphene further up to better align with MoS2 conduction


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band18,28-30, therefore enhancing the electron injection from metal into the conduction band of MoS2. It is also important to note that the low contact resistance (0.54 kΩ µm) achieved in Ni/graphene/MoS2 stack is more than one order of magnitude improvement over the control sample with only graphene/MoS2 contact (~5-11 kΩ µm, as shown in Supplementary Fig. S6). This could be attributed to the reduced interlayer van der Waals gap due to the continued bombardment of metal atoms on graphene during metal deposition process, as well as the elimination of series resistance of graphene electrodes. Additionally, compared with graphene/MoS2 contact, the presence of metal layer increases the density of states in the hybrid stack system, thus enhances the electron tunneling probability. Besides gate voltage, Rc is also strongly dependent on the temperature (Fig. 3a). At ON state (Vbg =25 V), the Rc decreases upon cooling, reaching a lowest value of

∼0.21 kΩ µm at 20 K. This metallic like behavior demonstrates that the contact transport is influenced by phonon scattering at sufficient high carrier concentration (large Vbg). At low gate voltage regime, large Schottky barrier dominates the contact carrier transport and Rc increases upon cooling, demonstrating an insulating behavior and consistent with previous report27. We have further analyzed the channel sheet resistance (ρ) as a function of gate voltage under different measuring temperature (Fig. 3b). Similar to Rc, the channel resistance decreases with increasing gate voltage. At ON state (Vg=25 V), a lowest sheet resistance (ρ) of 9 kΩ/□ and 5 kΩ/□ can be achieved at 300 K and 20 K, respectively. Importantly, with an ultra-short channel length (~80 nm), the device


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channel resistance (~0.7 kΩ µm) is smaller than the total contact resistance (2Rc ~1.1 kΩ µm), indicating that the contact resistance dominates the overall transport process in the short channel devices, and the delivering current of the short channel device may be improved upon further reducing the Rc.

Figure 3. Contact resistance, channel resistance, effective mobility and Schottky barrier height of MoS2 transistors. (a) Gate dependent contact resistance of graphenemetal hybrid contact at various temperatures (300 K to 20 K). (b) Gate dependent channel resistance of MoS2 at various temperatures. (c) Two terminal extrinsic (black square) and intrinsic (red dot) mobility extracted from device in Figure 2. Measurement temperature is from 300 K to 20 K (with 20 K step). With decreasing temperature, the mobility increases due to the reduced phonon scattering. (d) Extracted Schottky barrier height vs. gate voltage at various bias voltages. With increasing bias voltage, the measured Schottky barrier height is reduced due to the superimposed field effect tunneling process. We have further extracted the two terminal field effect extrinsic (including the contact resistance) and intrinsic (subtracting the contact resistance) mobility from transconductance using equations µ=[dIds/dVbg] × [L/(WCiVds)], where L/W is the ratio


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between channel length and width, and Ci is the capacitance between the channel and the back gate per unit area (~1.03 × 10-7 F/cm2 for 60 nm thick SiNx gate dielectric). Overall, the filed-effect mobility µ increases with decreasing temperature, as a result of the reduced phonon scattering. It is noted that a maximum intrinsic mobility of 104 cm2/V s and 274 cm2/V s is achieved at room temperature and low temperature (60 K), respectively. These mobility values are comparable those achieved in long channel devices (as shown in Supplementary Fig. S7), confirming the physical integration and removal of NW process does not introduce additional damage or defects in the channel region. The extrinsic mobility derived without excluding the contact resistance is considerably lower since the device behavior is largely limited the contact resistance at the short channel limit. The output characteristics show non-linear behavior at low bias regime particularly at low-temperature (Fig. 2b), suggesting the existence of a finite Schottky barrier. We have extracted the effective Schottky barrier height (SBH) at various bias and gate voltages from Arrhenius plot (Fig. 3d). In general, the effective SBH is sensitive to doping concentration and decreases with increasing positive gate voltage, consistent with previous reports13,26. Notably, with the ultra-short channel length, the effective SBH is also largely influenced by measurement bias voltage. At low bias voltage (10 mV), relative large SBH is observed, ranging from 7 meV (Vg=25 V) to 65 meV (Vg=-10 V). This value is around 2 times lower compared with our control sample using Ni contact to MoS2 (Fig. S8), confirming the reduced Fermi level pinning by inserting vdW contacted graphene buffer layer. With increasing drain bias voltage, the effective SBH is greatly reduced, and a zero SBH value is extracted when Vds > 0.5 V. This can be explained that, at such short channel length, most of the bias voltage is


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applied on the MoS2 contact junction. Under this situation, the slope of Arrhenius plot does not necessarily reflect the SBH associated with a pure thermionic current31, where additional tunneling current contributes to a significant portion of the total current32, resulting in a considerable reduction of the derived effective SBH.

Lch

Eot

Rc

ION

IOFF

Vdd

µ

(nm)

(nm)

(kΩ µm)

(mA/ µm)

(nA/ µm)

(V)

(cm2/V s)

ITRS 2.0 HP 2017

18

NA

0.12

1.29

100

0.75

150

ITRS 2.0 LP 2017

20

NA

NA

0.64

0.1

0.75

150

ITRS HP 2001

65

1.3-1.6

0.09

0.9

10

1.2

NA

This work (300 K) @ 1V

80

34

0.57

0.64

1.1

1

51

This work (300 K) @ 1.5 V

80

34

0.54

0.76

214

1.5

44

This work (20 K) @ 1.5 V

80

34

0.21

1.39

89

1.5

125

Table 1 | Comparison of the performance the 80-nm MoS2 transistor achieved in this work to ITRS report of silicon transistor in 2001 (channel length: 65 nm) and ITRS target for 2017 in ITRS 2.0. Lch, Eot, HP, LP, Vdd ,and µ stand for channel length, equivalent oxide thickness, high performance, low power, supply voltage and effective extrinsic mobility, respectively. Table 1 summarizes the key performance parameters achieved in our short-channel MoS2 transistors, along with those of silicon transistors of similar channel length (65 nm, ITRS 2001) and ITRS 2017 target for silicon on insulator (SOI) transistors20. Several important points should be noted from this table. (1) Compared with silicon transistors with similar channel length (Lch=65 nm) in 2001 ITRS report, our MoS2 transistors could deliver comparable current density, indicating considerable potential


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of MoS2 as the silicon successor in future electronics. Furthermore, it is important to note that the MoS2 device (at 300 K and 1V bias) shows comparable performance to that of the state-of-art SOI devices (ITRS 2017 LP target), in spite of its longer channel length (80 nm vs. 20 nm) and much thicker gate dielectric (Eot 34 nm vs. ~0.75 nm). (2) To further evaluate the potential of MoS2, it is also meaningful to compare our results with ITRS high performance (HP) target. In general, the highest current density of the MoS2 devices is still lower than that of HP silicon devices, which is primarily limited by the large channel length (80 nm vs. 15 nm) as well as contact resistance in 2DSCs (0.54 kΩ µm vs. 0.12 kΩ µm). Shorter channel length device may be created by using smaller masking nanowires, which are however increasingly more difficult to lift off. Additionally, it is noted that the channel resistance only accounts less than 40% of the

total resistance even in our relatively long 80-nm device, suggesting that the contact resistance remains a primary limiting factor of the overall transistor performance in the aggressively scaled devices (e.g., channel length down to 20 nm). Further effort in improving the contact resistance remains to be a continuing challenge for 2DSC transistors. (3) Our low temperature studies (at 20 K) demonstrate comparable performance (Ion, Ioff, effective µ) with that of silicon HP devices at room temperature. Although achieved at low temperature, it clearly indicates that reducing phonon scatterings would be the key to further optimize device performance. To this end, the performance of the MoS2 transistors may be further improved by using high-K dielectric to screen phonon scattering33-35 or using boron nitride encapsulation to minimize interface-trapping scattering24,27,36. In summary, we have reported a unique approach to high-performance short channel MoS2 transistors by using nanowire as a physical lift-off mask to create


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ultrashort channel transistors with pristine channel and low-resistance self-aligned metal/graphene hybrid contact. With improved contact by inserting graphene as a physical and electronic buffer layer, we demonstrate sub-100 nm MoS2 transistors with a record high ION over 0.83 mA/ µm at 300 K and 1.48 mA/ µm at 20 K. Our studies, for the first time, demonstrate that the MoS2 transistors can deliver comparable performance to the ITRS targets of silicon devices, suggesting the exciting potential of MoS2 and other 2DSC transistors for high performance, low power application, especially at a time when the Moore’s law is approaching its end3. ASSOCIATED CONTENT Supporting Information. Detailed experimental process and supplementary information is described. This material is available free of charge via the Internet athttp://pubs.acs.org. Corresponding Author *

E-mail: [email protected]

Notes The authors declare no conflict of interest. ACKNOWLEDGEMENTS We acknowledge the Nanoelectronics Research Facility (NRF) at UCLA for technical support. X.D. acknowledges financial support by ONR through grant number N0001415-1-2368. Y. H. acknowledges the financial support from National Science Foundation EFRI-1433541. I.S. would like to extend his sincere appreciation to the Deanship of Scientific Research at the King Saudi University for its funding of this research through the Research Prolific Research Group, Project No PRG-1436-25.


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Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide

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