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Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes Julian J. McMorrow, Cory D. Cress, William A Gaviria Rojas, Michael L. Geier, Tobin J. Marks, and Mark C Hersam ACS Nano, Just Accepted Manuscript • DOI: 10.1021/acsnano.6b08561 • Publication Date (Web): 17 Feb 2017 Downloaded from http://pubs.acs.org on February 20, 2017

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Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes Julian J. McMorrow,† Cory D. Cress,# William A. Gaviria Rojas,† Michael L. Geier,† Tobin J. Marks,†,‡ and Mark C. Hersam*,†,‡,§ †Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois 60208 ‡Department of Chemistry, Northwestern University, Evanston, Illinois 60208 §Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, Illinois 60208 #U.S. Naval Research Laboratory, Washington, D.C. 20375

KEYWORDS SWCNT; CMOS; inverter; radiation; hardening; total ionizing dose

ABSTRACT Increasingly

complex

demonstrations

of

integrated

circuit

elements

based

on

semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail,

ACS Paragon Plus Environment

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low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation.

To further improve device stability, radiation-hardening approaches are

explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

Two decades of research have seen the emergence of single-walled carbon nanotubes (SWCNTs) as one of the most promising candidate materials for next-generation integrated circuit applications.1-3 Their extraordinarily high mobility and aspect ratio make them attractive for high-speed and aggressively scaled electronics,4,5 while their ability to be sorted,6,7 formulated into semiconducting inks8-10 and deposited into random-network morphologies are critical

to solution-processed,

large-area,

flexible

electronic

applications.11-18

Recent

developments in SWCNT processing and integration have enabled complex SWCNT integrated circuits,19-21 demonstrating the maturity of the technology. In particular, the use of organic layers as dopants and encapsulation22-25 has emerged as an effective means of achieving stable enhancement-mode SWCNT transistors, enabling rail-to-rail, low-power complementary metal-


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oxide-semiconductor (CMOS) operation and integration.26,27 Combined with their superlative electronic properties, these demonstrations of integrated SWCNT-based technologies hold promise for high-performance device applications.28 The nanometer-scale cross-section, strong C-C bonds, and low atomic number of semiconducting SWCNTs make them an especially attractive material for electronics in radiation environments.29,30 Computational results relating to the charge transferred to SWCNTs by incident radiation indicate an insensitivity to single-event effects in devices with solutionprocessable channel dimensions.31 Instead, the primary sensitivity of SWCNT-based electronic devices in aerospace environments is likely related to cumulative radiation exposure effects in the form of total ionizing dose (TID),32,33 which will act on the materials surrounding the SWCNTs to degrade device performance. Studies have explored these TID effects in nonintegrated SWCNT transistors, revealing the importance of controlling device atmosphere when gauging the radiation response.34-36 Beyond space radiation, materials are exposed to ionizing radiation in the form of energetic electrons37 or photons38,39 in common lithographic processing techniques, requiring an understanding of the TID response of emergent semiconductor technologies. The demonstration of critical CMOS logic elements by controlling the doping and encapsulation of solution-processed SWCNTs motivates the study of radiation effects at the system level in SWCNT integrated circuits. The organic overlayers and their charge-transfer complexes at SWCNT surfaces that enable the controlled doping necessary for CMOS operation could potentially present a unique vulnerability to the presence of radiation-induced trapped charge.

Furthermore, previous work exploring TID effects in p-type and n-type SWCNT

transistors have not included the controlled, enhancement-mode doping levels that are critical to


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rail-to-rail, low-power CMOS logic operation.40 It should also be noted that no study to date has utilized in operando characterization to assess the dynamic response of SWCNT-CMOS integrated circuits to radiation exposure. In this work, we present a systematic study of the TID response of enhancement-mode SWCNT-CMOS inverters. The devices feature solution-processed SWCNT semiconducting channels and organic dopants with robust encapsulation and stable charge transport characteristics. Inverter electronic properties are measured after incremental exposure to Co-60 γ-ray radiation with static bias applied, while a subset of devices is measured in operando to monitor their evolution under dynamic operation. Critical inverter operating parameters such as switching threshold voltage, noise margins, gain, and static dissipated power are reported as a function of TID. Fundamental degradation mechanisms are investigated under static bias conditions and are found to differ by dopant type and bias state. Self-recovery of radiationinduced degradation is further explored as a means of achieving radiation hardness, since the inverter transport properties recover as quickly as 20 minutes after the cessation of radiation dosing. Importantly, when irradiated under dynamic bias conditions to simulate typical integrated circuit operating conditions, the SWCNT-CMOS technology is shown to be TID-hard, deviating from pre-radiation operation by less than 2% of the supply voltage.

RESULTS AND DISCUSSION The device structure of the SWCNT-CMOS inverters discussed in this study is illustrated in Figure 1. A device cross-sectional schematic is included in Figure 1a, in which the layers that make up the back-gated structure, as well as the dopant and encapsulation layers, are depicted. A detailed description of the device fabrication is provided in the Methods section. Inverters are


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locally gated with an atomic layer deposition (ALD) Al2O3 gate dielectric. The constituent PMOS and NMOS transistors are bottom-contacted and locally back-gated, where randomly oriented networks of purified semiconducting SWCNTs are formed via vacuum filtration and film transfer. The PMOS device is doped and encapsulated by polymer photoresist while the NMOS device is doped by benzyl viologen, a small molecule organic n-type dopant.23 Conformal ALD Al2O3 overcoats the entire device, serving as an encapsulation layer. The featured device structure and its doping and encapsulation scheme have proven effective at enabling wafer-scale, stable, integrated SWCNT-CMOS devices.27 Importantly, the fabrication procedures featured here are compatible with flexible substrates,41 implying utility in nextgeneration flexible electronic applications. Figure 1b includes a top view optical micrograph of an inverter. PMOS and NMOS channel dimensions (length × width) are 20 μm × 50 μm and 20 μm × 150 μm, respectively. Figure 1c is an atomic force microscopy (AFM) derived image of the channel region of the devices in which the SWCNTs can be seen to have a linear density of ~10 SWCNTs per μm. These channel dimensions and the SWCNT density were optimized in previous work.27


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Figure 1. SWCNT-CMOS inverter structure. (a) Schematic cross-section of an inverter with labeled terminals and color-coded materials. Cross-section orientation with respect to (b) is indicated by the black dotted line. (b) Top view optical micrograph of an inverter with labeled terminals and 1:3 ratio of widths of PMOS (red) to NMOS (blue) channels. The black dotted line indicates the cross-section orientation with respect to (a). Scale bar is 100 m. (c) AFM image of the randomly oriented network SWCNT channel region. Scale bar is 2 m.

The charge-trapping efficiency of a dielectric under irradiation increases with applied field.42 As a result, it is critical to characterize the devices with in situ electrical bias during irradiation. The SWCNT-CMOS inverters in this study were therefore irradiated at the two lowHIGH) and Vin = GND = 0 V power states of the CMOS technology, Vin = VDD = 1.2 V (Vdose in (Vdose LOW). in

The charge transport characteristics of the SWCNT-CMOS inverters were

characterized before and after Co-60 γ-ray irradiation for sequentially larger doses up to 2 Mrad in Figure 2. Inverter voltage transfer characteristic (VTC, Vin-Vout curves) corresponding to dose increasing doses are shown in Figure 2a (Vdose in HIGH) and Figure 2c (Vin LOW). Qualitatively,

we find that the VTC behavior for both radiation bias conditions trends toward higher Vin with increasing dose. In the case of Vdose in HIGH, the largest single change between doses occurs at the first dose of 20 krad, while apparent shifting ceases at doses above 200 krad. The shift in VTC curves toward higher Vin is consistent with weakened pull-down balance in the CMOS inverter structure, or equivalently, an increase in PMOS on-state current relative to the NMOS. To elucidate the nature of these trends, charge transport within the constituent PMOS and NMOS transistor devices was measured independently and shown in Figure 2b, where the gate voltage is defined in the Methods. For all doses, we find that the PMOS transfer curves remain largely unchanged, while the NMOS on-state current is found to decrease considerably with


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increasing dose. Additionally, the large decrease in on-state current observed at 20 krad (pink star) and apparent lack of change observed above 200 krad are consistent with the VTC curves in Figure 2a. We therefore conclude that for Vin HIGH during irradiation, the observed shifting in the VTC curves can be largely attributed to changes in the NMOS device during irradiation. The shift of these NMOS transfer curves toward higher gate bias is consistent with an accumulation of electrons in the gate dielectric near the SWCNT channel. The adsorbate-driven trapping of negative charge during irradiation has been previously observed in unencapsulated SWCNT transistors.34,40,43 Although adsorbate effects are unlikely to play a role in the present encapsulated inverter devices, organic-passivated graphene transistors have been shown to trap electrons during irradiation.44 To further understand this observation, we consider the bias conditions of the PMOS and NMOS devices during irradiation in the schematic inset to Figure 2b. Here we see that the Vin HIGH condition leaves the NMOS channel populated by electrons while the PMOS channel is depleted. SWCNT NMOS channels have been shown to be susceptible to the injection and trapping of electrons from the SWCNT channel into the adjacent dielectric under DC bias conditions.45 Furthermore, the biases on the NMOS terminals are such that the gate dielectric has a uniform electric field (~ +1 MV/cm) across the length of the channel. During irradiation, this uniform electric field in the gate dielectric drives the separation of charges generated in the dielectric by incident energetic photons. Separated electrons could potentially be trapped in the Al2O3 gate dielectric, causing the observed shifting of the NMOS transfer curves toward higher positive gate biases.

Simultaneously, the PMOS channel is in depletion, eliminating hole

injection into the gate dielectric as a primary mechanism, and the dielectric layer under the channel experiences a non-uniform electric field, the largest being near the overlap of the Vout


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and Vin terminals. This condition results in minimal charge separation and trapping in the gate dielectric, consistent with minimal shifting of the PMOS transfer characteristics with increasing dose. The condition in which Vin is low during dose (Vdose LOW) yields VTC curves that shift in monotonically toward high Vin with increasing dose.

As in the case of Vdose HIGH, this in

observation is consistent with sequentially lower NMOS on-state currents relative to the PMOS on-state current. In Figure 2d, an examination of the transport properties of the constituent transistors confirms this expectation. However, in this case, shifting in both the PMOS and NMOS devices contributes to the changes in the inverter VTC curves. Given the schematic of the terminal biases for the Vdose LOW state (inset), we find that in this state, the PMOS channel in is populated with holes while the NMOS channel is depleted. The bias conditions of the PMOS terminals are such that the PMOS gate dielectric experiences a uniform electric field (~ -1 MV/cm) across the channel region, which would tend to drive trapped radiation-induced electrons toward the SWCNT channel in a manner consistent with the observed shift in the PMOS transport characteristics toward positive gate bias.

Simultaneously, the Vdose LOW in

NMOS device is found to also shift toward positive gate bias, but with a qualitatively different HIGH NMOS device and in greater magnitude than that behavior than that observed in the Vdose in observed in the Vdose HIGH PMOS device, despite their analogous bias conditions. The nature in of these differences is next examined by an analysis of the transistor subthreshold behavior.


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Figure 2. Inverter voltage transfer characteristic curves for sequentially higher TID for Vdose in HIGH (a) and Vdose in LOW (c), both of which trend toward higher Vin with increasing dose. (b, d) HIGH (b) and Vdose constituent PMOS (dashed) and NMOS (solid) transistor curves for Vdose in in LOW (d). Insets include schematic cross-section diagrams with labeled terminal voltage levels. Channels that are biased in accumulation during irradiation are highlighted in blue. The pink star in (a, b) highlights prominent shift in transport properties with the first dose (20 krad), emphasizing the correlation between the evolution of the VTC curves and the NMOS transfer curves.

Log-linear plots of the constituent PMOS and NMOS transistor devices for increasing TID exposure are provided in Figure 3. For the Vdose HIGH state (Figure 3a), the PMOS device is in


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largely unchanged with increasing dose while the curves for the Vdose LOW state (Figure 3c) in NMOS device shift toward positive gate bias. An ambipolar minimum is identified for the preradiation NMOS curves, which is a result of the doping level imparted by the benzyl viologen ntype dopant. With increasing dose, this current minimum for the Vdose in HIGH state NMOS device shifts toward forward gate bias with no change in the minimum value (pink arrow, Figure 3a). This observation is consistent with uniform electron trapping in the dielectric along the semiconducting channel, as identified in the analysis of the Vdose HIGH state bias conditions. In in contrast, the current minimum for the Vdose in LOW state moves both toward higher bias and higher drain current (green arrow, Figure 3c). This variation has been observed in similar n-type SWCNT transistors having small-molecule dopants in varying concentrations, thus varying doping levels.23,25,46 Additionally, it has been shown that modulation in the ambipolar minimum is consistent with a modification of the Schottky barrier height between the metal contacts and SWCNT channel.47,48 Therefore, the non-uniform field induced in the channel during biasing gives rise to radiation-induced spatial doping variations along the channel and the potential for Schottky barrier height modification, especially near the Vout contact. The changes observed in the subthreshold properties of these constituent transistors translate directly to the static dissipated power through the respective inverter devices. For the Vdose in HIGH state (Figure 3b), the nearly constant behavior of the PMOS device with dose mirrors the lack of change in the power dissipated at Vin = VDD (shaded red) and the increase in the NMOS current at zero gate voltage tracks with the increase in power dissipated at Vin = 0 (shaded blue). Furthermore, the minimum in the dissipated power near Vin LOW shifts strictly toward higher input voltage, like the ambipolar minimum in the NMOS device (pink arrows). For the Vdose in LOW state (Figure 3d), the increasing (decreasing) power dissipation at Vin LOW (HIGH)


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correlates with the increasing (decreasing) current through the NMOS (PMOS) device at zero gate voltage. Additionally, the minimum in the dissipated power near Vin LOW shifts toward higher Vin and higher power, similar to the shifting observed in the ambipolar minimum in the NMOS device (green arrows).

Figure 3.

Subthreshold properties of the inverter constituent transistors for sequentially

dose dose increasing TID for Vdose in HIGH (a) and Vin LOW (c). Dissipated power for Vin HIGH (b) and

LOW (d). Lateral shift (pink arrows) and upward shift (green arrows) in transport minima Vdose in emphasize the correlation between the NMOS subthreshold properties and the dissipated power in the inverter.


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The qualitative trends identified in Figure 3 are quantified as functions of TID in Figure 4, in which the inverter properties (red, left axes) are correlated with the relevant properties of the constituent transistors (blue, right axes). Figure 4a plots the inverter switching threshold voltage (VM, where Vin = Vout) and noise margins for Vdose HIGH. In this representation, the input in voltages in which the inverter Vout is HIGH or LOW are shaded red, while the voltage window in which the inverter is in transition is white. The large shift in VM at the first dose and the plateau at high TID agree with observations of the VTC curves in Figure 2a. The noise margins track with VM, confirming that the shape of the VTC curve does not change appreciably as a function of dose. Inverter VM is related to the symmetry in the current within the PMOS and NMOS transistors. We quantify this symmetry by computing the ratio of the maximum PMOS current and maximum NMOS current and find that this parameter correlates well with VM as a function of dose.

These maximum NMOS and PMOS currents are provided in Figure S1a of the

Supporting Information. The changes in the current ratio, and therefore VM, are attributed to changes in the NMOS device because the PMOS device changes negligibly with dose in this bias LOW dose case. Because the overall shift in state. Figure 4b is an analogous plot for the Vdose in VM (73 mV) is less than the Vdose HIGH case (150 mV), we conclude that the Vdose LOW bias in in state is less sensitive to TID. Figure 4c examines the correlation between the inverter static power dissipation (all red symbols) and the off-state current of the constituent transistors, where the blue solid symbols denote NMOS device currents and open symbols denote PMOS device currents. The static bias condition during irradiation, Vdose HIGH and LOW, are denoted by upward facing and in downward facing triangles, respectively. At Vin = 0, the PMOS channel is activated, allowing Vout to rise to VDD. Under these conditions, a large field exists across the NMOS channel, and the


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power dissipated by the inverter in this state is expected to be correlated with the leakage current of the NMOS device. We indeed observe this correlation between the inverter dissipated power at Vin = 0 (red, solid triangles) and the NMOS current at Vg = 0 (blue, solid triangles) for both Vdose states. Analogously, the PMOS leakage current at Vg = 0 (blue, open triangles) correlates in with the dissipated power at Vin = VDD (red, open triangles), although the magnitude is much lower and weakly varying with dose. These PMOS and NMOS current values at Vg = 0 are provided on a log scale in Figure S1b of the Supporting Information. These relationships show that the NMOS-related parameters vary strongly with increasing dose while the PMOS-related parameters exhibit over an order of magnitude smaller change than the NMOS, thus establishing the NMOS channel to be the more radiation-sensitive for this SWCNT-CMOS technology. Increased static power consumption is deleterious to system-level CMOS implementation, thus warranting further investigation of the root cause. An examination of the current on/off ratios for the PMOS and NMOS devices for both Vdose HIGH and LOW states (Figure S1c) in reveals a slight improvement in PMOS on/off ratio with increasing dose, while the NMOS on/off ratios decrease by up to an order of magnitude. The trend of increasing static power consumption states is due to the downward slope of the power dissipation curve, at Vin LOW for both Vdose in which is related to the ambipolar minimum observed in the NMOS devices near Vg = 0. Because the nature of this ambipolar minimum is a function of the level of n-type doping experienced by the SWCNT channel, it should be possible to reverse this trend of increasing power dissipation with increasing dose by increasing the n-type doping during fabrication. The maximum magnitude of the change in VM up to 2 Mrad TID relative to the pre-rad state (150 mV and 73 HIGH and LOW, respectively) corresponds to 12% and 6.1% of VDD. Overall, mV for Vdose in


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these results are favorable for the radiation hardness of this SWCNT-CMOS technology at space-relevant doses.

Figure 4. SWCNT-CMOS inverter properties (left axes, red) and correlated transport properties of the constituent transistors (right axes, blue) as a function of TID. Inverter switching threshold voltage (left axes) and ratio of maximum drain current of PMOS to NMOS constituent transistors for Vdose HIGH (a) and Vdose LOW (b) (right axes). (c) Dissipated power through the inverter at in in Vin HIGH or Vin LOW (left axis) and current through constituent PMOS or NMOS devices at zero gate voltage (right axis).

NMOS-related values (solid markers) vary by an order of

magnitude larger than PMOS (open markers).

CMOS inverter gain is a measure of the effectiveness with which the device switches between Vout states. High gain corresponds to wider noise margins and smaller transition voltage windows.

The SWCNT-CMOS devices in this study exhibit peak gain in excess of 12,

consistent with previous work on this technology.26 Figure 5 illustrates the evolution of the HIGH (Figure 5a) and LOW inverter gain behavior with increasing TID. For both the Vdose in (Figure 5b) cases, the peak gain position trends with VM, shifting toward higher Vin values with increasing dose. The peak gain values for both dose states are plotted as a function of dose in Figure 5c. The peak gain is found to vary weakly with dose, neither increasing nor decreasing


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significantly up to 2 Mrad TID. The apparent noise in this value at various dose steps is likely due to the finite voltage step of the VTC sweep limiting the resolution when computing its derivative, and thus its gain. The lack of change in gain corroborates the conclusion that the transition voltage window remains largely unaffected by TID, which further shows the radiation hardness of this SWCNT-CMOS technology.

Figure 5. Inverter voltage gain as function of Vin for sequentially higher TID for Vdose in HIGH (a) and Vdose LOW (b). (c) Peak gain as a function of dose for Vdose HIGH (red) and Vdose LOW in in in (blue), both of which exhibit minimal degradation with increasing dose.

Following irradiation, the inverter devices were removed from the radiation source and held under the same static bias conditions as those used during irradiation. The resulting VTC curves and constituent transistor data are featured in Figure 6. Following removal from the radiation source, the radiation-induced changes in the device electrostatics stemming from trapped charges and modifications of contact barrier heights subside and the effects of TID exposure are diminished over time. Figure 6a shows that after a 20 min static bias, the Vdose HIGH device in exhibits a partial recovery of the post-2 Mrad curve toward the original pre-radiation curve. For the Vdose LOW device (Figure 6c), this 20 min static bias is enough to recover the post-2 Mrad in


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device properties to essentially the pre-irradiation condition. Examination of the recovery of the constituent transistors confirms that the recovery occurs as the reverse of the radiation-induced modification of the sensitive components of the inverters. Namely, the Vdose HIGH (Figure 6b) in PMOS device is unaffected by the incident radiation and remains unchanged under continued static bias, while the NMOS device shifts toward higher forward bias under irradiation and LOW (Figure 6d) devices shift toward recovers toward negative gate bias. Likewise, both Vdose in positive gate bias with irradiation and recover in the opposite direction toward negative gate bias. Recovery of the dissipated power and voltage gain properties follow similar trends (Supporting Information Figure S2). Quantifying the recovery by switching threshold voltage indicates a slight difference in recovery after 20 min, 49 mV (34% recovery) and 67 mV (92% recovery) for the Vdose HIGH and LOW cases, respectively. This observation likely reflects differences in the in amount of trapped charge for each bias state and dopant system as well as differences in each of the associated time constants for trapped charge recombination.


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Figure 6. Recovery of inverter transport properties after devices are removed from irradiation. HIGH (a) while full After 20 minutes of recovery, VTC properties recover partially for Vdose in recovery is observed for Vdose LOW (c). Recovery of the constituent transistor devices (b, d) in indicates consistent reversal of trends observed during irradiation.

The dose rate featured in these results (530 rad/s) is artificially high compared to the actual space environment (10-4 – 10-2 rad/s).49 If the dose rate is low enough that the rate of charge recombination meets or exceeds the rate of charge capture, the device will exhibit no change as a result of TID. Thus, it is expected that this SWCNT-CMOS technology would be TID-hard in


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the space environment.

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The static bias conditions featured thus far further represents an

unrealistic operating case in which radiation-induced charges experience applied electric fields that do not change with time. In integrated circuit applications, CMOS devices are clocked and switch bias states frequently. Thus, a more realistic bias condition features a clocked Vin signal during TID exposure. 50-52 To explore this case, the fully recovered device previously featured in the Vdose LOW static bias case was further irradiated while biased under dynamic Vin conditions. in Figure 7a plots Vin, Vout, and the total dissipated power before, during, and after an additional accumulated dose of 1.2 Mrad. Before irradiation, the Vin signal was inverted with appropriate rail-to-rail operation, and the dissipated power was ~2 nW for Vin LOW and ~0.2 nW for Vin HIGH. The inverting function is preserved during irradiation, where Vout deviates < 30 mV from the rail voltage, and the dissipated power is elevated to 2 – 4 nW. Following a dose of 1.2 Mrad, the device were removed from the radiation, where the rail-to-rail behavior and dissipated power at Vin HIGH are restored while the dissipated power at Vin LOW is now ~ 3 nW. These results suggest minimal change in the inverter operation when irradiated under clocked Vin conditions. Figure 7b confirms this conclusion by comparing the VTC curve for the post-1.2 Mrad dynamic bias state (green) to the pre-radiation (black) and recovered post-2 Mrad static bias (red) states. Here, the dynamic bias curve is nearly indistinguishable from either of the other curves, exhibiting VM, noise margin high, and noise margin low values that are within 9 mV, 2 mV, and 7 mV of the pre-radiation values, respectively. We note that dynamic biasing enables charge trapping in transition bias states not considered when biasing in the static Vdose HIGH or LOW in states. Dynamic biasing thus may allow for more rapid charge normalization, but also give rise to unexplored charge trapping mechanisms that could account for the shift in VTC properties toward lower Vin values, since VM changes from 632 mV to 617 mV when irradiated during


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dynamic operation. This voltage shift corresponds to 1.3% of VDD, demonstrating that dynamic biasing during irradiation is the most TID-hard mode of operation for this SWCNT-CMOS technology. These results, in addition to the high rate of recovery compared to the low space radiation dose rate, suggest TID-hard operation in space applications.

Figure 7. Effect of dynamic biasing during irradiation. (a) Vin, Vout, and dissipated power at the beginning (top) and end (bottom) of 1.2 Mrad irradiation, exhibiting slight deviations from the rail voltages and increased dissipated power during irradiation.

(b)

VTC curves before

irradiation (black), after static bias irradiation and recovery (red), and after dynamic bias (green), which demonstrate radiation hardness of the SWCNT-CMOS inverter under various biasing and irradiation conditions.

CONCLUSIONS A TID-hard SWCNT-CMOS technology is demonstrated here. Using organic dopant and encapsulation layers to achieve enhancement-mode transistors, the radiation response of rail-torail and low-power CMOS inverters is characterized for the first time. By making use of in situ charge transport characterization, the present CMOS inverters are found to exhibit differing degradation behaviors under different bias conditions. Both stable CMOS bias conditions result


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in an accumulation of radiation-induced trapped electrons, although the p-type and n-type devices are found to respond differently to the proximate accumulation of charge. An examination of the constituent transistors reveals the NMOS device to be the most sensitive component of the inverter system, the effects of which dominate those of the PMOS degradation by an order of magnitude. When devices are allowed to rest after high dose rate irradiation, the effects of aerospace-relevant levels of accumulated dose are negated within minutes, suggesting radiation hardness under mission-relevant dose rates. Finally, when the devices are irradiated under dynamic bias conditions that better resemble CMOS operation, the SWCNT inverters are minimally affected by TID, demonstrating a radiation-hard operation mode. These results thus represent a promising step toward the inclusion of large-area SWCNT-based electronics in future space and satellite applications.

METHODS Inverter Fabrication A silicon oxide wafer (300 nm dry thermal) was cleaved and cleaned with acetone and isopropyl

alcohol

(IPA).

A

gate

metallization

layer

mask

was

then

patterned

photolithographically, followed by the thermal evaporation of a Ni gate layer (20 nm at 1 Å/s, < 7 × 10-6 Torr base pressure) and subsequent photomask liftoff. A conformal 10 nm Al2O3 gate dielectric layer was next deposited via ALD (trimethyl aluminum/H2O, 113 cycles at 150 °C). An interconnect was etched through the gate dielectric by first patterning an etch mask photolithographically in alignment with the gate metal layer, followed by a reactive ion etch (RIE, 15 mTorr base pressure, 10 sccm CF4 + 40 sccm Ar at 100W for 6 min), and photomask liftoff. The contact metallization layer was subsequently patterned photolithographically in


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alignment with the gate metal layer, followed by thermal evaporation of a Cr adhesion layer (5 nm at 1 Å/s, < 7 × 10-6 Torr base pressure) and gold contact layer (75 nm at 1.5 Å/s, < 4 × 10-6 Torr base pressure), and photomask liftoff. An aqueous dispersion of purified semiconducting SWCNTs was prepared as described previously.27 A SWCNT random network film was then produced by vacuum filtering a dispersion of purified 99% semiconducting SWCNTs through a cellulose filter membrane (Millipore VMWP 0.05 m pore). The resulting SWCNT film and filter membrane were wetted with IPA and pressed onto the inverter structure, SWCNT side down. The substrate was then submerged into an acetone bath and removed after several hours, resulting in a random network SWCNT film for the inverters. The SWCNT channels were next defined photolithographically, and the excess SWCNTs were etched via RIE (200 mTorr base pressure, 20 sccm O2 at 100W for 15 sec) followed by photomask liftoff.

SWCNT Doping and Encapsulation Benzyl viologen dichloride (0.1 g, 97%, Sigma Aldrich) was dissolved in deionized water (5 mL). A biphasic solution was formed by adding toluene (2 mL, >99.5%, Sigma Aldrich) to the top of the solution. Sodium borohydride (>98% Sigma Aldrich) in water (1 mL, 200 mM) was then added as a reducing agent. This procedure causes the benzyl viologen solution to turn purple and evolve H2 gas. The solution was left to react overnight, after which the benzyl viologen in toluene (~10 mM) was decanted for use in SWCNT n-type doping. The undoped SWCNT inverter structure was vacuum annealed (150 °C at ~100 mTorr for 1 h) in a N2 glove box environment to drive off atmospheric adsorbates. Without exposure to ambient, a layer of photoresist (Shipley S1813) was spin-coated on the substrate. In ambient, the


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features to encapsulate the p-type channel regions were patterned photolithographically, and the devices were vacuum annealed again, simultaneously hard-baking the photoresist p-type encapsulant and driving off atmospheric adsorbates. The n-type channel was subsequently doped by spin coating the benzyl viologen toluene solution onto the vacuum annealed substrate (1 min at 1000 rpm) in an N2 environment, followed by annealing on a hot plate (1 min at 115 °C). The substrate was then transferred briefly in ambient to the ALD chamber, at which point the final Al2O3 encapsulation layer (~50 nm) was conformally deposited (500 cycles at 115 °C).

Inverter Characterization The electronic properties of the inverters were characterized using a probe station and Keithley 4200 Semiconductor Characterization System. Inverter VTC (Vin-Vout) curves were measured with four probes: VDD, GND, Vin, Vout. Constant VDD was applied, Vin was swept between Vin = 0 V and Vin = VDD, and Vout was measured at a constant current (Iout = 0). The switching threshold voltage was computed as the voltage at which the Vin-Vout curve intersects a diagonal line corresponding to Vin = Vout. The inverter gain as a function of Vin was computed as the absolute value of the derivative of the Vin-Vout curve. The noise margins were computed as the Vin values at which the inverter gain curve equals 1. The dissipated power as a function of Vin was computed as the current measured at the GND terminal multiplied by VDD. The transport properties of an individual NMOS (PMOS) transistor within an inverter were probed by fixing the Vout terminal bias to VDD (-VDD), the VDD terminal to VDD (-VDD) and sweeping Vin as the transistor gate (Vg) from 0 to VDD (-VDD). The drain current was measured at the Vout terminal.

Radiation Exposure


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Before irradiation, devices were purged under N2 to minimize ambient moisture and the generation of ozone during irradiation.53 Devices were biased at constant Vin conditions (Vin = 0 LOW dose and Vdose HIGH, respectively) to saturate any bias stress V or Vin = VDD for Vdose in in mechanisms and stabilize VTC curves. During irradiation and subsequent measurements, the devices were kept under N2 in a closed vessel. Inverter devices were irradiated by a Co-60 γ-ray source at a dose rate of 530 rad(Si)/s. Devices were monitored in situ during dosing, and inverter VTC curves and transistor sweeps were measured between doses.

ASSOCIATED CONTENT Supporting Information The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsnano.xxxxxxx. On-state and off-state current and current on/off ratio data for the constituent PMOS and NMOS devices; recovery data for the inverter dissipated power and voltage gain. AUTHOR INFORMATION Corresponding Author *E-mail: [email protected]. Author Contributions The manuscript was written with contributions of all authors. All authors have given approval to the final version of the manuscript. Notes


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The authors declare no competing financial interest.

ACKNOWLEDGMENT This work was supported by the MRSEC program of the National Science Foundation (DMR-1121262), the National Aeronautics and Space Administration NSTRF Grant NNX12AM44H, ONR MURI Grant N00014-11-1-0690, and the Defense Threat Reduction Agency (MIPR #HDTRA-15-15399). W.A.G.R. acknowledges support from the National Science Foundation Graduate Research Fellowship Program. This work made use of the EPIC, Keck-II, and SPID facilities of the Northwestern University NUANCE Center, which has received support from the Soft and Hybrid Nanotechnology Experimental (SHyNE) Resource (NSF NNCI-1542205); the MRSEC program (NSF DMR-1121262); the International Institute for Nanotechnology (IIN); the Keck Foundation; and the State of Illinois. REFERENCES (1)

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