NANO LETTERS
Realization of a Linear Germanium Nanowire p−n Junction
2006 Vol. 6, No. 9 2070-2074
Emanuel Tutuc, Joerg Appenzeller, Mark C. Reuter, and Supratik Guha* I.B.M. TJ Watson Research Center, Yorktown Heights, New York 10598 Received June 9, 2006; Revised Manuscript Received July 19, 2006
ABSTRACT Germanium nanowires grown by chemical vapor deposition exhibit a peculiar dopant incorporation mechanism. The dopant atoms, such as boron and phosphorus, get incorporated through the wire surface, a mechanism which limits the doping modulation along the wire length, and therefore the fabrication of more elaborate structures that combine both n- and p-type doping. Using a novel device design that circumvents these constraints, we demonstrate here a linear Ge nanowire p−n junction.
Self-assembled, metal-catalyzed semiconductor nanowires1 have received increased interest lately, partly in response to issues of complementary metal-oxide semiconductor (CMOS) technology scaling.2 Indeed, the metal-catalyst-mediated growth of semiconductor nanowire structures offers a unique bottom-up approach for device fabrication down to around 10 nm. The growth mechanism of the semiconductor nanowire also offers the possibility of realizing axial heterostructures. Examples include axial InAs/InP3 and GaAs/ GaP4 heterostructres in III-V compounds, as well as axially modulated composition in SixGe1-x nanowires.5 Furthermore, their electronic doping, a necessary ingredient for CMOS device fabrication, appears a straightforward extension of the vastly studied bulk semiconductor doping. For example, group IV semiconductor nanowires such as Si and Ge, can be n- or p-type doped with phosphorus or boron by exposing them to PH3 or B2H6 during growth. Despite the relative simplicity of achieving in situ electronic doping of nanowires during the growth phase, the dopant atom incorporation mechanism differs significantly from that of the host semiconductor nanowire growth. The metal-catalyzed synthesis of self-assembled silicon and germanium nanowires has been qualitatively described by the vapor-liquid-solid (VLS) mechanism: the source gas molecules (e.g., SiH4 or GeH4) dissociate at the metal catalyst droplet, diffuse through the droplet, and then condense at the catalyst-substrate interface, thereby forming a solid.1 Electronic doping can be achieved by introducing PH3 or B2H6 gases in the nanowire growth ambient. However, in the case of Ge nanowires the dominant mechanism for P and B atoms incorporation is through the nanowire surface and not at the catalyst level via the VLS mechanism. This observation is based on our detailed study of the doping incorporation mechanism in Ge nanowires. For example, if * Corresponding author,
[email protected]. 10.1021/nl061338f CCC: $33.50 Published on Web 08/04/2006
© 2006 American Chemical Society
a doping agent, e.g., PH3, is introduced midway during the nanowire growth, the device characteristics indicate the nanowire is electrically doped along its entire length. As such, the presence of such doping a agent at any stage of the growth renders the entire existing nanowire electronically doped, thereby severely limiting the longitudinal doping modulation and the realization of longitudinal nanowire structures with alternating doping characters.6 Additionally, the p-type dopant agents such as B2H6 dramatically enhance the semiconductor conformal growth7 resulting in tapered nanowire structures.8 Using a novel device design that circumvents some of these constraints, we demonstrate here a longitudinally modulated Ge nanowire p-n junction. Furthermore, from a careful analysis of our device characteristics we locate the position of the p-n junction along the nanowire to within 600 nm. Our samples are grown on Si(111) substrates in a chemical vapor deposition chamber. Prior to loading, a 10 Å thick Au film is deposited on the H-terminated Si(111) surface. The substrate is then annealed in situ at a temperature T ) 500 °C in an atmosphere of H2 in order for the Au film to form droplets, followed by a cool down to the growth temperature T ) 285 °C. The growth sequence of our nanowire devices is outlined in Figure 1a. We commence the growth by exposing the substrate to an ambient of GeH4 (10% in a helium mixture) at a 60 sccm flow rate and PH3 (20 ppm in helium) at a 10 sccm flow rate, at a total pressure of 5 Torr. A 1 h growth at these conditions results in a Ge nanowire segment with a typical length of 3 µm ((0.5 µm), and as we show below, our device characteristics demonstrate this segment is n-type doped. A second, nominally undoped Ge segment of approximately the same length is grown atop the first nanowire segment by exposing the substrate to an ambient of GeH4 (10% in a helium mixture) at a 60 sccm
Figure 1. (a) Growth sequence of our Ge p-n junctions. (b) SEM of a typical Ge nanowire growth on a Si(111) substrate, showing predominantly vertical nanowires aligned with the (111) crystal axes.
Figure 2. (a) SEM of a multifinger nanowire device, which is used to probe the local doping character along the wire length. Device characteristics, Id-Vds (main panel) and Id-Vgs (inset), measured on the devices located on sections I (panel b) and III (panel c) of the wire. The data evince a heavily n-doped lower section (I) and lightly p-doped upper section (III) of the wire.
flow rate, at a total pressure of 5 Torr. Last, a thin B-doped Ge shell capping the whole nanowire is grown. The B-doped Ge shell is grown using 60 sccm GeH4 (10%) and 10 sccm B2H6 (20 ppm), at a total pressure of 5 Torr, T ) 285 °C for a shell growth time of 7 min.9 Figure 1b shows an example of predominantly vertical growth of Ge nanowires on a Si(111) substrate, which demonstrates the epitaxial growth of Ge nanowires as well as identifies the growth direction as the (111) crystal axis. We have further verified this by performing a reciprocal space mapping using X-ray diffraction.8 Our Ge nanowires are slightly tapered, with typical base diameters of =60 nm and tip diameters of =20 nm, for wire lengths of =6 µm. To locally probe the electrical properties and doping character along the Ge nanowires, we fabricate multifinger devices with parallel metal contacts spaced by 500 nm gaps spanning the nanowire, as shown in Figure 2a. First, we Nano Lett., Vol. 6, No. 9, 2006
disperse the nanowires in an ethanol solution. The nanowire solution is then spun onto a 10 nm thick SiO2 dielectric, grown on an n-type Si wafer which serves as a back-gate for our devices. Using e-beam lithography, followed by a 600 Å Ni deposition and lift off, we define the metal terminals for our nanowire devices. Last, we anneal the devices in a reducing ambient at 110 °C for 20 min in order to improve the metal-nanowire contact. We interrogate our devices as follows. Every two adjacent metal contacts placed on the nanowires together with the Si substrate forms a threeterminal, nanowire field effect transistor (FET) device. The metal contacts serve as source and drain respectively, while the Si substrate is used as a back-gate in order to modulate the nanowire carrier density. The electrical characteristics of these devices are then used to extract information about the electronic doping along the length of the nanowire. We measure two types of electrical characteristics: (i) the drain 2071
Figure 3. (a) Comparison of the transfer characteristics measured on the n-type (red stars) and p-type (blue circles) sections of the wire, and the device where the two terminals are located on the n- and p-type sections (orange triangles), respectively. (b) Rectifying Id-Vds characteristics measured across the p-n junction device. For consistency, in all measurements the source is the metal contact placed closer to the wire’s base, e.g., for the p-n device the source is the n-type contact. The line represents the ideal diode model fit to the data for Vgs ) -2 V, using I 0 ) 10-9 A and n ) 2.
current (Id) vs the applied drain-source bias (Vds) at fixed values of the gate-source bias (Vgs) (output characteristics), and (ii) the drain current (Id) vs the applied Vgs at fixed values of Vds (transfer characteristics). For consistency, in each device the source contact is chosen to be the metal contact located closer to the nanowire’s base. We now examine the device characteristics of our nanowire FETs. In Figure 2b we show an example of output (main panel) and transfer (inset) characteristics measured on nanowire FETs located on the lower half of the Ge nanowires (section I of Figure 2a). The channel length for the data of Figure 2b is 600 nm, and the nanowire diameter is 60 nm. These data exhibit linear Id-Vds, with relatively high conductivity (∼10-4 S), which can be only slightly modulated by applying a gate bias. These data demonstrate that the nanowire is sufficiently highly doped such that the metal contacts revert to being transparent tunneling barriers, hence the linear Id-Vds characteristics and the high conductivities.10 The transfer characteristics of the same device shown in the inset of Figure 2b show a positive transconductance, which is consistent with an n-type, P-doped Ge nanowire FET body. The transconductance for Vgs > 0 V extracted from the data of Figure 2b is dId/dVgs ) 1.9 × 10-7 µS at Vds ) 0.1 V, which corresponds to a electron mobility of µn ) 95 cm2/(V s).12 The relatively high doping level does not allow for full depletion and inversion in these devices, as shown by the data of Figure 2b. We can readily explain this behavior if we picture our nanowire device as a cylinder lying on a flat substrate, which is composed of two regions: a lower portion of the wire lying closest to the dielectric substrate and which is affected by the gate-source bias and an upper portion of the wire which lies farther from the substrate and which is impacted less by the gate. Being electrically doped, the latter is highly conductive independent of gate-source bias and does not allow for a full turn off of our n-type devices.13 We further note that we consistently find that devices placed near the base of the wire exhibit device characteristics similar to those of Figure 2b, demonstrating that the nanowire 2072
base is indeed n-doped. Additionally, our data also imply that the p-type, B-doped Ge shell which caps the entire nanowire structure is sufficiently thin so that it becomes fully depleted and preserves the n-type character of the nanowire base. On the other hand the devices located near the nanowire’s tip, section III (blue) of Figure 2a, exhibit device characteristics which, as we discuss below, are consistent with a p-type, lightly doped channel body. The main panel of Figure 2c shows an example of the output characteristics for a device channel length of 600 nm and nanowire diameter of 40 nm. The drain current is higher as the gate-source bias becomes more negative and the device turns off at Vgs = 0 V. The subthreshold characteristics shown in the inset of Figure 2c display a negative transconductance which is consistent with a p-FET. The measured transconductance for the data of Figure 2c for Vgs < 0 V is dId/dVgs ) 1.6 × 10-7 µS at Vds ) -0.1 V. This value corresponds to a hole carrier mobility µp ) 100 cm2/(V s).12 The devices can be inverted at sufficiently high Vgs bias (∼4 V), and the drain current starts to increase again as a result of electron transport along the channel. The hole injection current level at Vgs ) -4 V is two or more orders of magnitude larger than the electron current injection at Vgs ) 4 V (Figure 2c), evincing a predominantly hole conducting channel. The equivalence between the core/shell structure of these devices and a regular p-FET can be understood if we resort again to decomposing the nanowire device in two portions. The first portion lies closer to the substrate and its electrical properties are impacted by the gate bias, while the second lies farther from the substrate and responds to a lesser extent to Vgs. In this picture, applying a more negative Vgs induces a larger hole carrier density in the first portion, thanks in part to the existence of a B-doped shell around the device. Moreover, the B-doped Ge shell also increases the band bending at the Schottky barrier (SB) between the Ni contacts and the Ge valence band, thereby increasing the tunneling probability of hole carriers through the SB which results in an enhanced Nano Lett., Vol. 6, No. 9, 2006
hole injection from contacts.14 This conclusion is further corroborated by comparing our undoped Ge nanowire device characteristics with those of Ge nanowires composed of an undoped core and a B-doped Ge shell. Indeed, devices with similar diameters and channel lengths fabricated on core/ shell nanowire structures show a larger, positive threshold voltage15 for the p channel, as well a higher hole injection current than devices fabricated on undoped Ge nanowires. Last, we add that the electrical characteristics measured on different devices, either n- or p-type, are in good quantitative agreement for similar channel lengths and nanowire diameters. Most interestingly, when the metal contacts are placed on sections with opposite doping type, section II (orange) of Figure 2a, we observe a strong transport asymmetry when the drain-source bias polarity is reversed, consistent with a p-n junction located between these terminals. Figure 3a shows a comparison between the transfer characteristics measured for all three device types (n-type, p-type, p-n junction), recorded at both negative and positive sourcedrain bias.16 The data for the n-type (star symbols) and p-type devices are consistent with that of Figure 2b,c. Changing the Vds polarity, from 0.5 to -0.5 V, results in no Id change for the n-type device and less than a factor 2 for the p-type device.17 We have further checked that physically swapping the source and drain results in very similar data for the n-type and p-type devices. While the n-type and p-type devices show little dependence on the source-drain bias polarity, the p-n junction device shows significantly (2 orders of magnitude) larger current when the drain-source bias is positive. The output characteristics of the p-n device shown in Figure 3b, clearly exhibit rectifying I-V behavior, namely, the device conducts when the drain (p-type contact) is biased positive with respect to the source (n-type contact). As we will argue in the following, this behavior is a clear indication of a p-n junction formed between the two electrodes used for this particular measurement. Clearly, the established modulation doping along the growth direction18 which allows the realization of ultrahigh mobility two-dimensional carrier systems is not possible in our Ge nanowire one-dimensional growth. For example, if we introduced B2H6 along with GeH4 in the growth ambient during the growth of the second segment of our device, the whole structure would be capped in a thick B-doped Ge shell and its electrical properties would be those of a p-type FET along its entire length. The relatively thin, B-doped Ge shell which caps the nanowire structure preserves the n-type doping character on the first segment but renders the second, upper segment lightly p-doped. A likely explanation for this behavior is the p-doped Ge shell becomes fully depleted on the lower half of the wire19 but enhances the hole transport, albeit gate dependent, on the upper half of the wire. In a wrap around gate geometry, the ensuing device can be pictured as an annular junction between the n-type core of the lower half and the p-doped shell of the upper half of the wire (inset of Figure 1a). In our device geometry, the holes will be confined closer to the back gate and the junction is somewhat skewed toward the substrate. Nano Lett., Vol. 6, No. 9, 2006
Figure 4. Schematic representation of the energy band profile along the Ge nanowire device in the p-n junction area, as a function of Vgs, for reverse (a) and forward (b) drain-source bias. The left and right terminals represent the source and drain, respectively.
For Vgs < 0 V the output characteristics of our nanowire p-n junction devices can be fitted well with an ideal diode model, Ids ) I0(eeVds/nkT - 1), with an ideality factor n ) 2. An example is shown in Figure 3b. The ideality factor n ) 2, a common thread in all our measured devices, suggests that the forward bias is dominated by recombination.20 For Vgs < 0 V the reverse current depends more strongly on Vds and the output characteristics depart from the ideal diode model. Although a quantitative modeling of our devices is beyond the scope of this study, in the following we show that by considering the impact of the back gate on the electrostatics in our nanowire devices we can qualitatively account for the observed device behavior. We simplify the problem by considering the band modulation only along the wire’s length and neglecting the radial modulation. Figure 4a illustrates the band bending situation under reverse bias conditions, i.e., for negative Vds values applied to the p-doped section of the wire. Under these conditions there are two possible paths that allow for current flow. Electrons can be injected from the drain (the right side of the band structure) into the conduction band while holes can propagate from the left to the right through the valence band. Both of these paths are affected by the gate field. For simplicity, we assume in our discussion a symmetric line-up of the Fermi levels in source and drain relative to the conduction and valence and similar doping levels for the p- and n-doped nanowire region. In this case, at a gate voltage of zero both current paths are blocked. Note that this situation corresponds to a Vgs of around +2 V in the experiment since the absolute gate 2073
voltage value is impacted by the work functions of both the wire and the substrate in addition to possible parasitic effects. Making the gate voltage more positive allows for a substantial change in the electron current from the drain. The thermally injected current increases exponentially for a near linear movement of the bands with the gate voltage. On the other hand, there is little change of the already small current from the source side due to holes. For negative gate voltages the situation mirrors. Now it is the hole current that exponentially increases with gate-source bias. The situation is substantially different for the forward bias conditions as shown in Figure 4b. For zero gate voltage, current can be easily injected from the source and the drain side. Note, that now electrons are injected from the source and holes from the drain. The positive drain voltage ensures that both paths allow for current flow. Changing the gate voltage under forward conditions does not change this picture dramatically. For positive gate voltage conditions, e.g., some of the hole current gets blocked while the electron current increases. If we assume that the two contributions are of similar magnitude, even a complete suppression of one of the two paths without a change of the other one would not change the current by more than a factor of 2. The same is true for negative gate voltages. Note that if we picture our device as a cylinder lying on a flat substrate, then the above picture applies most accurately to the portion of the wire closest to the dielectric substrate for which the gating is strongest. As we move farther from the substrate, the back gate bias will affect the energy band profile along the wire to a lesser extent. In this case, the energy band picture which best describes the portion of the wire farthest from the gate is that of Vgs ) 0 V of Figure 4. This section will contribute a constant, independent of Vgs high current at positive Vds and a low off-current at negative Vds. In summary, using a novel device design we demonstrate here a linear Ge nanowire p-n junction. Our device characteristics provide clear evidence of a p-n junction created between two adjacent electrodes within our nanowire. Furthermore, using a multifinger device design, we identify the approximate location of the junction to within 500 nm. Acknowledgment. The authors thank J. Ott and J. O. Chu for technical assistance. This work was supported in part by DARPA/SPAWAR Contract No. N66001-05-C-8043. References (1) Wagner, R. S.; Ellis, W. C. Appl. Phys. Lett. 1964, 4, 89.
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(2) Cui, Y.; Lieber, C. M. Science 2001, 291, 851. Sunkara, M. K.; Sharma, S.; Miranda, R.; Lian, G.; Dickey, E. C. Appl. Phys. Lett. 2001, 79, 1546. (3) M. T. Bjo¨rk, Ohlsson, B. J.; Sass, T.; Persson, A. I.; Thelander, C.; Magnusson, M. H.; Deppert, K.; Wallenberg, L. R.; Samuelson, L. Appl. Phys. Lett. 2002, 80, 1058. (4) Gudiksen, M. S.; Lauhon, L. J.; Wang, J.; Smith, D. C.; Lieber, C. M. Nature 2002, 415, 617. (5) Wu, Y.; Fan, R.; Yang, P. Nano Lett. 2002, 2, 83. (6) A recent study indicates that the dopant incorporation through the nanowire surface can be suppressed for certain growth condition in the case of Si nanowires, see: Yang, C.; Zhong, Z.; Lieber, C. M. Science 2005, 310, 1304. (7) Hall, L. H.; Koliwad, K. M. J. Electrochem. Soc. 1973, 120, 1438. Rai-Choudhury, P.; Hower, P. L. J. Electrochem. Soc. 1973, 120, 1761. (8) Tutuc, E.; Guha, S.; Chu, J. O. Appl. Phys. Lett. 2006, 88, 043113. (9) The growth of the B-doped shell relies on the B-induced Ge conformal growth at low temperatures.8 A measurement of the shell thickness on our nanowires is a difficult task and beyond the scope of this study. We note however that a marker Si substrate without Au catalyst placed in the vicinity of the nanowire substrate showed a 15 nm planar growth during the growth of the B-doped shell. It is unclear if the conformal growth on the nanowires resulted in exactly the same thickness. (10) Assuming a uniformly doped nanowire and bulk mobilities (ref 11), the conductivities extracted from Figure 2b data correspond to an doping level of 2 × 1018 cm-3. (11) Cuttriss, D. B. Bell Syst. Tech. J. 1961, 40, 509. (12) If we neglect the contact resistance, the following relation holds: dId/dVds ) µCVds/L2, where C is the wire-gate capacitance and L is the channel length. The capacitance values we used in order to extract the mobilities were numerically calculated for our device geometry. (13) The spatial extent of the first, “gated” portion of the wire depends on the doping level. For a higher doping level, the gated portion will have a smaller thickness and vice versa. (14) Knoch, J.; et al. Appl. Phys. Lett. 2005, 87, 263505. (15) For a p-FET, the threshold gate voltage (VT) is defined as the Vgs value at which the Id vs Vgs changes the functional form: for Vgs < VT, Id vs Vgs is polynomial, while for Vgs > VT, Id vs Vgs is an exponential. (16) We recorded the transfer characteristics at Vds ) (0.5 V for the p-type and p-n junction devices here and at Vds ) (0.1 V for the n-type device in order to avoid Joule heating in these higher conductivity devices. Since the n-type devices exhibit linear Id-Vds characteristics the Id vs Vgs data were multiplied by a factor 5 in Figure 3a for a meaningful comparison with the other traces. (17) The change of Id at opposite Vds polarities is consistent with that of a p-FET: at negative Vds, Id approaches saturation and thus has lower values that at positive Vds. (18) Stormer, H. ReV. Mod. Phys. 1999, 71, 875. (19) We have further verified this explanation by varying the thickness of the B-doped Ge shell. For example, if we double the shell growth time its thickness will be sufficiently large so that the whole wire will have p-type character. (20) See, e.g.: Sze, S. Physics of Semiconductor DeVices; Wiley: New York, 1981.
NL061338F
Nano Lett., Vol. 6, No. 9, 2006
