Letter pubs.acs.org/NanoLett
Reconfigurable Silicon Nanowire Transistors André Heinzig,† Stefan Slesazeck,† Franz Kreupl,‡ Thomas Mikolajick,†,§ and Walter M. Weber*,† †
Namlab gGmbH, Nöthnitzer Str. 64, 01187 Dresden , Germany Technische Universität München, Department of Hybrid Electronic Systems, Arcisstrasse 21, 80333 Munich, Germany § Technische Universität Dresden, Chair for Nanoelectric Materials, Helmholtzstraße 10, D-01069 Dresden, Germany ‡
S Supporting Information *
ABSTRACT: Over the past 30 years electronic applications have been dominated by complementary metal oxide semiconductor (CMOS) devices. These combine p- and n-type field effect transistors (FETs) to reduce static power consumption. However, CMOS transistors are limited to static electrical functions, i.e., electrical characteristics that cannot be changed. Here we present the concept and a demonstrator of a universal transistor that can be reversely configured as p-FET or n-FET simply by the application of an electric signal. This concept is enabled by employing an axial nanowire heterostructure (metal/intrinsic-silicon/metal) with independent gating of the Schottky junctions. In contrast to conventional FETs, charge carrier polarity and concentration are determined by selective and sensitive control of charge carrier injections at each Schottky junction, explicitly avoiding the use of dopants as shown by measurements and calculations. Besides the additional functionality, the fabricated nanoscale devices exhibit enhanced electrical characteristics, e.g., record on/off ratio of up to 1 × 109 for Schottky transistors. This novel nanotransistor technology makes way for a simple and compact hardware platform that can be flexibly reconfigured during operation to perform different logic computations yielding unprecedented circuit design flexibility. KEYWORDS: Silicon nanowire, reconfigurable transistor, RFET, universal transistor, reprogrammable logic, Schottky barrier FET
T
without modifications to the data path could extend the boolean functionality of the common complementary metal oxide semiconductor (CMOS) technology with high efficiency. In this paper, we show a fine grain reconfigurable technology based on universal FETs built from silicon NWs, which can be programmed dynamically to a p- or n-FET by applying an external select voltage. The configuration concept is based on sensitive control of the charge carrier transport over nanoscale metal semiconductor junctions and has the unique advantage of not relying on doping. In contrast to typically ambipolar operating Schottky barrier field effect transistors (SBFETs), our reconfigurable transistors (RFETs) can be implemented in complementary logic. Abrupt metal semiconductor contacts along silicon NWs are used to create SBFETs.5 The NW geometry yields an ideal electrostatic coupling to the Schottky junction.6 We show that the electronic transport across the junctions can be effectively tuned with high sensitivity by applying external electric fields. Devices which can be configured to operate as p- or n-FETs have then been created by addressing the Schottky junctions in a SBFET individually. While one junction can be used to block one carrier type, the other junction is tuned to alter its conductance to the other carrier type.
he capability to configure electronics for customized functions after manufacturing is provided by reprogrammable circuits. Two different strategies can be distinguished to perform reconfigurability of logic functions. One embodiment, called the coarse grain method, is to route information pathways to the desired static devices or functional units. This has been implemented in field programmable gate array (FPGA) circuitry since 1984. Significant advancement has been reported on nanometer scale circuits by C. M. Lieber and A. DeHon, where reprogrammable nanowire (NW) FPGA matrices have been studied.1,2 Recently, the Lieber group developed an innovative NW-based approach that enables programmable circuits for nanoprocessors,3 showing the potential of programmable circuits. In contrast to coarse grain, the fine grain approach represents the reconfiguration of the logic function at each building block. Its implementation holds the promise for an even more compact and flexible circuit design. Up to date, the most prominent example of a fine grain reconfigurable device is the memristor.4 However, since the memristor is a nonvolatile two terminal device, it is reconfigurable only via its data line and not by a distinct configuration line. A voltage pulse is required to preprogram its electrical behavior prior to the employment of the envisioned logic function. This sequence is time and energy consuming and raises the need for additional functionality to be included in the data path. In contrast, a device which can change its electric behavior dynamically during operation © 2011 American Chemical Society
Received: September 6, 2011 Revised: November 17, 2011 Published: November 23, 2011 119
dx.doi.org/10.1021/nl203094h | Nano Lett. 2012, 12, 119−124
Nano Letters
Letter
Our reprogrammable NW device is illustrated schematically in Figure 1. The transistor core is a metal−semiconductor−
Figure 1. Schematic of a reconfigurable silicon NW FET. NiSi2 NW segments form source and drain Schottky junctions with Si. Gates 1 and 2 couple electrostatically with each Schottky junction independently from each other. One gate is used to program the por n-polarity, whereas the other one tunes the conductance through the NW.
Figure 2. Nanowire heterostructure formation and SEM image of a reconfigurable NW FET. (a) Schematic of axial Ni silicidation within the SiO2 shell. (b) SEM of the formed interfaces of NiSi2, Si, and SiO2. (c) SEM of NW FET prior to gate electrode patterning. The red arrows indicate the location of the Schottky junctions. (d) Nanowire FET with top gate electrodes, gates 1 and 2, overlapping the Schottky junctions. The scale bar is 20 nm in (b) and 200 nm in (c,d).
metal heterostructure along the length of a NW. Such axial NW configurations have been studied previously as the active components in field effect transistors5,7−10 and Coulomb blockade devices.11 The heterostructure materials of choice were NiSi2/intrinsic−Si/NiSi2 in an axial arrangement. These were all embedded in a SiO2 shell. With thermally grown SiO2 as a gate dielectric, silicon exhibits comparatively low interface trap densities,12 which is an important performance requirement for field effect devices. Moreover, the formation of metal silicon alloys, i.e., transition-metal silicides, has been extensively studied over the past decades.13 The motivation for using NiSi2 as source drain metal electrodes is two-fold. First, abrupt heterojunctions to Si can be formed within the NW, exhibiting a sharpness up to the atomic level.7,14 Second, NiSi2 Fermi level aligns near the intrinsic Fermi level of Si.15 Upon formation of the NiSi2/Si junction, a potential barrier, i.e., a Schottky barrier, arises for both electron and hole injection across the contact (0.66 eV for electrons, 0.46 eV for holes).16 The two Schottky junctions at both ends of the NW are the key elements that enable reconfigurability of our devices. In turn, the NW heterostructure geometry is beneficial to improve the gate control of the active region as the field of the gate is enhanced at the metal tip end, exactly where the Schottky junction is located. In contrast to conventional NW FETs, separate gates are located at the two Schottky junctions. They are designated to select p- or n-FET configuration with the program gate, gate 2, and to steer the injection with the control gate, gate 1 (Figures 1 and 2d). For fabrication of the NW heterostructures, vapor−liquid− solid (VLS) grown intrinsic silicon NWs with 25−37 nm diameter and ⟨112⟩ crystal direction were employed. The NWs were dispersed on SiO2-coated n-silicon substrates. Thermal oxidation of the NWs was used to form a 10 nm thick SiO2 shell. At both NW ends, SiO2 is etched, and Ni reservoirs are deposited. Upon annealing, Ni diffuses axially into the SiO2coated Si NW and transforms the Si regions into metallic, single-crystalline NiSi2 NW segments (Figure 2a,b), as described in ref 5. As a result, NiSi2/intrinsic−Si/NiSi2 NW axial heterostructures surrounded by a SiO2 shell are formed. The remaining Ni reservoirs are used to connect the NiSi2 source and drain regions. The locations of the NiSi2/Si Schottky junctions are determined by scanning electron microscopy (SEM) (Figure 2c). Subsequently, individual (Ti/
Al) metal gate electrodes are patterned on top of each Schottky junction with electron beam lithography. Figure 2d shows a finalized reprogrammable transistor structure with the individually addressable top gate electrodes. The resulting device of Figure 2 has a reduced silicon core diameter of 20 nm with a length of 680 nm, surrounded by the SiO2 shell. The charge carrier transport in the fabricated nanoscaled SBFET is provided by bending the energy bands in the active region.17,18 Analyzing the dependence of carrier injection to gate location with scanning gate microscopy (SGM) indicated that the Schottky junctions and their adjacent Si regions are the most sensitive parts for carrier injection.19 Further analysis of the electrical behavior, with respect to different gating geometries, showed that saturation currents comparable to those of a single common backgate can be reached with simultaneous operation of the separate top gates in Figure 2d (more details in Supporting Information). The results imply that the ungated region does not limit conductance and that gating, just at the vicinity of the Schottky junctions, is sufficient to control the current injection of holes and electrons. Next, fine grain reconfigurable operation of our transistors, as programmed by an electrical signal, is shown. The target parameter for reconfiguration is FET polarity, i.e., switching from p- to n-FET behavior. After considering various independent top gate combinations, the most straightforward approach was determined to be when one Schottky junction is altered to block the undesired charge carrier type, while the other junction controls the injection of the desired carriers into the active region. The results of the transistor depicted in Figure 2 are summarized in Figure 3. The potential of the top gate on the right-hand side, VG2, is set as the program bias, while the potential at the left-hand electrode, VG1, is used to tune device conductance. Figure 3 shows the measured electric characteristics (a,c) and the corresponding schematic band diagrams (d). In the first configuration, p-type FET behavior is programmed by setting the program gate, VG2, to −3 V and the drain source voltage, VD, to −1 V constant (Figure 3d left column). Accordingly, the VG2 potential effectively blocks electron injection at the drain electrode. The control gate, VG1, 120
dx.doi.org/10.1021/nl203094h | Nano Lett. 2012, 12, 119−124
Nano Letters
Letter
Figure 3. Electric characteristics and working principle of the RFET. (a) Measured transfer characteristic programmed as p-FET (red) and n-FET (blue). (b) Simulated transfer characteristic with indication of combined carrier tunneling and thermionic emission (1), thermionic emission (2), and off-state (3). Hole/electron transport is indicated with red/blue, and the dashed lines show the characteristics when tunneling would not occur. (c) Measured output characteristic of the p-programmed FET. (d) Corresponding band diagrams to states 1−3.
is swept between positive and negative values. For VG1 < 0, the upward band bending stimulates hole injection into the active region at the source side. Sweeping VG1 to positive values blocks the injection of holes, shutting off the FET. The resulting subthreshold transfer characteristic resembles typical p-FET behavior (Figure 3a, red curve). Next, n-type behavior was programmed by switching the polarity of the program gate to VG2 = +3 V and the drain bias to VD = +1 V (Figure 3d), i.e., by applying the inverse electrostatic configuration to the p-type case. In this case the potential VG2 blocks the injection of holes from the drain electrode into the active region but makes the junction transparent for electrons. At VG1 < 0, electron injection is quenched at the source electrode by the high-energy barrier. Increasing VG1 to positive values lowers the bands at the source electrode, enhancing electron injection. The I−V curve indeed resembles an n-type FET (Figure 3a, blue curve). In synthesis, the polarity of the same FETs can be selected by simply applying a program potential at one top gate electrode. P- and n-type execution can be configured for the same device. This implies that static p- and n-type FETs in a circuit could be replaced by reconfigurable transistors. In principle, they can enable any boolean logic function in a complementary design. Thus, they are universal FETs for logic applications. Furthermore, the potential to change the configuration of each transistor within the circuit enables the reconfiguration of this circuit in a fine grain manner. Specific logic functions can be dynamically altered during operation. Consequently, the main advantage of the concept is that additional logic functions
can be provided with the same number of transistors compared to standard CMOS logic. Note that the devices are entirely bidirectional: Equivalent results are obtained by swapping the signals between source/ drain and VG1/VG2. This symmetry is another clear advantage for flexible and adaptive circuit design. The transfer characteristic of the p- and n-programmed device is plotted in backward and forward sweeping mode. The device shows insignificant hysteresis. This can be attributed to the low density of interface traps due to the passivated and near ideal interface of Si and thermal SiO2. The total modulation for the p-FET (n-FET) configuration is 1 × 109 (6 × 107) within a VG1 range of 3 V. These values can be even higher as the offstate currents are at our detection limit of 4 × 10−15 A. The maxima on currents are −1.9 μA (94 μA μm−1) and 1.1 × 10−7 A (5.3 μA μm−1) for p- and n-FET programming, which give maximum current densities, JDmax, of 600 and 34 kA cm−2, respectively. The scaled peak trans-conductance amounts to 6 mS μm−1 (p-program FET) and 7.5 nS μm−1 (n-program FET). The inverse subthreshold slope, S, characterizing the steepness of switching reaches values as low as 90 mV dec −1 for the p-programmed mode. For the n-programmed mode, the lowest measured S is 220 mV dec−1. It is higher than the pprogrammed mode, since it could only be determined in an injection state where tunneling dominates (Figure 3b,d, state 1), as is illustrated below. To further elucidate the charge transport and to corroborate the reprogrammable FET device behavior, the measured electrical response has been compared with theoretical models. 121
dx.doi.org/10.1021/nl203094h | Nano Lett. 2012, 12, 119−124
Nano Letters
Letter
Figure 4. Selective charge distribution in different operation states. (a,d) Hole/electron domination in the p-/n-programmed on-states, with nearsurface charge accumulation in the gated region. (b,d) Selective charge separation in the off-states. Black lines indicate the top gate electrode locations. (e) Simulated band structure in the NW center along the x-axis for the p-programmed off-state 3 (c) showing induced virtual bandgap widening.
Finite element calculations were carried out with Sentaurus Device 3D simulator. These consider drift diffusion transport within the Si region and thermionic emission and quantum mechanical tunneling [Wentzel Kramers Brillouin (WKB) approximation] at the junctions.20 Indeed, the calculated device characteristics mimic the measured behavior with high accuracy. The subthreshold regime of the p- and n-program curves is divided into a steeper (Figure 3b, state 2) and a flatter region (Figure 3b, state 1). Simulations confirm that the former is governed by thermionic emission of charge carriers over the energy barrier, whereas the latter is dictated by tunneling through the thinned regions of the Schottky barrier.18 The dashed line in Figure 3b shows a synthetic characteristic when Schottky barrier tunneling would not occur. The drive current for both p- and n-operation is significantly dominated by tunneling. Furthermore, the simulations suggest that the source to drain leakage currents in both off-states are limited by our measurement resolution. The dominant contribution of tunneling carriers to the oncurrent is contrary to conventional FETs with low doping concentrations. It is a result of the small scale NW device geometry of the reconfigurable FET. Both the downscaling of the NW diameter and the enhancement of the dielectric properties are expected to contribute to the reduction of the barrier width for tunneling when applying the same biases. This leads to a lower Schottky junction resistance, as shown in studies of diodes and SBFETs.21,22 In complementary circuits, the off-state currents contribute largely to the overall energy consumption. Single-gated SBFETs exhibit a significant off-state current, since band bending is directed to either positive or negative potentials. Increasing the effective energy barrier for holes leads to decreasing the barrier for electrons,23 with the off-state given by the trade-off between electron and hole injection. This is the case when band bending does not occur, nominally at VG = 0 V. Depending on the bandgap of the semiconductor and electrode material, thermally activated charge carriers can, even when in the off-state, be injected into the active region at room temperature. Concepts have been presented to reduce the off-currents by an additional barrier in the active region with a middle top gate of a SBFET.24 The off-current suppression of the reconfigurable transistor is distinctively different and more effective. The independent gating enables an opposite band bending at the Schottky contacts. Hence, a virtual band gap widening for
thermally activated charge carriers can be effected (Figure 4e). Electrons and holes are locally separated at different junctions in the off-state, preventing injection into the ungated region between the electrodes. This leads to an unpopulation of charge carriers between the gates, as seen in Figure 4b,c (depicted in green). This state is unfeasible in both conventional transistors and previous SBFET approaches. The concept of selective blocking of electrons and holes at the vicinity of the source and drain electrodes enables a negligible off-current below 4 × 10−15 A. The enhanced gate voltage sensitivity for the present device structure is attributed to the small size and geometry of the Schottky contacts. The axial metal-semiconductor NW heterostructure used here is the most ideal geometry for electrostatic coupling of an electric field to a Schottky contact.6,25 The highest electric field gradient takes place at the conducting tip, i.e., exactly at the location of the Schottky junction.5 For a practical implementation of the transistors in complementary logic circuits, symmetric transfer characteristics are desirable, i.e., similar on-currents, and comparable subthreshold slopes and absolute values of the threshold voltages for p- and n-program FETs. In silicon CMOS technology, the lower mobility of holes compared to electrons is compensated by a larger channel width of the p-FETs. In the case of the reconfigurable NW FET, the same size of the active region can in principle be used since the lower mobility of holes within the active region can be compensated by a lower Schottky barrier height for holes than for electrons. Thus, the on-current ratio between the p- and n-FETs can in principle be adjusted by optimizing the tunneling ratio to the valence and conduction bands, as supported by our simulations. The working principle of transistor reconfiguration is not only applicable to bottom-up synthesized NW structures. The concept can be transferred to state-of-the-art CMOS technology processes to enable large-scale integration. Several implementation scenarios are conceivable. The geometry of the active region can be an ultrathin body silicon-on-insulator (SOI) layer, an etched fin, or a top-down processed NW. The material requirements for reconfigurability are abrupt and homogeneous Schottky junctions between an intrinsic semiconductor and a corresponding metal with midgap work function. Sufficient electrostatic control to each Schottky junction has to be provided by the individual gate stacks. 122
dx.doi.org/10.1021/nl203094h | Nano Lett. 2012, 12, 119−124
Nano Letters
Letter
operate as p- or n-FET as programmed by an electric signal. The concept has been realized by utilizing an arrangement consisting of an axial NiSi2−Si−NiSi2 NW heterostructure embedded in a SiO2 shell. The underlying mechanism is the independent control of the charge carrier injection through each Schottky junction by two separate top gate electrodes. The working principle is illustrated by electrical measurements and supported by device simulations. The devices exhibit an efficient tuning of conductance up to record values of 1 × 109. It was found that the opposite band bending at source and drain effectively quenches source drain leakage currents in the off-state. This finding makes the use of alternative lower band gap semiconductors applicable as high leakage currents have been a major hurdle for their implementation in microelectronics. An inherent and unique advantage of this device concept is that no doping is required to realize p- and n-type FETs, leading to a leaner technological complexity. Consequently, any logic function can be computed by the interconnection of such transistors. In addition, the circuit function could be dynamically altered to match the user's demands during operation, i.e., allowing fine grain circuit reconfiguration. This approach can be exploited to enable different subsequent computing operations with the same hardware, increasing the computing power of the system and giving the prospects of compact circuit design.
Electrostatic gate coupling is enhanced by scaling down the junction area,21 employing high k dielectrics and a surround gate architecture.26 In addition to the volatile configuration of our devices, a nonvolatile configuration is conceivable. The introduction of a trapping material or floating gate close to the Schottky junctions could retain programmed p- or nconfigurations. Although nonvolatile programming excludes the application of a continuous program voltage, in principle it reduces the speed of reprogramming. The reconfigurable transistor concept is especially promising for the implementation of low band gap semiconductor materials. The often reported high junction leakage in conventional FETs for Ge27 (work function = 0.66 eV) and InAs (work function = 0.35 eV) can be suppressed effectively by the virtual bandgap widening effect introduced above. This, combined with inherent high electron and hole mobility for the active region, could result in enhanced electrical characteristics. Figure 5 shows the simulated transfer characteristic of a
■
ASSOCIATED CONTENT S Supporting Information * Details of methods for fabrication and electrical characterization. This material is available free of charge via the Internet at http://pubs.acs.org.
■
AUTHOR INFORMATION Corresponding Author *E-mail:
[email protected].
Figure 5. Prospects for reconfigurable NW devices. Simulated transfer characteristics for low bandgap material (0.66 eV) to midgap metal (4.4 eV). These work functions correspond to a Ge−NiGe Schottky junction. The device shows enhanced on-currents and symmetric transfer characteristics.
■
ACKNOWLEDGMENTS This work was partially funded by the EU (NODE: IST015783). The authors thank D. Grimm and D. Pohl from the Leibnitz Institute for Solid State and Materials Research Dresden for their help regarding EBL and TEM.
reconfigurable transistor, based on material work functions equal to a Ge−NiGe heterojunction. Reconfigurability and low off-currents (
