Reliable Multi-State Data Storage with Low-Power Consumption by

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Reliable Multi-State Data Storage with Low-Power Consumption by Selective Oxidation of Pyramid-Structured Resistive Memory Youngjin Kim, Hanhyeong Choi, Hyun S Park, Moon Sung Kang, Keun-Young Shin, Sang-Soo Lee, and Jong Hyuk Park ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b10188 • Publication Date (Web): 16 Oct 2017 Downloaded from http://pubs.acs.org on October 21, 2017

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ACS Applied Materials & Interfaces

Reliable Multi-State Data Storage with Low-Power Consumption by Selective Oxidation of PyramidStructured Resistive Memory Youngjin Kim,†,‡ Hanhyeong Choi,‡,⊥ Hyun S. Park,∬ Moon Sung Kang,# Keun-Young Shin,*,§ Sang-Soo Lee,*,†,‡ and Jong Hyuk Park*,‡

†

KU-KIST Graduate School of Converging Science and Technology, Korea University,

Seoul, 02841, Korea ‡

Photo-Electronic Hybrids Research Center, Korea Institute of Science and Technology,

Seoul, 02792, Korea ⊥

School of Chemical and Biological Engineering, Seoul National University, Seoul 08826,

Korea ∬Fuel

Cell Research Center, Korea Institute of Science and Technology, Seoul, 02792, Korea

#

Department of Chemical Engineering, Soongsil University, Seoul, 06978, Korea

§

Department of Materials Science and Engineering, Hallym University, 24252, Korea

*E-mail: (J.H.P.) [email protected], (S.-S.L.) [email protected], and (K.-Y.S.) [email protected] KEYWORDS: multilevel resistive memory, pyramidal electrode, tip-enhanced electric field, surface energy, conductive filament, resistive switching

1 ACS Paragon Plus Environment


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ABSTRACT Multilevel data storage using resistive random access memory (RRAM) has attracted significant attention for addressing the challenges associated with the rapid advances in information technologies. However, it is still difficult to secure reliable multilevel resistive switching of RRAM due to the stochastic and multiple formation of conductive filaments (CFs). Herein, we demonstrate that a single CF, derived from selective oxidation by a structured Cu active electrode, can solve the reliability issue. High-quality pyramidal Cu electrodes with a sharp tip are prepared via the template-stripping method. Morphologydependent surface energy facilitates the oxidation of Cu atoms at the tip rather than in other regions, and the tip-enhanced electric fields can accelerate the transport of the generated Cu ions. As a result, CF growth occurs mainly at the tip of the pyramidal electrode, which is confirmed by high-resolution electron microscopy and elemental analysis. The RRAM exhibits highly uniform and low forming voltages (the average forming voltage and its standard deviation for 20 pyramid-based RRAMs are 0.645 V and 0.072 V, respectively). Moreover, all multilevel resistance states for the RRAMs are clearly distinguished and show narrow distributions within one order of magnitude, leading to reliable cell-to-cell performance for MLC operation.


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1. INTRODUCTION Resistive random access memory (RRAM) is a device that modulates the resistance states through electrical stimulation for data storage.1 RRAM has great potential as a nextgeneration nonvolatile memory device to replace NAND flash memory.2-4 Among the RRAM devices reported to date, RRAM based on electrochemical metallization (ECM) in the active electrodes has attracted great interest due to its low cost, fast switching speed, low-power consumption, excellent scalability, and various switching materials.5-10 Increasing the data storage density of RRAM is essential for information processing and for addressing the challenges associated with the rapid advances in information technologies.11 The multilevel cell (MLC) technique is a promising method that allows storage of multiple bits on a single cell using multi resistance states.12-13 The key issue for MLC operation in RRAM is to separate each resistance state without overlap.12, 14-16 It has been difficult for conventional RRAM devices with a planar shape to ensure reliable MLC operation due to the large fluctuations of the resistance value arising from the stochastic and multiple formation of conductive filaments (CFs) in a single cell.12,

14, 17

Moreover, repeated operation of the

devices may result in fusion between the CFs, further deteriorating their MLC properties.17-22 A number of techniques have been studied to overcome problems with non-controlled CFs, including impurity doping,23-24 introduction of an interfacial layer,25-27 incorporation of an additional insulating structure,27-28 and insertion of metal nanoparticles.29 Despite some progress being acheived by these approaches, a large number of CFs are still formed in the insulating medium of the RRAM. It is because the oxidation process can occur simultaneously over the entire area of the active electrode. Therefore, it is necessary to develop a strategy for controlling the oxidation process of the active metal in a confined area, ideally forming a single isolated CF in one memory cell. Recently, we have reported that a pyramid-shaped Ag electrode is effective to control CF formation in RRAM via manipulation of electric fields.30 In the ECM mechanism, the oxidation of Cu is thermodynamically more favorable than Ag because the standard redox potential of Cu is lower than that of Ag.31 In addition, a sharp tip with a relatively small tip radius can be easily obtained with Cu because the grain size of Cu is smaller than that of Ag.32 Therefore, the exploitation of Cu pyramidal electrodes for RRAM will be beneficial in



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achieving selective oxidation of the active electrodes and controlling CF formation in the device. Herein, we introduce pyramidal electrodes into RRAM to enable the selective oxidation of the active metal and control the formation of CFs. Pyramidal Cu active electrodes with a high-quality tip were prepared by the template-stripping method. The high surface energy and enhanced electric field at the pyramid tip allow the selective oxidation of Cu atoms at the tip, resulting in the controllable formation of CFs. The resulting RRAM device exhibited highly uniform MLC operation with reliable/low forming voltages and narrow cell-to-cell variation.

2. EXPERIMENTAL DETAILS Details of the fabrication and characterization methods are provided in the Supporting Information (Figure S1 and S2). 2.1. Preparation of Si templates The templates were fabricated with photolithographic techniques using a 100-nm-thick SiN layer/Si(100) wafer. Positive photoresist (PR) (GXR601; AZ Electronic Materials) were spincoated onto the pre-cleaned templates, and then exposed under an ultraviolet lamp using chrome-on-glass masks and a mask aligner (MA6; Karl Suss). The PR on the exposed areas was eliminated using a developing solution (AZ 325; AZ Electronic Materials). Then, the hole array patterns were developed on the PR layer. The hole patterns were transferred to the SiN layer by reactive-ion etching (RIE) (RIE 80 Plus; Oxford Instruments) with CF4 and O2 gases. The templates with inverted pyramid structures were prepared via an anisotropic etching process using 30% potassium hydroxide (KOH) solution at 60 °C for 10 min. Finally, the SiN layer was removed in a hydrofluoric acid solution, and the resulting templates were cleaned in a piranha solution.

2.2. Fabrication of Cu pyramid-based memory devices The fabrication procedure for the Cu pyramid-based memory devices is described in Figure S1 in the Supporting Information. A 140-nm-thick Cu layer was deposited on the Si template using a thermal evaporator (KVE-T4004L; Korea Vacuum Technology). The deposition rate was approximately 0.1 nm/s under a pressure of about 10-6 Torr. Thermally curable epoxy 4 ACS Paragon Plus Environment

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(EPO-TEK 377; Epoxy Technologies) was applied onto the top of the patterned film, and then a glass substrate was attached to peel off the Cu structures. The epoxy was cured at 150 °C for 1 h. The Cu pyramid structure was stripped off using a razor blade. A 140-nmthick Al2O3 layer, and a 40-nm-thick Pt layer, were deposited sequentially onto the stripped Cu pyramids via radio frequency (RF) and direct current (DC) magnetron sputtering (SME200E; ULVAC), respectively. The sputtering process was operated under a power of 150 W, a pressure of 5 mTorr with Ar, and a source-to-substrate distance of 15 cm. The Pt layer was deposited using a stainless steel mask with 25-µm-diameter holes.

2.3. Preparation of specimens for observation of conductive filaments To observe the CFs in the Cu pyramid-based RRAM, the specimens were prepared using the following process. First, a 2-µm-thick Pt layer was deposited on the RRAM to protect the pyramid structure. Second, a small area around the pyramid tips (length: 7.5 µm, width: 3 µm) was cut via focused ion beam (FIB) milling (Quanta 3D FEG; FEI), and then transferred onto a Cu grid. Third, DC voltage ranging from 0 to 50 mV was applied to the specimen using a Cr tip (Figure S2a in the Supporting Information). Finally, the width of the specimen was cut to about 100 nm via FIB milling (Figure S2b in the Supporting Information), and then the CF was observed using transmission electron microscopy (TEM).

2.4. Electromagnetic finite-element simulation for pyramid structures The electric field E in the pyramid-based RRAM was solved with the COMSOL multiphysics software using the following equation: = −∇, where V is the electric potential. The following parameters were obtained from the TEM measurements. The layer thickness was 140 nm for the Cu bottom electrode, 150 nm for the Al2O3 insulating layer, and 40 nm for the Pt top electrode. The radii of curvature were 20 nm at the bottom electrode, 110 nm at the insulating layer, and 180 nm at the top electrode. The refractive index of Al2O3 was set at 1.76 (the other parameters were obtained from the COMSOL material library). The maximum size of the mesh elements for the simulations was 100 nm; a high-resolution mesh was used around sharp features. The Cu electrode was set to an electrostatic potential of 0.645 V (which is the average forming voltage for 20 cells) and the Pt electrode was grounded.



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2.5. Characterization The morphologies of the pyramid-based RRAM devices were observed using scanning electron microscopy (SEM) (JSM-6700F; JEOL). The current–voltage analysis for the memory devices was carried out under ambient conditions, using a semiconductor parameter analyzer (4155C; Hewlett-Packard) equipped with an SMU/pulse generator (81104 A; Agilent).


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3. RESULTS AND DISCUSSION Figure 1a shows an SEM image of the Cu pyramid arrays prepared by the template-stripping method. The template-stripped pyramid structures have a uniform and sharp tip with a radius of curvature of 20±2 nm. The tip radius indicates that the grain size of Cu is smaller than that of Ag, a key factor in the activity of the ECM reaction and enhancement of the electric field.31-33 The pyramid arrays had a uniform size that can provide scalability for the RRAM device. To fabricate a RRAM device, an Al2O3 layer and a Pt electrode were deposited on a Cu pyramid using a sputtering method. From the FIB and SEM analysis, it was observed that the Cu pyramid RRAM structure was fabricated successfully, and the thicknesses of the Cu, Al2O3, and Pt layers were about 140, 150, and 40 nm, respectively (Figure 1b). The radii of the Cu and Al2O3 tips were estimated at about 20 and 100 nm, respectively. The taper angle of the Cu tip was ~70.6 °, in accordance with the theoretical angle of KOH anisotropic etching for the silicon mask.34 The electroforming behaviors of the pyramid-based RRAM were observed using DC sweep analysis. The uniform forming voltage leads to reliable switching behaviors based on CF formation.17, 29-30 Figure 1c shows current-voltage (I-V) curves for the forming process of the 20 pyramid-based cells on a semi-logarithmic scale. Under a steady increase in applied positive voltage, the device remained in the high resistance state (HRS) and then abruptly switched to the low resistance state (LRS) in the low voltage range. During the DC sweep for each of the 20 pyramid-based cells, the forming voltages were confined to narrow and low ranges between 0.50–0.75 V, implying excellent reproducibility between cells and low-power consumption. Moreover, the average forming voltages and their standard deviation for the 20 pyramid-based cells were 0.645 V and 0.072 V, respectively (Figure 1d). The above results imply that a uniform CF formed in each cell. The distributions of the forming, SET, and RESET voltages of control devices containing unstructured, planar Cu electrodes were measured. Figure S3a and b in the Supporting Information show the I-V curves and the cumulative probability graph for the forming process of 20 conventional memory devices with planar electrodes. For the planar cells, the minimum compliance current (Icc) for electroforming was 0.1 mA (no forming behavior was observed at Icc less than 0.1 mA). The forming voltages of the planar devices were much higher (0.8–8.9 V) than those obtained in the pyramid-based devices (0.5–0.75 V) (Figure 1c,



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d). During the DC sweeping analysis for 50 cycles, the SET and RESET voltages of the devices with planar electrodes were widely distributed between 0.55 and 9.12 V and between -0.13 and -2.88 V, respectively (Figure S3c and d in the Supporting Information). The performance of the devices with planar electrodes cannot be directly compared to that of the devices with pyramidal electrodes due to the different Icc values. However, it can still be concluded that the memory devices with pyramidal electrodes require lower operating power and exhibit more stable switching behaviors.


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Figure 1. (a) Scanning electron microscopy (SEM) images of Cu pyramid arrays. The images were tilted 54° from normal. The inset in (a) is a high-magnification image of the tip region of the Cu pyramid. (b) Cross-sectional image for Pt/Al2O3/Cu pyramid RRAM. (c) Currentvoltage (I-V) curves for the forming process of 20 pyramid-based cells on a semi-logarithmic scale. The devices were tested under the following conditions: voltage sweep rate: 0.05 V/s, and compliance current: 0.1 µA. The area of the Pt top electrode was about 490 µm2 (diameter: 25 µm) for each cell. (d) Histograms of the forming voltage in each unit cell.



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The multilevel switching performance of RRAM devices based on a pyramid structure, such as SET and RESET voltages, was measured using DC sweep analysis. As shown in Figure 2a, when positive voltages were applied to the pyramid-based RRAM under different Icc values of 0.1, 0.5, and 1 µA during the SET process, three different LRSs could be distinguished clearly. During the resistive switching process, the RESET current increased with increasing Icc. The resistive switching behavior is attributed to the size of Cu CFs, which is directly related to the value of Icc in the CF model: the filament size gradually increases with increasing Icc during forming or SET processes.17, 35 The HRS remained at almost the same current for all three states. Therefore, the device has four well-distinguished states, i.e., one HRS and three different LRSs, implying the capacity for multi-bit storage. When multilevel switching tests were performed on 20 pyramid-based cells, three different LRSs were still distinguished without overlap (Figure S4 in the Supporting Information). Moreover, the SET and RESET voltages exhibited narrow distributions between 0.20–0.40 V and -0.20– -0.30 V, respectively. Based on the DC sweep results, electric-pulse-induced-resistance (EPIR) switching tests on three pyramid-based cells, randomly chosen from the 20 electro-formed memory cells, were conducted under SET and RESET voltage pulses of different amplitudes. Positive pulses of 0.32, 0.40 and 0.47 V, with a pulse width of 500 ns, were applied to the pyramid-based cell to switch between the three different LRSs. Moreover, a negative pulse of -0.35 V was employed with a pulse width of 500 ns to successfully obtain the HRS. As shown in Figure 2b, each resistance state of the three pyramid-based RRAMs under EPIR mode was highly stable, without overlap for 100 cycles. The write and erase energies, including the MLC states, showed ultralow power consumption of below 0.5 µW; the power consumption values are summarized in Table 1. Figure 2c shows the distribution of the resistance states, including three LRSs and one HRS, for the three pyramid-based RRAMs. For all RRAM samples, all of the resistance states were separated clearly from each other and the resistance values in each of the four resistance states had narrow distributions within one order of magnitude. The range of each resistance state is shown in Table 1. From the above results, we confirmed that filament growth controlled by the oxidation process can both ensure reliable cycle-to-cycle MLC performance and obtain cell-to-cell MLC uniformity. In general, lowering the value of Icc is an effective method for reducing power consumption.36 However, as mentioned above, the value of Icc is related to the diameter of a 10 ACS Paragon Plus Environment

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CF; thus, long retention of LRS might become a problem under low Icc values.35, 37-38 Figure 2d shows the retention properties of the pyramid-based cell for four resistance states at room temperature. The resistance values, including the one HRS and three LRSs, remained almost the same for 105 sec under the read voltages at 0.1 V. This is presumably because dense CFs were formed by the localized injection of Cu ions via the tip-enhanced electric field, as reported previously for an Ag pyramid-based RRAM device.39 These robust CFs resist selfdissolution from atomic diffusion and can maintain LRS retention with ultralow power.



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Figure 2. (a) Direct current (DC) sweeping results of pyramid-based cells according to different Icc values of 0.1, 1, and 10 µA. (b) Electric pulse-induced resistance testing was done under the following conditions: 00: -0.35 V, 01: 0.32 V, 10: 0.4 V, and 11: 0.47 V, with 500 ns pulse-width. (c) Cumulative plot of the resistance states, including three low resistance states (LRSs) and one high resistance state (HRS). (d) Retention performance for different resistance states at room temperature. During the retention test, the read voltage was 0.1 V.


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Table 1. Summary of the calculated power consumption (and range) for each resistance state of the three pyramid-based RRAM devices. Average Set Power

Average Reset Power

Minimum/Maximum value

(Watt)

(Watt)

of resistance (Ω)

01

1.94E-08

4.28E-08

1.42E+06 / 2.53E+06

10

6.67E-08

1.60E-07

5.55E+05 / 8.95E+05

11

2.43E-07

3.95E-07

1.89E+05 / 3.15E+05

RRAM devices having a pyramid structure were prepared by FIB milling to observe CF formation. Figure 3a shows a scanning transmission electron microscopy (STEM) image of the pyramid structure RRAM without any external voltage. From the line-mapping analysis, it is apparent that no Cu atoms were observed within the Al2O3 medium (Figure 3b). On the basis of the MLC results, positive DC voltages of 0.3 V and 0.5 V were applied to each active Cu electrode with respect to the Pt electrodes. Surprisingly, oxidation was observed only at the tip in both samples, and no other regions of oxidation were observed in the pyramid structure RRAM, as shown in Figure S3 in the Supporting Information. From the linemapping results in Figure 3d and f, the CF element was identified as Cu. Thus, the resistive switching behavior of the pyramid-based RRAM deviance proceeded via ECM of Cu near the tip region. Another interesting result concerns the number of Cu atoms in the line mapping results. Each CF exhibited different numbers of Cu atoms at different applied voltages. A greater number of Cu atoms were observed at an applied voltage of up to 0.5 V, which means that higher external stimulus produces denser CFs. Therefore, the multilevel switching behaviors in our structured RRAM can be understood as the growth of vertical and dense Cu CFs. These results can be interpreted according to the theory of subsequent lateral widening/retention of CFs.



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Figure 3. Scanning transmission electron microscopy (STEM) images and results of line mapping analysis of pyramid-based cells. (a) and (b) show the results obtained without external voltages. (c) and (d) show the results of applying external voltage up to 0.3 V. (e) and (f) shows the results of applying external voltage up to 0.5 V. The orange lines show the positions of line profile measurement.


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To interpret such selective CF growth near the pyramid tips, it is necessary to understand the resistive switching mechanism of the pyramid-based RRAM device. We attribute this phenomenon to the two geometrical effects arising from the pyramid structure. The first is the difference in surface energy between the tip region and the other region due to the pyramidal structure.8 The surface energy (γ) of a Cu atom according to its position can be calculated using the following equation:40-41

γ =

(1)

where Es is the energy of the surface block of the Cu atom, Eb is the energy of an equal number of Cu atoms in the bulk, and A is the surface area. The surface energy of a Cu atom is the sum of the interaction energy among all Cu atoms. Therefore, the surface energy of a Cu atom increases as the number of neighboring Cu atoms decreases. Thus, a Cu atom at the tip has a higher surface energy than a Cu atom at other sites. Figure 4 shows a schematic illustration of the forming process for Cu filaments. The Cu atom at (i) the top site has the highest surface energy because it interacts with only one other Cu atom, implying that this Cu atom is the easiest one to oxidize. The generated Cu ion migrates to the inert Pt counter electrode, and then the ion is reduced to a Cu atom. After the Cu atom at site (i) is oxidized, the atoms at edge sites (ii) and (iii), which have relatively higher surface energy compared to other regions, would be oxidized subsequently. The repetition of these processes forms a Cu filament. Consequently, the Cu filament forms exclusively and easily in the tip region.



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Figure 4. Schematic illustration of forming behaviors in the pyramid-based cell. The nucleation and growth of Cu filaments occur predominantly at the tip due to the tip-enhanced electric field as well as the high surface energy. Since the tip of the Cu pyramid is rapidly oxidized, the filament has grown widely in various directions.


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The second effect is the tip-enhanced electric fields, which induce a reduction in the activation energy barrier for the migration of Cu ions in the Al2O3 medium.42 To estimate the electric fields in the pyramid-based RRAM device, electrostatic properties were estimated using finite-element modeling in the COMSOL multi-physics software, based on the geometric parameters measured using TEM, as shown in Figure 5a. When an average forming potential of 0.645 V was applied between the Cu and Pt electrodes, the electric field near the tip region of Cu was significantly enhanced. In particular, the electric fields decreased rapidly away from the tip (Figure S6 in the Supporting Information). The electric fields near the tip with various tip angles in the pyramid-based memory devices were estimated by finite-element modeling (Figure S7 in the Supporting Information). The magnitude of the electric fields near the tip increased with decreasing the tip angle. In other words, a low angled pyramid tip can facilitate the ionization of Cu atoms at the tip, implying that the performance of the pyramid-based devices can be further improved. Figure S8 in the Supporting Information shows a simulation result for the electric fields near the tip. The arrows indicate the direction of migration of the Cu ions generated at the tip according to the gradient of the electric fields. However, the actual CF was widely grown in various directions (Figure 3). It is presumably due to the explosive oxidation of Cu atoms at the pyramid tip. When the electric potential is applied, the tip of the pyramid is rapidly oxidized due to the high surface energy and the tip-enhanced electric field. Therefore, a large number of Cu ions are instantaneously supplied near the tip, and they can be transported in various directions, alleviating the effect of the electric fields on the CF growth direction. Compared with the magnitudes of the electric field on the planar region, the electric field near the tip region was larger by 2.5 times, respectively (Figure S6 in the Supporting Information). Figure 5b shows the ion-hopping mechanism for the tip-enhanced effect in the pyramid-based memory device. The energy barrier of ion-hopping can be represented by:3, 4344

∆ = ∆ −

(2)

where ∆W and ∆ are the energy barrier with and without the electric field, a is the hopping distance, and E is the applied electric field. From equation (2), the energy barrier for ion-hopping can be lowered by enhancing the electric field. Because the electric field in the tip region of the pyramid-based RRAM is higher than those in the plane and edge of the pyramid, ion-hopping can be facilitated in the tip region. In addition, the ion-hopping current density (Jhop) can be expressed as:3, 43-44 17 ACS Paragon Plus Environment


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Jhop = 2zecaν exp −

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sinh

(3)

where c is the concentration of Cu2+ ions and ν is the frequency factor at trap sites. Figure 5c shows the double-logarithmic I-V curve. This curve exhibits an uncommon tendency compared to typical memory devices. The switching mechanism for typical RRAM devices generally involves a change from ohmic conduction to another conduction mechanism. such as

space-charge-limited-conduction

(SCLC),

Poole−Frenkel

(P-F)

emission

or

Fowler−Nordheim (F−N) tunneling.45-46 However, in our case, a slope of about ~3.23 (range: 0–0.15 V) is seen before the appearance of ohmic conduction, because of the enhanced electric field and surface energy affecting Cu oxidation and ion-hopping near the tip region.3, 43-44

After that, the current values typically changed from ohmic conduction (I ∝ V1.1) to

Child’s square law conduction (I ∝ V2.27), i.e., the SCLC mechanism. Consequently, the Cu filament is developed only at the tip region of the pyramids and the forming voltages in the pyramid-based cell are fixed within a uniform range because of the high surface energy and enhanced electric field. This leads to highly uniform cell-to-cell MLC performance.


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Figure 5. (a) Simulation results of the electric fields near the tip region of the pyramid-based RRAM device under an electric potential of 0.645 V, which was obtained using COMSOL multi-physics software. (b) Schematic diagram of the Cu ion-hopping mechanism. Top: without externally applied potential, middle: with application of electric potential, and bottom: according to the electric field enhancement via the Cu tip of the pyramid structure. (c) The double-logarithmic I-V curve of the Cu pyramid-based memory device on electroforming.



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4. CONCLUSIONS In summary, we have demonstrated that selective oxidation, derived from a structured active electrode, enables reliable multilevel resistive switching and low-power consumption in RRAM devices. High-quality Cu pyramid arrays with uniform size and a sharp tip were fabricated via the template-stripping method, and employed as the active electrodes. The tipenhanced electric field and high surface energy of the Cu pyramid facilitated ionization of Cu atoms and fast migration of generated Cu ions to the counter electrode. Therefore, selective oxidation near the tip region of the structured, active Cu electrode enabled controlled growth of a single Cu CF, suppressing CF growth in other regions and utilizing lower forming powers. The location control of CFs in RRAM was achieved with highly uniform forming voltages and low power consumption, leading to reliable cell-to-cell performance for MLC operation. This result has great potential for practical application in high-storage RRAM technology.

ASSOCIATED CONTENT Supporting Information Schematic diagram for the preparation process of Cu pyramid-based resistive memories; experimental setup to observe conductive filaments in resistive memory devices; I-V curves and cumulative probability graph for the forming process of 20 film-based memory device and cycle test; I-V characteristics with controlled compliance currents for MLC operation in 20 pyramid-based memory devices; cross sectional TEM images of electro-formed RRAM; simulation results of the electric fields for the Pt/Al2O3/Cu pyramid-based RRAM; finiteelement modeling to estimate the electric field near the tip with various angles in the pyramid-based memory devices; the direction of migration of the generated Cu ions according to the gradient of the electric fields. This material is available free of charge via the Internet at http://pubs.acs.org.

AUTHOR INFORMATION


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Corresponding Author *E-mail: (J.H.P.) [email protected], (S.-S.L.) [email protected], and (K.-Y.S.) [email protected]

Notes The authors declare no competing financial interest.

ACKNOWLEDGMENTS We acknowledge the financial support from the R&D Convergence Program of National Research Council of Science and Technology of Republic of Korea and a Korea Institute of Science and Technology internal project. S.-S.L. appreciates the research grant from the KUKIST Graduate School. This research was also supported by Hallym University Research Fund, 2017 (HRF-201703-005).



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TOC figure


Reliable Multi-State Data Storage with Low-Power Consumption by

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