Remote Gating of Schottky Barrier for Transistors and Their Vertical

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Remote Gating of Schottky Barrier for Transistors and Their Vertical Integration Young Jin Choi,†,¶ Seongchan Kim,†,¶ Hwi Je Woo,† Young Jae Song,†,‡ Yoonmyung Lee,§ Moon Sung Kang,*,⊥ and Jeong Ho Cho*,∥

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SKKU Advanced Institute of Nanotechnology (SAINT), ‡Department of Nano Engineering, and §Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 440-746, Republic of Korea ⊥ Department of Chemical and Biomolecular Engineering, Sogang University, Seoul 04107, Korea ∥ Department of Chemical and Biomolecular Engineering, Yonsei University, Seoul 03722, Korea S Supporting Information *

ABSTRACT: This paper introduces a strategy to modulate a Schottky barrier formed at a graphene−semiconductor heterojunction. The modulation is performed by controlling the work function of graphene from a gate that is placed laterally away from the graphene−semiconductor junction, which we refer to as the remote gating of a Schottky barrier. The remote gating relies on the sensitive work function of graphene, whose local variation induced by locally applied field effect affects the change in the work function of the entire material. Using Kelvin probe force microscopy analysis, we directly visualize how this local variation in the work function propagates through graphene. These properties of graphene are exploited to assemble remote-gated vertical Schottky barrier transistors (v-SBTs) in an unconventional device architecture. Furthermore, a vertical complementary circuit is fabricated by simply stacking two remote-gated v-SBTs (pentacene layer as the p-channel and indium gallium zinc oxide layer as the n-channel) vertically. We consider that the remote gating of graphene and the associated device architecture presented herein facilitate the extendibility of graphenebased v-SBTs in the vertical assembly of logic circuits. KEYWORDS: Schottky barrier transistor, remote gating, graphene, Kelvin probe force microscopy, vertical integration single device placed at the bottom.41,42 Moreover, the vertically integrated devices based on layer-by-layer stacking of functional materials do not require saving a well spacing between the n- and p-channels, which is necessary in the conventional lateral-type CMOS technology to prevent crosstalk between the complementary channels and to avoid latch up. In fact, a common design rule for the well spacing is to separate the nand p-MOSFET channels by 6 times the minimum width of the line, whereas the vertically stacked channels from additive processes do not require this consideration. Overall, the vertical stacking of unit vertical devices can greatly amplify the areal integration density of transistors. However, this potential of v-SBTs can be realized after resolving a fundamental issue with the device structure. Because the gate dielectric in a v-SBT has the function of controlling the injection of charge carriers to the vertical channel, this insulating layer has to be placed on top of (for a top-gate v-SBT) or beneath (for a bottom-gate v-SBT) the

T

he gapless electronic structure of graphene, which exhibits linear energy dispersion near the Dirac voltage, permits the development of an unconventional device architecture.1−8 In particular, graphene can be exploited as the electrode that yields a tunable semiconductor−electrode injection barrier as the Fermi energy level of graphene can be tuned widely by the application of an external electric field.9−20 This mechanism sets the basis for graphene-based vertical Schottky barrier transistors (v-SBTs); the current level of these devices can be changed by controlling the SB height via tuning the gate bias.21−33 Such a vertical transistor structure is expected to trigger a paradigm shift in electronic device architecture and associated circuit design. A vertical channel, unlike the lateral channel used in conventional transistors, can, in principle, mitigate the challenges to achieving a nanoscale channel length as the channel length can be determined simply from the thickness of the semiconductor layer.11,22,34−36 Furthermore, the vertical configuration of the unit transistor may facilitate the integration of multiple devices in an entirely different vertical scheme.37−40 Vertical stacking of unit devices does not consume additional chip estate beyond what is needed for a © 2019 American Chemical Society

Received: March 22, 2019 Accepted: June 25, 2019 Published: June 25, 2019 7877

DOI: 10.1021/acsnano.9b02243 ACS Nano 2019, 13, 7877−7885

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Scheme 1. Schematic Description of Current Path between Vertically Integrated SBTs: (a) Vertically Integrated Transistors Based on Conventional SBT Architecture and (b) Vertically Integrated Transistors Based on Unconventional, Simple SBT Architecture That Does Not Include the Insulating Layer in the Central Path of the Channel Current Flux

Figure 1. (a) Schematic illustration explaining the variation of the graphene work function as a function of distance from ion-gel gate dielectric layer. (b) Schematic of measurement setup of KPFM. (c) KPFM images acquired at different positions (d = 50, 150, 250, and 350 μm) under different VG values (−2, −1, 0, 1, and 2 V). (d) Histograms of surface potential values extracted from different KPFM images. (e) Average surface potential values measured at different d and VG values. (f) Maximum change in surface potential between VG of +2 and −2 V as a function of d.

source electrode.15,28,30 This indicates that if more than two vSBTs are to be stacked vertically, an electrically insulating layer needs to be inserted between the channels of the devices. In such a scenario, the electrical current between the stacked transistors cannot flow vertically in a straight line (along the direction of the transistor channel); instead, it would have to bypass the inserted insulating layer through complicated interconnects (Scheme 1a). Integrating v-SBTs in a drastically simplified design is possible if the work function of the

graphene source electrodes can be modulated without having to place a gate dielectric layer directly either on top of or beneath the graphene electrode (Scheme 1b). In such a scenario, the current will flow between the stacked devices along the direction of the channel current without a bypass. Such straightening of the current path between neighboring transistors can greatly simplify the structure of the threedimensionally integrated circuit and the associated fabrication process. 7878

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Figure 2. (a) Schematic of measurement setup of KPFM for ion-gel-gated IGZO. (b) KPFM images and histogram of surface potential values of IGZO at different VG values (−2, −1, 0, 1, and 2 V). (c) Average surface potential values of IGZO measured at different VG values. (d) Schematic of measurement setup of KPFM for 110 nm thick Al2O3-gated graphene. (e) KPFM images and histogram of surface potential values of graphene at different VG values (−20, −10, 0, 10, and 20 V). (f) Average surface potential values of graphene measured at different VG values.

propagate through graphene, and the local work function of the entire material can change even at the position where the graphene strip is not in direct contact with the gate dielectric layer. Such an indirect method to control the work function of graphene constitutes the fundamental principle of the remote control of the SB, which is the core strategy introduced in this paper. KPFM analysis was used to examine the propagated variation of the work function on the locally gated graphene strip (Figure 1b).44 To prepare the sample for the KPFM measurement, chemical vapor deposition (CVD)-grown monolayer graphene was transferred (Figure S1) and patterned onto a Si/SiO2 substrate prepatterned with Au contacts. A pair of prepatterned Au contacts later served as the ground and the gate electrodes of the measurement sample. Subsequently, an ion-gel gate dielectric was photopatterned such that it partially covered the graphene strip and bridged the graphene to the prepatterned Au contact. Upon the application of VG, the KPFM tip (Au) was scanned over a region that was not directly covered with the ion-gel electrolyte. Because the parameter obtained from the KPFM apparatus (eVCPD) reflects the relative offset between the work function of the KPFM tip (ΦAu) and that of the sample of interest (Φgraphene), the twodimensional KPFM image visualizes the areal distribution of the local variation in the work function of the sample. Accordingly, our KPFM measurement could reveal the influence of gating of one side of a graphene strip on the work function on the other side of the graphene strip as a function of VG. In particular, by performing the KPFM measurement at different regimes located at different distances (d) from the section of the graphene strip that was covered with the ion-gel layer, we could directly visualize the gatingdistance-dependent variation in the work function induced by the remote gating.

In this work, we introduce a strategy to modulate the height of a SB formed at a graphene−semiconductor heterojunction. This modulation is performed by controlling the work function of graphene from a gate that is placed laterally away from the graphene−semiconductor junction, which we refer to as the remote gating of a SB. This remote gating relies on the work function of graphene, which can even change in response to a local variation in the carrier density induced by a locally applied field effect. Using Kelvin probe force microscopy (KPFM) analysis, we directly visualize how this local variation in the work function propagates through graphene. These properties are exploited to stack v-SBTs with a remote-gated graphene source electrode in an unconventional device architecture. Furthermore, a complementary vertical logic is fabricated by simply stacking two remote-gated v-SBTs (pentacene layer as the p-channel and indium gallium zinc oxide (IGZO) layer as the n-channel) vertically.

RESULTS AND DISCUSSION Consider a graphene strip that is partially covered with an iongel layer and a metal contact (Figure 1a). The ion-gel layer can serve as the electrochemical gate dielectric; therefore, the work function of the graphene strip can be modulated by applying a bias to the metal contact (VG). Because the ion-gel layer covers only a fraction of the graphene strip, the application of VG would directly modulate the work function of the graphene strip that is placed underneath this layer in an electrostatic manner, which is different from chemical doping method.43 At the same time, the work function of the graphene strip that is not covered with the ion-gel layer should also be affected by VG. This is because the density of states of graphene, especially near its Dirac condition, is so small, such that even a small change in the local charge carrier density can influence the electronic structure at the neighboring areas. Overall, the variation in the work function induced by the gate can 7879

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Figure 3. (a) Schematic of the cross section of v-SBT with gate electrodes positioned at different d. (b) Transfer characteristics of v-SBT with gate electrodes positioned at different d at fixed VD = 0.1 V. (c) ON current density at VG = 2 V and ON/OFF current ratio of v-SBT. (d) Output characteristics of v-SBT. (e) Representative temperature-dependent output curves of v-SBT with gate 1 at VG = −2 and +2 V. (f) Plots of ln(I/T2) versus 1/kBT of v-SBTs with gate 0 and gate 1 at different VG values. (g) Gate-dependent modulation of φSB.

Figure 1c shows a series of 1 μm × 2 μm KPFM images that were acquired at different positions (d = 50, 150, 250, and 350 μm) under different VG values (−2, −1, 0, 1, and 2 V). The darker region in the KPFM images corresponds to a position in the film with a more negative surface potential, whereas the brighter region corresponds to that with a more positive surface potential. The series of images clearly show that application of a positive VG leads to a positive enhancement of the surface potential. This implies that graphene becomes more n-doped when it is gated with a positive VG locally through the ion gel. In contrast, application of a negative VG results in p-doping of the graphene layer. The electrostatic modulation of graphene by the remote gating was additionally confirmed from a separate experiment directly measuring the sheet resistance of a graphene strip under VG applied at the remote gate (d = 50 μm), which showed a consistent trend obtained from the surface potential measurement (Figure S2). More importantly, the series of images also show that the doping effect on graphene depends on the distance from the locally gated area. Whereas the application of different VG values induces a large contrast in the KPFM images when they are acquired from the regime at d = 50 μm, the contrast in those acquired at d = 350 μm is hardly perceivable. These results indicate that the extent of the remote gating depends on d and that the remote gating is effective up to a finite distance. For a quantitative analysis, the histograms of the surface

potential values extracted from the different KPFM images were constructed (Figure 1d). The topmost histogram shows the counts of surface potential values measured at d = 50 μm under different VG values (−2, −1, 0, 1, and 2 V), whereas the bottom-most histogram depicts the counts of surface potential values measured at d = 350 μm. The large VG-dependent variation in the histogram at d = 50 μm is gradually suppressed with increasing d. The average surface potential values measured at different d and VG values are summarized in Figure 1e, and the change in the surface potential at VG = +2, 0, and −2 V is plotted in Figure 1f as a function of d. At d = 50 μm, the work function of graphene can be modulated by a value as large as 1.1 (±0.1) eV by remote gating using the iongel electrolyte (Figure S3). These results provide an important basis for demonstrating our strategy for the vertical integration of v-SBTs as proposed above. We note that remote gating is not a distinct feature of semimetallic graphene. The work function of a strip of a semiconductor (e.g., IGZO) can also be remote-gated through the very same ion-gel gate dielectric. Figure 2a shows a schematic description of the sample used to examine the possibility of remote gating of a strip of IGZO film. Figure 2b shows a series of KPFM images acquired at a distance of d = 30 μm from the edge of the ion-gel layer under application of various voltages to the gate. The bottom panel of Figure 2b shows the histogram of the surface potential difference at 7880

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ACS Nano different VG values, as obtained from the KPFM images. Although the possibility of remote gating of IGZO could be confirmed, the degree of modulation achievable for IGZO was smaller than that achievable for graphene (Figure 2c). We attribute this difference in the degrees of modulation to the density of states near the Fermi level of the material. For semimetallic graphene, which has a rather low density of states near the Dirac condition, even a small change in the electron density can induce a large shift in the work function of the material, and a local variation in the work function can readily propagate through the material. In contrast, for IGZO or for any other semiconductor, the much higher density of states of the material prevents a drastic change in the work function with a change in the electron density. Consequently, the propagation of the variation in the work function induced by local gating of the material to the rest of the material would be less pronounced. We also point out that the large variation in the work function of graphene induced by remote gating at such a small voltage (1 μF/cm2).45−48 The charge density induced by gating is equal to the product of the capacitance of the gate dielectric and the applied voltage. When a gate dielectric with a lower capacitance (for example, 110 nm thick Al2O3 layer with a specific capacitance of 75.2 nF/cm2) is used (Figure 2d), the remote gating of graphene at d = 30 μm induces only a small change of 0.08 eV in the work function, even at 20 V (Figures 2f,g and S4). Overall, we find that remote gating can be achieved not only for graphene but also for semiconductors through the use of gate dielectrics. However, the remote-gating effect is more pronounced for materials with a low density of states when they are remotegated using a highly capacitive gate dielectric system. These conditions are met when graphene is used as the material in combination with ion gel as the gate dielectric. Next, the concept of remote gating was applied to the design of an unconventional v-SBT structure with a graphene source electrode. Figure S5 shows a schematic of the fabrication procedure for a unit, top-gated v-SBT based on an IGZO− graphene heterojunction with a remote-gateable graphene electrode. Details of the fabrication procedure are provided in the Methods section. Figure 3a shows a schematic of the device cross section with gate electrodes positioned at different d, where d is defined as the distance of the edge ion-gel gate from the center of the transistor channel. Gate 0 is located directly on top of the IGZO channel (d = 0 μm), whereas gate 1, gate 2, and gate 3 are separated from the channel by d = 200, 450, and 700 μm, respectively. Figure 3b shows a series of transfer characteristics (i.e., drain current (ID) versus gate voltage (VG) relations obtained at a fixed drain voltage (VD)) for a single IGZO channel that were obtained by using gate contacts located at different positions. The curves were measured at a positive VD (=0.1 V); electrons were injected from the graphene source electrode to the IGZO channel. The use of gate 0 corresponds to the device architecture of a conventional graphene-based v-SBT, where the charge injection from the SB formed between the graphene source electrode and the IGZO channel is directly controlled by the gate dielectric and the gate electrode placed on the vertical trajectory of the channel. When gate 0 was used for gating (black curve in Figure 3b), ID could be modulated by 3 orders of magnitude upon sweeping of VG from −2 to +2 V. Such an effective modulation of the channel current in such a narrow range of VG is attributed to the high capacitance of the

electrolyte-based gate dielectric as discussed above. When gate 1separated from the channel by 200 μmwas used for gating, ID could be modulated by more than 2 orders of magnitude upon sweeping of VG in the same range (red curve in Figure 3b). The ON current and OFF current of the channel were lower and higher, respectively, than those when gate 0 was used for gating. However, these results clearly demonstrate that a v-SBT can be operated reasonably through remote gating. The ON current density of the v-SBT with a gate at d = 0 was 6.4 × 10−1 A/cm2, but that with a gate at d = 700 μm was 7.3 × 10−2 A/cm2. The OFF current density of the device was 3.9 × 10−4 A/cm2 when a remote gate placed at d = 0 μm was used, but it gradually increased up to 3.0 × 10−2 A/cm2 when a remote gate placed at d = 700 μm was used. Overall, the modulation of the channel current became less prominent with an increase in the distance at which the remote gate was placed (the green and blue curves in Figure 3b were obtained using gate 2 and gate 3, respectively). The ON/OFF current ratio of the device, which reflects the ability of the gate bias to modulate the current level, decreased gradually from 1.6 × 103 when a gate located at d = 0 μm was used to 2.4 when a gate located at d = 700 μm was used. Figure 3c summarizes the ON current density (obtained at VG = 2 V) and the ON/OFF current ratio for the vertical IGZO channel operated through remote gates placed at different locations. The results shown here are the average values of results obtained from more than five devices. These results are consistent with the results obtained from the KPFM analysis, depicted in Figure 1, indicating that the remote-gating effect faded away as d increased. The given d-dependent change in the transistor characteristics indicates that the device performance would be improved if one could place the remote gate as close as possible to the channel, which would be a natural consequence of down-scaling the devices. Regardless of the position at which the gate is located, the modulation of the current as well as the operation of the v-SBT can be described as follows. For v-SBTs at positive VD, electrons (i.e., the majority carriers of the IGZO channel in our devices) are injected into the channel from the source electrode (the graphene electrode in our devices). In such a situation, application of a positive VG to the remote gate would decrease the work function of the graphene source electrode as well as the SB height at the graphene−IGZO (source− channel) junction for electron injection. Consequently, electrons would be readily injected into the channel from the graphene electrode, and higher ID would be obtained. In contrast, application of a negative VG to the remote gate would increase the work function of the graphene source electrode as well as the SB height at the source−channel junction. Consequently, the electron injection would become difficult, and lower ID would be obtained. As long as the graphene electrode can be remotely gated to modify its work function, the explained operation principle will be applicable to our vSBTs. The only difference will be the degree of modulation achievable, which depends strongly on d. The output characteristics of the v-SBT (ID−VD relations obtained at fixed VG values; see Figure 3d) show behavior that is consistent with that of the transfer characteristics; this supports the proposed operation mechanism of the v-SBT structure. For the measurement of the output characteristics, VD was swept between +0.4 and −0.4 V. Regardless of the location of the remote gate, the output characteristics show 7881

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Figure 4. (a) Transfer characteristics of remote-gated pentacene v-SBT at different VD values. (b) Circuit diagram and (c) schematic device structure of vertical complementary circuit based on v-SBTs with pentacene and IGZO as the p-channel and n-channel, respectively. (d) Voltage transfer characteristics and signal gain of vertical complementary logic. (e) Schematic band diagram of circuit operation at positive and negative VIN values.

asymmetric gate dependence.49 The variation in ID is more pronounced at positive VD than at negative VD. The asymmetry arises from the different directions of flow of electrons (i.e., the majority carriers of the IGZO channel in our devices) at different polarities of VD. At positive VD, electrons are injected into the channel from the graphene source electrode, whose work function can be modulated by the remote gating. Therefore, a large change in ID is observed with changing VG. Also, because the nature of the graphene−IGZO contact changes from a Schottky-type at negative VG values to an Ohmic-type at positive VG values, the shape of the ID−VD relation gradually changes toward a linear one with increasing VG values positively (Figure S6). Meanwhile, at negative VD, electrons are injected into the channel from the indium−tin− oxide (ITO) drain electrode, whose work function is hardly affected by the remote gating. Therefore, at negative VD values, a significant change in ID is not observed with changing VG. Furthermore, the influence of VG is suppressed with increasing d, which is consistent with the transfer characteristics shown in Figure 3b. The SB modulation performed by remote gating was analyzed quantitatively via temperature-dependent transport measurements of the device. The SB height (φSB) at the graphene−IGZO junction can be estimated according to the thermionic emission theory.32,50,51 According to this theory, φSB is related to the saturation current (ISAT) of a diode according to the following equation:

VD relations of the v-SBT with gate 0 and gate 1, respectively. The series of curves were obtained under VG = −2, 0, and +2 V. Typically, Isat of a given Schottky diode is obtained from the y-intercept of the tangential lines under a reverse bias (VD > 0). Figures 3e,f shows ln(I/T2) versus 1/kBT plots of the v-SBT obtained at different VG applied through gate 0 and gate 1, respectively. From the slope of the curves, the values of φSB at various VG applied through the two different gates could be extracted. The resultant gate-dependent modulation of φSB is shown in Figure 3g. For the v-SBT with gate 0, φSB changed from 1.2 to 0.2 eV with an increase in VG from −2 to +2 V. The φB modulation was estimated to be around 1.0 eV within a VG sweep window of 4 V. The modulation of φSB of the v-SBT operated with remote gate 1 was found to be as large as 0.73 eV, even though gate 1 was separated from the channel by d = 200 μm. We note that this modulation value of φB (0.73 eV) determined from the temperature-dependent transport measurements agrees reasonably well with the value of ΔWgraphene (0.7 eV) obtained from the KPFM measurement. Remote gating could be achieved not only for the vertical IGZO n-channel but also for a pentacene p-channel deposited onto a graphene source electrode. Pentacene v-SBTs at VD = −0.5 V provided a maximum current density of 47.9 mA/cm2, an ON/OFF current ratio of ∼103, and a subthreshold swing of 441 mV/dec (Figures 4a and S9). Based on these remotegated v-SBTs, a simple architecture for vertical complementary logic circuits could be devised, which was thus far unachievable using any previously developed device structure. The benefit of remote gating is that it can modulate the height of the SB of an electrode−semiconductor heterojunction without the insertion of an insulating dielectric layer in the coral direction of the charge flux in the device. The removal of the insulating layer along the current path of a device allows the current path between vertically stacked transistors to be linearized. This provides a much simpler design for the integration of transistors and their fabrication processes. Furthermore, it

ij qφ yz Isat = AA*T 2 expjjj− SB zzz j kBT z k {

where A is the area of the Schottky junction, A* is the effective Richardson constant, q is the elementary charge, kB is Boltzmann’s constant, and T is the absolute temperature. Accordingly, φSB of a given Schottky diode can be obtained from the slope of the ln(Isat/T2) versus 1/kBT relation. Figures S7 and S8 show the representative temperature-dependent ID− 7882

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aqueous LCE-12 (Cyantek Co.) solution (LCE-12/H2O = 1:4). Subsequently, single-layer graphene, synthesized by CVD, was transferred onto the prepatterned glass/ITO/IGZO substrate and patterned by the photolithography and reactive ion etching.53−55 Because the contaminants on graphene lead to substantial increase in the threshold voltage of the device, thermal treatment was applied to the graphene electrode (at 200 °C for 2 h) once it was patterned onto the IGZO layer. Separately, an ion-gel solution was prepared by mixing a polyethylene glycol diacrylate monomer, 2-hydroxy-2methylpropiophenone initiator, and 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ionic liquid in a weight ratio of 2:1:22. This ion-gel solution was drop-cast onto the substrate and patterned by exposure to UV light (365 nm, 350 W) for 10 s through a photomask.48 The unexposed part of the drop was gently removed by H2O. For fabrication of the vertically stacked complementary circuit, a 200 nm thick pentacene (99%, Aldrich) layer was thermally deposited directly onto the graphene layer of the IGZO-based remote-gated v-SBTs prepared by the above-described procedure at a rate of 0.12 Å/s under a pressure of 10−7 Torr. Finally, a 40 nm thick Au electrode was thermally deposited onto the pentacene layer through a photomask. The surface potential of ion-gel-gated graphene was measured by Kelvin probe force microscopy (NX10 AFM, Park Systems) under ambient conditions. The current−voltage characteristics of the device were measured with a probe station (MS Tech. Co.) using a Keithley 4200 under dark and vacuum conditions.

provides extendibility in the vertical assembly of logic circuits. As a proof of concept, we assembled a vertical complementary circuit by simply stacking multi-heterostructures of an ITO electrode, an IGZO n-channel, a remote-gateable graphene electrode, a pentacene p-channel, and a Au electrode. The resulting complementary structure directly realizes the circuit diagram of a complementary logic typically drawn in plane (Figure 4b) in a vertical space (Figure 4c). A supply voltage (VDD) was applied to the Au electrode, whereas the ITO electrode was connected to the ground. The input voltage (VIN) was applied to the remote gate, and then, the output voltage (VOUT) was measured from the graphene source electrode. Figure 4d shows the voltage transfer characteristics of the vertical complementary circuit with the remote-gateable graphene electrode, which were measured at negative VDD (VDD = −0.1, −0.3, and −0.5 V). At a negative VDD, application of a negative voltage to the remote gate (i.e., negative VIN) caused the n-channel to turn off but enabled the p-channel to be turned on. Therefore, VOUT reflected the magnitude of VDD (Figure 4e); this corresponds to the “0” logic state of the circuit. When a positive VIN was applied, the n-channel was turned on, but the p-channel was turned off. Consequently, VOUT reflected the voltage of the ground (i.e., 0 V), which corresponds to the “1” logic state of the circuit. The signal gain, defined as the absolute value of dVOUT/dVIN, was around 2.6 at VDD = −0.5 V (right panel of Figure 4d). This value was higher than that from a laterally connected pentacene p-channel v-SBT and PTCDI-C8 n-channel v-SBT with an ion-gel gate dielectric (∼0.6).52

ASSOCIATED CONTENT S Supporting Information *

The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acsnano.9b02243. Additional experimental details and figures; Raman spectrum of the CVD-grown graphene, KPFM measurement results, fabrication procedure, temperature-dependent output characteristics, and electrical properties of pentacene v-SBTs (PDF)

CONCLUSION Here, we introduced an interesting operational scheme for modulating the SB at a graphene−semiconductor heterojunction. The scheme relies on the low density of states of graphene, which causes the work function of the entire material to respond even to a local variation in the charge density. On the basis of this feature, we could indirectly modulate the SB formed at the graphene−semiconductor heterojunction by using an ion-gel gate dielectric and a gate that were placed laterally away from the heterojunction. This freedom with regard to the location of the gate facilitated the design of a completely different v-SBT architecture. Because the electrically insulating gate dielectric layer was not placed in the vertical path of the current flux in the unconventional device architecture, logics based on remote-gated v-SBTs could be assembled simply by stacking the devices vertically without any complicated interconnects. The extendibility of the device architecture is expected to provide the design of highly integrated logics that truly exploit the vertical transistor channel.

AUTHOR INFORMATION Corresponding Authors

*E-mail: [email protected]. *E-mail: [email protected]. ORCID

Young Jae Song: 0000-0001-6172-3817 Moon Sung Kang: 0000-0003-0491-5032 Jeong Ho Cho: 0000-0002-1030-9920 Author Contributions ¶

Y.J.C. and S.K. contributed equally to this work.

Notes

The authors declare no competing financial interest.

ACKNOWLEDGMENTS This work was supported by a grant from the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2017R1A2B2005790, 2017R1A4A1015400, and 2017R1C1B2006789).

METHODS An ITO-coated glass was patterned through conventional photolithography and subsequent chemical etching with 35% HCl. An IGZO precursor solution was prepared by dissolving 0.085 M of indium nitrate hydrate, 0.0125 M of gallium nitrate hydrate, and 0.0275 M of zinc acetate dehydrate in 10 mL of 2-methoxyethanol, and then, the mixture solution was stirred at 75 °C for 12 h. The solution was spin-coated at 4000 rpm for 30 s onto the glass substrate with the prepatterned ITO. The resulting film (thickness = 48 nm) was annealed at 60 °C for 2 min and then sintered via high-density, deep-UV treatment (wavelengths: 253.7 and 184.9 nm) under a nitrogen flow (75 L/min) for 10 min. The UV-sintered IGZO film was then patterned via photolithography and chemical etching with an

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DOI: 10.1021/acsnano.9b02243 ACS Nano 2019, 13, 7877−7885

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DOI: 10.1021/acsnano.9b02243 ACS Nano 2019, 13, 7877−7885