Resist-Free Direct Stamp Imprinting of GaAs via Metal-Assisted

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Functional Nanostructured Materials (including low-D carbon)

Resist-Free Direct Stamp Imprinting of GaAs via Metal-Assisted Chemical Etching Kyunghwan Kim, Bugeun Ki, Keorock Choi, Seung Min Lee, and Jungwoo Oh ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.9b00456 • Publication Date (Web): 20 Feb 2019 Downloaded from http://pubs.acs.org on February 23, 2019

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ACS Applied Materials & Interfaces

Resist-Free Direct Stamp Imprinting of GaAs via Metal-Assisted Chemical Etching Kyunghwan Kim, Bugeun Ki, Keorock Choi, Seungmin Lee, and Jungwoo Oh*

School of Integrated Technology, Yonsei University, 85 Songdogwahak-ro, Yeonsugu, Incheon 21983, Republic of Korea

Yonsei Institute of Convergence Technology, Yonsei University, 85 Songdogwahakro, Yeonsu-gu, Incheon 21983, Republic of Korea

KEYWORDS: Resist-free direct imprinting, Nanoimprint lithography, Metal-assisted chemical etching, Nanostructure, Chemical imprinting, GaAs

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ABSTRACT

We introduce a method for the direct imprinting of GaAs substrates using wetchemical stamping. The pre-defined patterns on the stamps etch the GaAs substrates via metal-assisted chemical etching. This is a resist-free method in which the stamp and the GaAs substrate are directly pressed together. Imprinting and etching occur concurrently until the stamp is released from the substrate. The stamp imprinting results in a 3D anisotropic etching profile and does not impair the semiconductor crystallinity in the wet-chemical bath. Hole, trench, and complex patterns can be imprinted on the GaAs after stamping with pillar, fin, and letter shapes. In addition, we demonstrate the formation of sub-100 nm trench patterns on GaAs through a singlestep stamping process. Consecutive imprinting using a single stamp is possible, demonstrating the recyclability of the stamp, which can be used more than 10 times. The greatest benefit of this technique is the simple method of patterning by integrating the lithographic and etching processes, making this a high-throughput and low-cost technique.


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Introduction

To improve the performance of various semiconductor devices such as electronic,1–3 optoelectronic,4–6 and microelectromechanical (MEMS) devices,7 3D patterns with high aspect ratios on semiconductors are fabricated by dry etching using plasma to achieve anisotropic etching profiles.8,9 In this process, plasma ions are accelerated and collide with the semiconductor substrates, potentially causing structural defects in the single crystal. Ion-induced defects form recombination sites, which reduce carrier lifetime and device performance. Crystal defects in silicon are easily removed by subsequent heat treatment, yielding a high quality crystalline material. On the other hand, defects in binary and ternary compound semiconductors are typically hard to repair.10,11

Metal-assisted chemical etching (MacEtch) is a wet-based anisotropic etching technique proposed as an alternative to conventional dry etching. 12–26 Semiconductor substrates covered with catalytic metals are etched in an etching bath of an acid and an oxidant. In the conventional MacEtch processes, the semiconductors in contact with the metals are electrochemically etched in the 4 ACS Paragon Plus Environment

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vertical direction by the catalytic reaction of the metal. Without high-energy plasma and complex vacuum equipment, the anisotropic etching characteristics of MacEtch yield structures with high aspect ratios on some semiconductors. 12–21 Because the etching occurs via an electrochemical reaction in a wet-etching bath without plasma ions, single crystallinity is preserved in the semiconductor material.

To fabricate a MacEtch structure, the polymer resists must be patterned on the semiconductor by photolithography. In addition, metal deposition is required to induce the catalytic reaction of the semiconductors with the etchant. Some studies have simplified the metal patterning process with nanosphere lithography15, 16, 22 or thermal agglomeration.17, 18 In both cases, metals are left inside the semiconductors after the MacEtch process. Thus, processing for metal removal is required to avoid metal contamination and the degradation of device performance.18–20, 23

Recent lithographic methods for fabricating nanoscale semiconductors have required extreme ultraviolet optics27, 28 or an electron-beam system,29 which are complicated and expensive. Nanoimprint lithography (NIL) simplifies the lithographic process by using mechanical templates and imprint resists instead of irradiation with 5 ACS Paragon Plus Environment


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light or electrons.30–39 NIL has drawn much attention because it is not limited by the diffraction nor scattering of photons. Furthermore, the nanoscale patterns can be transferred onto semiconductors repeatedly, which reduces the processing complexity and cost. In a typical NIL process, a pre-defined template is pressed onto a polymer resist at elevated temperatures33–36 or under ultraviolet (UV) illumination.37–39 Subsequent dry etching eventually replicates the imprint patterns on the semiconductors. Despite the many advantages offered by NIL, some defects associated with the resist occur, such as delamination because of the adhesion between the template and the resist and because of bubbles arising from air trapped in the resist. 34, 37, 38

In this work, we directly imprinted GaAs substrates using a chemical stamp in an etching bath. This method uses a template stamp as in NIL, but the stamp is directly pressed on the semiconductor and the semiconductor is etched by MacEtch.40–46 This method imprints the stamp patterns directly on the semiconductor without using an intermediate resist followed by dry etching. The catalytic metals pre-defined in the stamp induce the electrochemical reaction with the semiconductor, and the patterns 6 ACS Paragon Plus Environment

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are imprinted on the semiconductor. In this chemical imprinting step, the metalcoated stamp is placed in a solution containing an acid and an oxidizing agent. In direct imprinting, the lithographic and etching processes occur concurrently, and imprinting stops only when the stamp is released from the semiconductor. In this process, metal catalysts are not left in the semiconductor and are not consumed during the imprinting process,24 which enables the repeated use of the stamp. This imprinting technique enables nano/microscale 3D patterning directly on semiconductors, representing a dramatic improvement in etching techniques.

Experimental Section

Si stamps were fabricated by conventional semiconductor processes: photolithography, dry etching, the Bosch process, and metal deposition. Borondoped p-type Si (100) substrates with 650–700-μm thickness and 5–30-Ω cm resistivity were used. After cleaning the Si with acetone, isopropanol (IPA), and deionized (DI) water, the native oxide was removed using buffered oxide etchant



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(BOE). The photoresist-patterned Si wafer was subjected to the Bosch process via inductively coupled plasma reactive-ion etching (ICP-RIE) with octafluorocyclobutane (C4F8) and sulfur hexafluoride (SF6) plasma. After etching to a depth of about 5-μm using the Bosch process, the photoresist was removed using an O2 plasma asher and acetone, IPA, and DI water cleaning. SF6 plasma was used for the trimming process, and the pattern size was reduced to the submicron scale. The residues and oxide formed during the RIE processes were removed using piranha solution and BOE. Then, 100-nm C4F8 films were deposited to insulate the stamp electrically from the MacEtch redox process. Finally, a 10-nm Cr adhesion layer and a 100-nm Au catalyst layer were deposited by direct current (DC) sputtering.

As substrates, 1.13–2.06 × 10-3 Ω‐cm resistivity and 600–650-μm-thickness Si doped n-type GaAs (100) was used for imprinting. The GaAs substrate was cleaned using acetone, IPA, and DI water. The etchant was a mixture of KMnO4 (50–100 mg), HF (48%, 30 mL), and DI water (30 mL) and was mixed for 30 min. The GaAs substrate was then placed in physical contact with the stamp and etched in the etchant. Etching occurs through the electrochemical reaction promoted by a Au 8 ACS Paragon Plus Environment

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catalyst. The morphology and etch depth of the imprinted GaAs were characterized by optical microscopy (OM), field emission-scanning electron microscopy (FE-SEM), and atomic force microscopy (AFM). The chemical composition of the imprinted GaAs was characterized by energy dispersive X-ray spectroscopy (EDS) and timeof-flight secondary ion mass spectrometry (TOF-SIMS).

Results and Discussion

Figure 1 illustrates the etching mechanism of the chemical imprinting process. The pre-defined stamp is pressed onto the GaAs substrate. Only the area where the stamp and the GaAs substrate are in contact is selectively etched in the etch bath. The GaAs is electrochemically etched by the redox reaction of the Au catalyst. The Au catalyst accelerates the reduction of KMnO4, which generates electronic holes. The reduction process is greater in the Au region exposed to the solution than in the region in contact with the GaAs. The generated holes diffuse through the metal layer and oxidize the GaAs. These holes are not injected into the Si stamp because of the



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electrical barrier (C4F8) placed between the Si and the metal catalyst, so deformation of the stamp structure does not occur. The oxidized GaAs is subsequently etched by an HF solution in the etching bath. The reactant and byproducts diffuse between the stamp and the GaAs. These reactions are the basic principles of MacEtch. Etching stops when the stamp is released from the GaAs, and the stamp is recycled for another round of chemical imprinting.

Figures 2a-1–e-1 show SEM images of template patterns fabricated on the Si substrates by using conventional semiconductor processes, i.e., photolithography, dry etching (reactive-ion etching (RIE) and the Bosch-process), and metal deposition (Cr/Au). Figure 2a-1 shows a circular pillar pattern with 1.1-μm diameter. The patterns were coated with a C4F8 polymer, followed by Cr/Au metal (Figure 2b-1). The C4F8 film serves as an electrical barrier to the migration of electronic holes, which prevents the stamp itself from being etched during chemical imprinting. Figures 2c-1 and d-1 show fin shapes with 1-μm width and 4-μm pitch and a square mesh with 1-μm width and 8-μm pitch, respectively. Figure 2e-1 shows the school logo “YONSEI,” which contains various patterns in each letter. The letters Y and S 10 ACS Paragon Plus Environment

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are made of pillars, O and E are closed with continuous lines, and N and I contain straight lines. The aspect ratios of the circular pillar, fin shape, and square mesh in Figures 2a-1–d-1 are about five, and those of the patterns in Figure 2e-1 are about two.

We fabricated durable stamps on single crystalline Si to show the capabilities of this technique best, and the processing conditions were optimized to produce high aspect ratio template patterns. A high aspect ratio improves the flow of reactants and byproducts when contact is made with the semiconductor. This effect is even greater when the semiconductor is etched with closed patterns. The Young’s modulus of polydimethylsiloxane (PDMS) is approximately 1–2 MPa depending on the mixing ratio of the base and curing agent, whereas that of Si is 150 GPa and that of GaAs is 80 GPa. The technique introduced in this study does not imprint the resist, but directly imprints the crystalline semiconductor. Therefore, we designed a rigid stamp using silicon for the first attempt.

Figures 2a-2–e-2 show the SEM images after imprinting the GaAs with the stamp shown in Figures 2a-1–e-1 for 10 min. All patterns were successfully imprinted on 11 ACS Paragon Plus Environment


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the GaAs using the Si stamps. The size of the imprint patterns on GaAs slightly increased compared to that of the template patterns because both the side and endfaces of the stamp were deposited with metal. If the metal were deposited only on the end-face of the stamp, the increase in size after imprinting could be reduced. Figures 2a-2 and b-2 show the top- and cross-sectional views of hole arrays with 1.2-μm diameter and 3.5-μm depth after etching with column patterns. The holes were anisotropically etched in the vertical direction, resulting in an aspect ratio of three. Figures 2c-2 and d-2 show rectangular trenches with 1.2-μm width and 1.7-μm depth and square arrays with 8-μm pitch, 1.2-μm space, and 1.2-μm height. The etching depths of the trenches and square arrays were measured using crosssectional SEM images (Figure S1). Finally, Figure 2e-2 shows the “YONSEI” logo that was mirror symmetrically imprinted on the GaAs substrate with hole and line patterns. Stamp patterns with straight and curved lines, and pillar arrays were imprinted simultaneously.

Figure 3 shows the nanoscale imprinting capability. The SEM images show the trench patterns with 110-nm and 60-nm widths after the chemical-imprinting of GaAs 12 ACS Paragon Plus Environment

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using straight fins with 100-nm and 50-nm widths, respectively. The widths of the imprinted patterns became slightly wider than those of stamp patterns. This is attributed to the lateral distribution of electronic holes that were not immediately consumed under the stamp in the chemical etching. These holes diffused to the vicinity of the stamp and lateral etching occurred subsequently. We believe that the optimized reaction and mass-transport rates minimized this effect, improving pattern transfer fidelity.

Figures 4a and b shows the changes in the etch profile and depth as a function of imprinting time. At the beginning of the imprinting, chemical reaction occurs at the edge of the contact area. This results in a smooth slope at the top of the pattern, as shown in Figure 4a. When the etching time was less than 30 s, the etch rate was fast and the etched GaAs surface was flat. As the etching time increased, the etch rate slowed and the etching began to occur non-uniformly at the center and the edges, resulting in a W-shaped surface. This is a common occurrence in the MacEtch process.21, 25 Figure 4c illustrates the etching mechanism for the hole diffusion and mass transport of the reactants and products. Initially, injected electronic holes 13 ACS Paragon Plus Environment


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diffuse to adjacent of the contact area and react. Once the entire contact area has been etched, injected electronic holes are consumed or recombined with electrons before diffusing to areas adjacent to the contact area, and the short mass transfer path facilitates mass transfer to the center of the stamp, resulting in a flat surface. As the etch depth increases, the transfer path of the reactants and products needed for the chemical reaction increases. At the edge of the stamp, this mass transfer is faster than at the center, so the etch rate is also faster. Non-uniform etching decreases as the pattern size is reduced. In the direct imprinting process, electronic holes for oxidizing GaAs are generated by reaction with the etching solution around the metal catalysts, and they are transferred through the metal layer. Although the size of the pattern increases, the supply of holes for GaAs oxidation is maintained through the metal layer, but the supply rate of the liquid chemical for etching is slowed, especially in the center, which leads to non-uniform etching rates. The oxidized GaAs at the edge is immediately etched, but the etching of the oxidized GaAs at the center is delayed. For this reason, as the etch time increases, the local etch rate difference increases, and the overall etch rate decreases significantly. The


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non-constant etching rate is associated with a change in the path length for the mass transport of reactants and byproducts. This phenomenon is more obvious for large patterns. Nanoscale patterns are expected to be much less affected by nonuniformity.

Chemical imprinting tends to show a variation in the etch rate with the pattern density, which is equivalent to the proximity effects observed in RIE (Figure S1). During chemical imprinting, upon contact, the etchant is confined to the space between the stamp and the GaAs. The mass transport for chemical reactions varies according to the local variation of pattern density, which eventually alters the etch rates. The holes imprinted by the pillar array were deeper than those in the trench and square patterns imprinted by fins and a square mesh, respectively. In addition, in the same pattern, the volume of the confined etchant between the stamp and GaAs determined by the aspect ratio and spacing of the patterns results in a difference in the etch depth. The fin-shaped stamp patterns shown in Figure 2c-1 imprinted the GaAs to a depth of 1.7-μm (Figure S1b-2), whereas the stamp of finshaped patterns with 1-μm width, 1-μm space, and an aspect ratio of 2 resulted in 15 ACS Paragon Plus Environment


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shallowly imprinted GaAs (Figure S1d-2). In this respect, a stamp pattern having a high aspect ratio is helpful for reducing the non-uniformity of the etching rate in chemical imprinting.

Figure 5 shows the capability of this technique to imprint a large area with complex patterns. Figure 5a shows an optical microscope image of an alphabetic array (approximate size of 1 cm × 1 cm). Complex 3D features were defined with a pillar array as shown in the inset. The stamp was finished by the deposition of the Au catalyst after RIE and the polymerization of the Si substrate. Figure 5b shows an identical pattern imprinted with mirror symmetry on the GaAs. The pillar arrays in the entire Si stamp left hole arrays in the GaAs. The rainbow coloration of the periodic structure reveals the diffraction grating effects. The ability to imprint multiple patterns in a large area suggest that chemical imprinting has the potential to be applied to a variety of optical components. Figures 5b-1–b-3 show enlarged features of the imprinted alphabetic array on the GaAs substrate, suggesting that chemical imprinting can be successfully extended to large area substrates. The depth of the imprinted alphabetic array on GaAs is approximately 180 to 220 nm, as shown in the 16 ACS Paragon Plus Environment

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AFM line scan data (Figure S2). The variation in the depth is presumed to be caused by the pattern density variation and parallel misalignment between the stamp and the GaAs substrate during the imprinting.

Figures 6a–c show a series of photographs and Figures 6d–e show SEM images taken after the chemical imprinting of GaAs using the same stamp. The stamp was reused eleven times, and the etching time was 15 s. After the 3rd use, some portions were not printed correctly on the GaAs, possibly because the flat contact between the stamp and the GaAs substrate was imperfect. On the other hand, after the 4th use, the entire array was well imprinted on the GaAs. Thus, the contact between the stamp and the substrate must have been improved compared to the earlier attempts. Figures S3 and S4 show the optical microscope images of the alphabetic array imprinted on the GaAs after the 2nd and 4th uses of the stamp. The results indicate that the recycled stamp can be used to imprint a large area. After the 5th use, most of the pattern was not transferred to the GaAs because of peeling-off and destruction of the stamp (Figure S5). However, in some portions, the patterns of the stamp transferred to GaAs until the 11th attempt. Figures 6d–e and Figure S6 shows a 17 ACS Paragon Plus Environment


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series of SEM images taken after imprinting GaAs using a single stamp from the 1st to the 11th time for comparison. The well-defined hole arrays were maintained after imprinting multiple times. However, the presence of transferred particles or the incompleteness of our prototype equipment are causes for concern (Figure S7). In such conditions, the stamp does not etch the GaAs substrate. This suggests that improving the mechanical contact with a robust stamp could increase the repeatability of imprint quality significantly.

MacEtch fabricates anisotropic semiconductor profiles in a wet etching bath, and plasma ions and vacuum equipment, which are required for anisotropic etching, are not required. In addition, the wet-chemical reaction does not impair semiconductor crystallinity. This is a promising technique that can simplify conventional lithography and etching. Despite these advantages, one of the concerns over conventional MacEtch technology is the metal removal process. Using MacEtch on a semiconductor requires activation by a metal catalyst. To fabricate a semiconductor structure using MacEtch, the metal catalyst must be patterned on the semiconductor via lithography. The metal catalyst penetrates the semiconductor and is not 18 ACS Paragon Plus Environment

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removed. Thus, metal removal requires additional etching processes. On the other hand, direct imprinting does not require metal catalyst removal after etching is finished. EDS mapping images and TOF-SIMS analysis of the imprinted GaAs shows that metal catalyst is not transferred to GaAs during imprinting (Figure S8). The metal catalyst patterns are firmly attached to the stamp even after imprinting (Figure S9). When the stamp is released from the semiconductor, it can be recycled and used for the next round of printing.

Conclusion

Direct imprinting is a novel method for fabricating micro/nanoscale 3D patterns on semiconductors. This technique directly imprints semiconductors using chemical stamps by utilizing combined reactions of lithography and etching. Durable stamps made of Si using semiconductor processing allow the multiple imprinting of GaAs substrates. Using this method, complex alphabetic arrays were prepared on a centimeter scale. Conventional NIL uses pre-defined templates, which greatly



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simplifies the lithography steps. Beyond these advantages, direct imprinting is a resist-free process and is not affected by the various issues associated with resists. However, the direct imprinting process resulted in non-uniformity at the microscale, which is associated with mass transport for the chemical reaction.42–44 We believe that this issue can be solved through more sophisticated process optimization. In summary, direct imprinting has the potential to be applied in various fields as an alternative lithographic and etching method.


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FIGURES

Figure 1. Schematic of the chemical imprinting mechanism. (a) A stamp coated with a catalytic metal (Au) is fabricated on Si using conventional dry etching and metal deposition. The stamp and GaAs are pressed together in an etch bath. The GaAs substrate is directly imprinted by metal-assisted chemical etching. Etching stops when the stamp is released from the GaAs, and the stamp is recycled for another round of chemical imprinting. This is a resist-free method of imprinting lithography and direct etching. (b) Electronic holes are generated by the reduction of KMnO4 with 21 ACS Paragon Plus Environment


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a Au catalyst. The holes (h+) diffuse through the Au layer and oxidize GaAs, and the HF solution etches the oxidized GaAs. The transport of reactants and byproducts occurs between the stamp and the GaAs. The electrical barrier provided by C4F8 polymerization prevents the Si stamp itself from being etched during chemical imprinting.


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Figure 2. (a-1–e-1) SEM images of various stamp patterns fabricated on Si using conventional semiconductor processing (dry etching, plasma polymerization, and metal deposition). (a-1) Top view of pillar array with 1.1-μm diameter (aspect ratio of 5), (b-1) cross-sectional view of Si fins coated with C4F8 polymer (electrical barrier) and Cr/Au metal (catalyst), (c-1) top view of straight fins with 1-μm width and 4-μm pitch, (d-1) square mesh patterns with 1-μm width and 8-μm pitch, and (e-1) “YONSEI” logo pattern fabricated using pillar array, curved lines, and straight lines.


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(a-2–e-2) SEM images of corresponding patterns imprinted on GaAs after chemical imprinting. (a-2) Top view and (b-2) cross-sectional views of the hole array (aspect ratio of 3) stamped with a pillar array (a-1), (c-2) trench pattern stamped with fins (c1), (d-2) square arrays, and (e-2) mirror-symmetrically imprinted “YONSEI” logo (e1).



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Figure 3. SEM images of (a) 110-nm and (b) 60-nm width trench pattern imprinted on GaAs with stamp with 100-nm and 50-nm width fins.


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Figure 4. (a) Cross-sectional trench images on GaAs after chemical imprinting for 10 to 150 s (scale bar = 1 μm). (b) The etch rates rapidly increased in the initial stages of imprinting and then slowed. The etch depths were measured at the deepest point of the W shape. Several samples were measured to obtain the average and standard deviation of the etch depths. (c) Schematic of three stages of chemical imprinting on GaAs. At the beginning, etching starts from the edge of the contact 27 ACS Paragon Plus Environment


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area. As the imprinting time increased, the flat etched surface morphology becomes W-shaped, suggesting location-dependent non-uniform chemical etching. This is due to the different mass transport rates (reactant and byproducts) for metal-assisted chemical etching at the edges and centers of the GaAs/stamp interface.

Figure 5. (a) A complex alphabetic array pattern fabricated as a stamp. Photographs were taken using an optical microscope (approximate size of 1 cm × 1 cm). The 3D stamp was fabricated on an Si substrate using dry-etching (RIE), polymerization (C4F8), and metal deposition (Cr/Au). The inset shows a 1-μm square pillar array that shows the stamp features. (b) Mirror symmetric features are clearly imprinted on the


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GaAs after chemical imprinting with the stamp. The inset shows the hole arrays imprinted in the GaAs. (b-1)–(b-3) Enlarged hole arrays imprinted in the GaAs showing fairly consistent results across the area: the letters (1) “A,” (2) “H,” and (3) “Y” (scale bars in a, b = 2 mm, inset = 2 μm, b-1–b-6 = 50 μm).

Figure 6. (a–c) A series of photographs showing the recyclability (2nd to 4th use) of the stamp for consecutive chemical imprinting using a single stamp with 1 cm × 1 cm scale. Some portions of the stamp were not imprinted at the 3rd attempt because of the lack of flatness between the stamp and the GaAs in the laboratory environment. On the 4th attempt, the entire stamp was clearly imprinted on the GaAs, suggesting



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that the stamp itself was robust and that the incomplete contact was an engineering issue. (d–f) A series of SEM images showing the selected location of alphabetic array after the (d) 2nd, (e) 4th, and (f) 11th imprinting attempt of the GaAs using a single stamp (scale bars in a–c = 2 mm, d–f = 20 μm).


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AUTHOR INFORMATION

Corresponding Author Jungwoo Oh: [email protected]

Author Contributions K. Kim, B. Ki and J. Oh developed the original ideas. K. Kim and J. Oh contributed to the paper writing. K. Kim carried out most of the experimental work. K. Choi and S. Lee assisted with some experiments and data analysis.

Notes The authors declare no competing financial interest.

ACKNOWLEDGMENT This research was supported by the MSIT (Ministry of Science and ICT), Korea, under the “ICT Consilience Creative Program” (IITP-2018-2017-0-01015) supervised by the IITP (Institute for Information & communications Technology Promotion). This research was also supported by Basic Science Research Program through the 31 ACS Paragon Plus Environment


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National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science, and Technology (NRF-2016R1D1A1A09918647).

Supporting Information The Supporting Information is available free of charge on the ACS Publications websites at DOI: SEM images, AFM line scan data, photographs, optical microscope images, EDS mapping images, TOF-SIMS analysis, photograph of the prototype chemical imprinting equipment, and SEM images of the Si-based stamp.

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