NANO LETTERS
Resonance Tunneling Diode Structures on CdTe Nanowires Made by Conductive AFM
2004 Vol. 4, No. 9 1637-1641
Susheng Tan,† Zhiyong Tang,‡ Xiaorong Liang,†,⊥ and Nicholas A. Kotov*,‡,§,| Department of Chemistry, Oklahoma State UniVersity, Stillwater, Oklahoma 74078, and Departments of Chemical Engineering, Materials Science, and Biomedical Engineering, UniVersity of Michigan, Ann Arbor, Michigan 48109-2136 Received May 26, 2004; Revised Manuscript Received July 10, 2004
ABSTRACT Variation of band gap across the nanowire length would be an exceptionally attractive property for the fabrication of on-nanowire devices such as resonance tunneling diodes (RTD). Band gap variation can be achieved by selective thinning of semiconductor wires by scanning probe lithography (SPL) technique. The external bias applied to a conductive AFM tip during scanning of CdTe nanowires was chosen so as to exceed the threshold of electric field-assisted evaporation of CdTe, estimated to be 5.5 V. Relatively high external voltages of 10−11 V cause fast and complete disintegration of a nanowire portion under the tip. In this way the nanowire can be cut to a desired length. Selection of a voltage between 5.5 and 10 V allows one to control the speed of CdTe evaporation. Thus, one can modulate the thickness of the semiconductor with angstrom scale precision along the nanowire length. Smaller diameter of the nanowire results in increase of quantum confinement in selected areas. The double barrier quantum well valence band profile necessary for the manufacturing of RTD Esaki diodes was demonstrated.
Introduction. To date, virtually all nanoelectronic devices have been made by precise positioning of a nanoparticle, nanowire (NW), or carbon nanotube between electrodes.1-3 With respect to NWs, prototype devices such as transistors, gates, and others have been made on the basis of their junctions. For instance, when the top wire has n-type and the lower wire has p-type conductivity, the point of contact acts as a diode.4,5 If one could avoid the step of physically moving two or more NWs with respect to each other and with respect to the electrodes, a significant decrease in the fault rate and an improvement in reproducibility of the device characteristics can be achieved. One of the alternatives to junction-based devices is the fabrication of functionally different areas on a single NW. Among different means of altering electrical characteristics of a quantum-confined semiconductor, the most straightforward approaches are surface modification and/or nanomachining of designated areas. In-situ fabrication of p-n junctions and functionally analogous structures may greatly simplify device production, especially when used in conjunction with lithography and selective growth. * Corresponding author. † Department of Chemistry, Oklahoma State University. ‡ Department of Chemical Engineering, University of Michigan. § Department of Materials Science, University of Michigan. | Department of Biomedical Engineering, University of Michigan. ⊥ Current address: Department of Chemistry, Purdue University, West Lafayette, IN 47907. 10.1021/nl0492077 CCC: $27.50 Published on Web 08/04/2004
© 2004 American Chemical Society
Different nanolithographic tools can be used for selective functionalization of NWs. Electron beam lithography6-8 or X-ray lithography6,9,10 dominated the field of ultrahigh resolution patterning in the past. With rapid development of scanning probe microscopy (SPM), nanolithography using SPM tips, also known as scanning probe lithography (SPL), is becoming a viable competitor to the other two techniques. It is capable of directly producing three-dimensional structures at the nanometer scale under normal temperature and atmospheric pressure, which is particularly attractive for device fabrication.11-14 The arsenal of surface modification tools in SPL includes electrons emitted from an SPM tip and simple mechanical force resulting in nanoindentation and scratching of the substrate. SPL was successfully employed for creation of organic, biological, and inorganic (metal, semiconductor) nanostructures, such as dots, stripes, gratings, gaps, contacts, etc.15 There also have been some reports on fabricating NWs with SPL16-18 and a few studies on fabrication of insulating or tunneling gaps between them. Recently, Li et al. reported that silver NWs can be cut or machined to desirable sizes by nanoindentation.19 However, no studies on manufacturing NWs with alternative thickness variations along the wires that are necessary for on-wire devices have been reported. For instance, thickness variations are needed for the fabrication of the so-called Esaki diodes,20,21 displaying a region of negative resistance, i.e., a
segment of current-voltage curve where the forward current decreases with increasing bias. In this study, a real-time SPL was used to make gaps and thin blocks on CdTe NWs using a conductive atomic force microscope (C-AFM) setup. This makes possible the simultaneous acquisition of dimensionality data (thickness) and performance of lithographic operations, which is exceptionally convenient for device manufacturing. Experimental Section. CdTe NWs were prepared by spontaneous assembly of NPs as described in detail elsewhere.22 Briefly, 5 mL of methanol was added into 5 mL 0.2 mM of CdTe NPs ∼5 nm in diameter stabilized by thioglycolic acid.23,24 The mixture was centrifuged for 10 min at 5800 rpm. The precipitate was then redissolved in 5 mL deionized water with pH 10.0. After that, the reaction media was incubated for 3 days at 55 °C. During this period, the solution darkened, which indicated the formation of NWs. CdTe NWs obtained by this method were uniform in diameter but varied in length from 50 nm to several micrometers, being on average 1 micrometer in length. For the SPL experiments, an 8.6 × 10-6 mM solution of CdTe NWs was deposited onto arsenic-doped silicon wafer by spin-coating. The substrate was mounted on a steel sample puck using silver conductive adhesive. The thus obtained film was annealled at 100 °C for 20 min before AFM experiments. All SPL/AFM operations were carried out on a Multimode SPM with the NanoScope IIIa controller (Digital Instruments/ Veeco, Santa Barbara, CA). To enable C-AFM operations the SPM was equipped with a Quadrex extender and conductive application module. AFM lithography and imaging were done under ambient conditions (with a relative humidity of ∼30% at 25 °C) using a contact mode AFM with 20 nm Au-coated commercial Si3N4 cantilevers (MikroMasch USA, Portland, OR). Unless otherwise stated, all AFM measurements and/or AFM manipulations in this study were made under an applied force of 6 nN with activated z-feedback loop. The voltages were quoted referencing the polarity of the tip side. All the samples were grounded. Depending on the desirable effect, a bias from 0 to 12 V was applied to the tip, which caused cutting/thinning of the NWs. The tip voltage can be applied in either constant or sweeping mode. After SPL, 3∼5 different locations were chosen from which to acquire thickness data of the reduced heights, which were subsequently averaged. Standard methods of statistical analysis were applied to them to determine error bars. This was done for each voltage/time pair of experimental parameters used for SPL modification of CdTe. The presented images were the most representative among those obtained. In some cases, the y-scan direction was disabled in order to fabricate very narrow gaps on CdTe NWs. During the imaging phase, AFM was operated in the conventional scanning mode to generate the surface topographical images line-by-line at a very low applied load (usually < 6 nN). The images were obtained both before and after applying bias. Results and Discussion. Previous studies demonstrated that the C-AFM is a powerful tool that can provide direct 1638
information on surface conductivity, two-dimensional dopant profiling, and electronic states of nanoscale objects.23,25,26 For example, in our previous publication, C-AFM was used to evaluate the conductivity of silica-coated CdTe NWs.23 It was also established that the transversal charge transport from the AFM tip to the NW and then to the substrate involves mid band gap states of the quantum-confined semiconductor. As a part of this study, we also learned that it is possible to precisely machine CdTe NWs and produce band gap junctions and other structures relevant to nanoelectronics. The essence of the SPL process in CdTe under a C-AFM tip is most likely field-assisted evaporation of the material. Since the gap between the poles in C-AFM is very small, the fields can reach as high as 109 V/m, even when the applied voltage (bias) is rather small-in the range of few volts. Electrons emitted from the tip and accelerated by the electrical field can knock out the atoms and/or heat the semiconductor. This results in vaporization of CdTe in a very limited area under the AFM tip. The evidence of the fieldassisted evaporation can be clearly seen from the chemical composition of AFM tips after lithographic procedure (Supporting Information, Figure S1). Both the EDAX spectrum and element mapping clearly show the presence of Cd all over the AFM cantilever, even in distances as far as 80 µm from the tip, which can happen only via gas-phase transfer. As well, AFM images remain sharp, even after extensive machining, which indicates that CdTe was dispersed away rather than being deposited on the tip as a clump.15 Note that field-assisted evaporation of CdTe may also result in some chemical modification of the NW. This effect can be used for doping a certain area. The focus of this study, however, is mainly the topological changes in the NW and the electronic effects expected from that. One of the simplest demonstrations of C-AFM SPL on CdTe NWs, can be done when AFM scanning is fixed in the horizontal, x direction, so the AFM tip only moves back and forth between left and right scanning limits, so there is no movement in the y-direction (besides random drift of the piezoelectric head). The pathway of the probe crosses a CdTe NW lying approximately perpendicular to the tip trajectory. Without an external voltage applied to the C-AFM probe, the wire remains intact (Figure 1A, B), even after repeated scans. The force load on the cantilever was kept intentionally very low, i.e. at < 6 nN, to make sure that no mechanical damage was done to the NW. When a bias of 10 V was applied, during the scan, the height profiles and AFM images demonstrated drastic changes in the NW (Figure 1C, D). Here the experiment was setup so that the bias was applied on the NWs only when the tip moves over it. A brief 10 V pulse with a duration of 8 ms was programmed to be turned on at the point where the CdTe NWs lying. After several scans, the voltage pulse was switched off and normal contact mode imaging was resumed. As a result of that, an obvious gap (Figure 1B and D) was created in the intended position of CdTe NW (Figure 1A and C) after 10 min of voltage pulse machining. The gap width of 25 nm was created. It correlates very well with the 20 nm diameter of the C-AFM tip used here. The depth of the gap is equal to the NW Nano Lett., Vol. 4, No. 9, 2004
Figure 1. Height images and line profiles along the longitudinal direction of CdTe NW: (A), (B) before and (C) and (D) after nanomachining by the C-AFM lithography.
Figure 2. Bias dependence of thinning of CdTe NWs. (A) 2-D and (B) 3-D height image.
diameter. So, the net result of the described process was cutting the NW into two pieces. The voltage applied to the tip during scan can be controlled as one of the experimental parameters. By varying the bias during scanning in the x direction (perpendicular to the NW), its effect on the resulting height of CdTe NWs can be examined. In this case, one can allow the movement along the y direction parallel to the NW, to make the experiment continuous. It also eliminates possible artifacts due to incidental variation in tunneling characteristics in multiple AFM approaches to the scanned object. No changes in NW topology were observed under voltage pulses of 4 V or lower. As the bias increased from 5 to 10 V, the height decreased gradually (Figure 2A and B). For the 7 nm CdTe NW, the lower limit for the voltage necessary to remove the CdTe materials, i.e. threshold voltage, was about 5.5 V. As one may expect, the threshold voltage depends slightly on the diameter of CdTe NWs. The larger the NW diameter, the higher is the threshold voltage. For instance, for a NW with a diameter of 10 nm, the threshold voltage was 9 V. To compare these data with SPM modification of other onedimensional structures, it takes 6.5 V to cut an individual Nano Lett., Vol. 4, No. 9, 2004
carbon nanotube,16 and it requires 19 V to create a similar gap on an Au strip.27 No data on SPM lithography of other semiconductor NWs had been reported so far. The cutting process can be finished in less than one minute when the applied voltage was 11 V. Once the threshold is reached, the rate of the CdTe removal correlates very well with the bias magnitude. This means that one can not only cut but also gradually reduce the diameter of the NW to a desirable value by choosing appropriate combination of the bias and time it is applied to a selected area. Indeed, under a bias voltage of 7 V, two thinned sections of 2 and 4 nm thick along the same wire of an average thickness of 6.5 nm were fabricated (Figure 3). In this case, the AFM tip was first placed and scanned on the one spot of the CdTe NW. As soon as a profile with 2 nm depth was created, the bias voltage was switched off and then the tip was moved to the second position along the CdTe NW. The external bias was turned on again and the second portion with a depth of 4 nm was produced after scanning for 5 min. Because of the effect of the tip shape, the machined sessions were V-shaped with a gap in the top of around 100 nm. The controlled thinning process on CdTe NWs offers great opportunity for the fabrication of diode blocks on the same 1639
Figure 3. Height images (A), line profile (B), and schematics of conduction band energy (C) of a thinned CdTe nanowire. Under controlled bias voltage of 7 V, two thinned sections of 2 mm and 4 mm thick along the same wire of an average thickness of 6.5 mm were obtained.
NW. Following a similar procedure, a thin block of 200 nm wide and only 2 nm thick was successfully created on a 10 nm CdTe NW under a bias voltage of 9 V (Figure 4). Furthermore, it is possible to create a sequence of periodic blocks with different thicknesses on single NWs (Figure 5). Two neighboring blocks of 3.5 and 6.5 nm high were made by thinning an 8.5 nm CdTe NW under a bias voltage of 8 V with bias pulse durations of 10 and 5 min, respectively (Figure 5). Since there is intrinsic dependence of the NW band gap on its diameter, nanomachining translates into the possibility of band-gap engineering. Thus, C-AFM may be used for manufacturing a prototype of quantum tunneling devices on nanostructures, such as the Esaki diodes well-known in the solid-state physics research community. Since the first report about such device in 1958,28 the Esaki diode has attracted great attention due to its negative differential resistance with potential applications in a variety of electronic circuits.29 Our new technique opens the door to the fabrication of nanoscale resonance tunneling diodes (RTD), one of the most interesting devices in the area of nanoelectronics. As one can see from Figure 3C, the energy profile for a conduction band along the NW is identical to the so-called double barrier RTDs.30,31 These prototype quantum devices are currently made only from thin semiconductor films deposited in a certain sequence to produce a quantum well sandwiched between two layers of different materials with higher bandgap energy.32 Tunneling through the two barriers and the quantum well gives rise to the area of negative resistance characteristic for Esaki diodes. After some optimization of 1640
Figure 4. Height images of CdTe nanowires before (A) and after (B) nanomachining by using the conductive AFM lithography. (C) is the line profile along the longitude direction of the modified CdTe nanowire. A block of thinned CdTe nanowire of 200 nm wide and only 2 nm thick was successfully created under a bias voltage of 9 V.
Figure 5. Height image (A) and line profile (B) of a machined CdTe nanowire. Two neighboring blocks were thinned to 3.5 and 6.5 nm, respectively, under a bias voltage of 8 V for working time of 10 and 5 min, respectively.
the distances between the notches and their depths in CdTe NW, one can expect to see similar effects measuring the lateral conductivity in the prototype device in Figure 3A. Additionally, some other configurations with similar Esaki diode characteristics can be made when an n-type CdTe NW with band gap modulations is transferred onto a p-type substrate, creating multiple p-n junctions. To verify band-gap variations along the sculpted NW, tunneling spectroscopic measurements were performed on the three blocks with thickness of 3.5, 6.5, and 8.5 nm, respectively, which were fabricated by C-AFM (Figure 6). All I-V plots (Figure 6A) were recorded by placing the C-AFM tip on the top of the fabricated blocks similarly to the previous study of CdTe NW.23 By differentiating the I-V Nano Lett., Vol. 4, No. 9, 2004
chemical composition of AFM tips after lithographic procedure. This material is available free of charge via the Internet at http://pubs.acs.org. References
Figure 6. Electronic properties of the CdTe NWs. (A) I-V plots obtained by C-AFM on three fabricated blocks with different thickness in one NW (see Figure 5). (B) The corresponding conductance, (dI/dV); the curves were offset vertically for clarity.
curves, complex conductance curves can be obtained (Figure 6B). It is known that tunneling conductance can be considered to be proportional to the electronic local density of states (LDOS) of the semiconductor. In the relevant voltage range, different LDOS were revealed. If the strongest peaks are considered as markers for band gap boundaries, then the band gap can be calculated to be 1.9, 2.3, and 3.5 eV for the NW blocks of 8.5, 6.5, and 3.5 nm in diameter, respectively. Photoluminescence measurements of CdTe NWs suspended in water give a lower limit of the band gap of 1.9 V,23 which coincides very well with our findings from C-AFM. Recent theoretical calculations indicate that a single CdTe spherical quantum dot can have several optical transitions (band structure) and the positions of these transition bands shift to higher energy levels with the decrease of radius R of the CdTe nanospheres,33 as expected from the foundations of the quantum confinement effect. In summary, SPM lithography was applied to manufacturing of on-wire devices from CdTe NWs. CdTe as a semiconductor is convenient for this technique because it exhibits a low threshold voltage for field-assisted evaporation under the tip. A prototype Esaki diode was fabricated by sculpting NW with C-AFM lithography. RTD with double barrier quantum well structures was produced by varying NW thickness in a desirable pattern from 3.5 to 8.5 nm. The real time monitoring of the nanolithography provides a precise control of the depth of the thinned blocks and the size of the gaps. Complete separation of different parts of the NW is also possible to create a single electron tunnel junctions. In perspective, NPs of different materials can be inserted by simple self-assembly techniques.34-36 Acknowledgment. N.A.K. thanks NSF-CAREER, NSFBiophotonics, NIH-NASA, AFOSR, and OCAST for financial support of this project. This research was also partially supported by NSF grant, EPS-0132354. Supporting Information Available: Figure S1 representing evidence of the field-assisted evaporation from the Nano Lett., Vol. 4, No. 9, 2004
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