Letter pubs.acs.org/NanoLett
Rolled-up nanomembranes as compact 3D architectures for field effect transistors and fluidic sensing applications Daniel Grimm,†,‡,* Carlos Cesar Bof Bufon,†,§ Christoph Deneke,†,§ Paola Atkinson,†,⊥ Dominic J. Thurmer,† Franziska Schaff̈ el,∥ Sandeep Gorantla,† Alicja Bachmatiuk,† and Oliver G. Schmidt†,‡,* †
Institute for Integrative Nanosciences, IFW Dresden, Helmholtzstrasse 20, 01069 Dresden, Germany Material Systems for Nanoelectronics, Chemnitz Technical University, Reichenhainer Strasse 70, 09107 Chemnitz, Germany ∥ Department of Materials, University of Oxford, Parks Road, Oxford OX13PH, U.K. ‡
S Supporting Information *
ABSTRACT: We fabricate inorganic thin film transistors with bending radii of less than 5 μm maintaining their high electronic performance with on−off ratios of more than 105 and subthreshold swings of 160 mV/dec. The fabrication technology relies on the roll-up of highly strained semiconducting nanomembranes, which compacts planar transistors into three-dimensional tubular architectures opening intriguing potential for microfluidic applications. Our technique probes the ultimate limit for the bending radius of high performance thin film transistors. KEYWORDS: Rolled-up electronic device, flexible metal-oxide field effect transistor, indium gallium arsenide, microfluidics, solvent sensing eformable thin film devices are widely used in flexible large-area electronics including artificial skins,1 solar 2 cells, and electronic paper displays3,4 as well as pressure5 and magnetic6 sensors. Organic semiconductors2,3,5,7,8 and thin films of otherwise rigid semiconducting materials9−14 have been investigated for such applications. The flexibility of these electronic devices allows their integration into circuits on irregular surfaces or with unconventional shapes suitable, for instance, for microfluidic applications. However, reliable device operation under tight folding conditions such as crumpling and bending over sharp edges remains a major challenge. The minimum bending radius of an electronic circuit is therefore a crucial parameter, and it is of great importance to explore the fundamental mechanical constraints of flexible yet fully functional devices. Although it has been demonstrated that thinner substrate supports lead to transistors functioning with bending radii well below 1 mm, compressing the devices to a radius less than 100 μm causes severe degradation or even irreversible failure of their electronic performance.5 Motivated by this challenge, we have developed a technique to fabricate free-standing inorganic thin film transistors (TFTs) without flexible host substrates that withstand ultrasmall bending radii of 5 μm without suffering any structural damage. The freestanding nanomembrane based transistors rely on differentially strained single crystalline semiconductors that roll-up into a tubular geometry once released from their host substrate by selective underetching.15,16 In this way, large area devices are compacted to footprints orders of magnitude smaller than the original planar structure. The fabricated three-dimensional devices naturally offer a microfluidic channel which we explore
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© 2012 American Chemical Society
for chemical sensing. Recently, a variety of rolled-up electronic devices have been fabricated ranging from ultracompact capacitors,17 resistors18 and curved two-dimensional electron gases19,20 to molecular21 and superconducting22 heterojunctions. However, the crucial electronic device in large scale integrated circuitry, the field effect transistor, has not yet been addressed by this technique. Realizing rolled-upfield effect transistors (RUFETs) implies that high performance electronics might be incorporated into ultracompact three-dimensional architectures both for on-chip main stream Si technologies as well as for off-chip autonomous microsystems in the not too distant future. The single-crystalline III−V semiconductors incorporated in the RUFETs are grown by molecular beam epitaxy, as reported elsewhere.23 This allows for precise strain-engineering by adjusting the structural composition. After in situ deoxidation under arsenic overpressure, a 200 nm thick GaAs buffer is grown on the semi-isolating GaAs (001) wafers, followed by 40 nm AlAs as a sacrificial layer. The simplest employed strained semiconducting nanomembrane multilayer consists of 20 nm In0.2Ga0.8As as a stressor, followed by 30 nm GaAs thin films with an n-doping of 3.5 × 1018 cm−3. As shown in Figure 1a, the fabrication process requires only conventional twodimensional lithography to pattern the detachable metal-oxide field effect transistors. The devices are isolated by a 50 nm deep etch in a sulphuric acid and hydrogen peroxide solution. The Received: October 23, 2012 Revised: December 13, 2012 Published: December 17, 2012 213
dx.doi.org/10.1021/nl303887b | Nano Lett. 2013, 13, 213−218
Nano Letters
Letter
Figure 1. Process flow for rolled-up TFTs. (a) Schematic fabrication of RUFETs by the roll-up of strained semiconducting nanomembranes. Strained single-crystalline GaAs and In0.2Ga0.8As (green) on top of AlAs layers (red) are patterned by standard 2D techniques: (i) Device isolation by shallow wet etching. (ii) Structuring planar TFT with Ohmic contacts (yellow) and gate electrodes (blue). (iii) Deep-etching allows access to the sacrificial AlAs layer. (iv−vi) Selective wet-etching of the underlying AlAs layer releases the strained layer stack into a 3D tubular shape. (b) Optical image of unrolled planar (right) and RUFET devices (left). Insets: close-ups of the channel region after rapid thermal annealing. (c) SEM overview of millimeter long tubes, partly color-coded. The red arrows indicate the rolling directions.
diluted HCl (Figure 1b; Figure S4−S6, Supporting Information). The planar TFT with a device width of 400 μm is compacted into a tubular architecture with 10 windings and outer radius of around 6.5 μm, representing a minimum bending radius of 5.3 μm (see eq S4, Supporting Information). The top rolled-up layer of the inner winding contacts the released bottom surface. The electrical insulation between adjacent layers in the tube is guaranteed by the top dielectric film. The scanning electron micrograph (SEM) shows an overview of two free-standing and millimeter long tubes with 12 parallel RUFETs each (Figure 1c). By varying the strain conditions of the dielectric and electrodes, we fabricated RUFETs with minimum bending radii between 4 and 9 μm (Figure S3, Supporting Information). A more detailed description of the fabrication process is provided in the Supporting Information. For structural investigations by transmission electron microscopy (TEM) we prepared lamellae along the tube axis as indicated by the dashed red line in Figure 1b. The overview of the upper part of a RUFET demonstrates the high quality of the gate region (Figure 2a). The tight contact between
substrate leakage between adjacent isolated devices is below the setup detection limit (
