Scalable Approach for Vertical Device Integration of Epitaxial

Mar 26, 2009 - In this letter, we demonstrate the simultaneous vertical integration of self-contacting and highly oriented nanowires (NWs) into airbri...
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NANO LETTERS

Scalable Approach for Vertical Device Integration of Epitaxial Nanowires

2009 Vol. 9, No. 5 1830-1834

A. Lugstein,* M. Steinmair, C. Henkel, and E. Bertagnolli Institute for Solid State Electronics, Vienna UniVersity of Technology, Floragasse 7, A-1040 Vienna, Austria Received December 15, 2008; Revised Manuscript Received March 2, 2009

ABSTRACT In this letter, we demonstrate the simultaneous vertical integration of self-contacting and highly oriented nanowires (NWs) into airbridge structures, which have been developed into surround gated metal oxide semiconductor field effect transistors (MOSFETs). With the use of conventional photolithography, reactive ion etching (RIE), and low pressure chemical vapor deposition, a suspended vertical NW architecture is formed on a silicon on insulator (SOI) substrate where the nanodevice will later be fabricated on. The vapor-liquid-solid (VLS) grown Si-NWs are contacted to prepatterned airbridges by a self-aligned process, and there is no need for postgrowth NW assembly or alignment. Such vertical NW architecture can be easily integrated into existing ICs processes opening the path to a new generation of nonconventional nano devices. To demonstrate the potential of this method, surround gated vertical MOSFETs have been fabricated with a highly simplified integration scheme combining top-down and bottom-up approaches, but in the same way, one can think about the realization of integrated nano sensors on the industrial scale.

Since the emergence of nanostructures as technologically relevant materials, bottom-up fabrication strategies and selfassembly methods have become increasingly attractive. Recently, nanowire (NW) devices have received considerable attention as regards their use in integrated nanoscale electronics,1-5 sensors,6-8 and photonic devices9-11 as well as for studying fundamental properties in small dimensions.12 In particular, epitaxially grown Si-NWs have been identified as promising candidates for post-CMOS logic elements because of their potential compatibility with existing semiconductor technology.13 In many of these demonstrations, NWs were assembled after growth into ordered arrays by alignment aided by fluid flow or by applying electric fields.14,15 In other cases, electrical contacts were defined with electron beam lithography on individual nanowires randomly distributed on the substrate.16 Although connecting electrodes to nanowires one at a time contributes to exploring novel nanowire device applications, it imposes limitations on nanofabrication at technologically relevant scales. Thus, a massively parallel technique is needed to allow bridging of bottom-up fabricated NWs between electrodes, and combining assembly with nanowire growth is attractive when industrial scaling is the goal. Further, growing NWs in standing positions is another issue to achieve vertical NW FET 17-20 and/or devices with extreme packing density.21-25 Our scalable approach for such parallel and vertical integration of self-contacting NWs is schematically described in Figure 1a-d. By combining well-known top-down * Corresponding author. E-mail: [email protected]. 10.1021/nl803776a CCC: $40.75 Published on Web 03/26/2009

 2009 American Chemical Society

semiconductor processing techniques and epitaxial Si-NW growth with control of the NW location and orientation, we circumvent the problem of handling and positioning nanometer-sized objects that arises in the conventional pick-andplace approach.4,26 The NWs are grown where they need to be with a minimum number of processing steps. The starting materials used were pieces of a silicon on insulator (SOI) wafer (Figure 1a), which have a 2 µm thick device layer on top of a 2 µm thick thermally grown buried oxide (BOX). Both the device layer (Si-110) and the substrate (Si-111) are p-type with a boron doping of >3.1018 cm-3. First of all, a freestanding cantilever is structured by photolithography and RIE. The BOX is partially removed by wet etching with buffered hydrofluoric acid (BHF) followed by a water rinse to guarantee a hydrogen terminated Si surface (Figure 1b). Next, gold colloids with a diameter of 80 nm in aqueous solution are placed selectively below the now freestanding Si cantilever by dielectrophoresis (Figure 1c). Subsequently, Si-NWs are synthesized by VLS growth in a hot wall chemical vapor deposition reactor using SiH4 as the precursor (Figure 1d).27 The transmission electron microscopy (TEM) image in Figure 2a shows such a grown single crystalline Si-NW with the catalytic Au nanoparticle cap. The NWs are typically 100 nm thick, and the lack of tapering suggested that radial growth was negligible. The HRTEM micrograph of the crystalline core clearly shows the Si (111) atomic planes (separation 3.14 Å) perpendicular to the NW axis. The reciprocal lattice peaks, which were obtained from a 2D Fourier transform of the lattice resolved image, proves that

Figure 1. Schematic process flow illustrating the methods used for vertical integration of self-contacting Si-NWs. (a) SOI substrate with a heavily p-doped device and handle layer. (b) Freestanding cantilever on SOI wafer structured by photolithography and RIE. (c) Selective deposition of the catalytic Au particle below the freestanding Si cantilever by dielectrophoresis from an aqueous solution of Au colloids with a diameter of 80 nm. (d) Suspended Si-NW device ready to perform a two probe current-voltage (I/V) measurement by applying a voltage sweep to the top contact and simultaneously reading the current flowing in the circuit, while the SOI substrate wafer was held at a constant potential.

Figure 2. (a) TEM and HRTEM image of a Si-NW with the catalytic Au nanoparticle on top. The HRTEM image and the diffraction pattern confirm the 〈111〉 growth direction and the single crystalline nature of the Si-NW. (b) Cross-sectional low-magnification, brightfield TEM image of an epitaxial Si-NW and the HRTEM image of the substrate-NW interface region.

the growth axes is 〈111〉 with vertical {112} facets.28 The TEM image in Figure 2b shows the interface region of SiNWs grown epitaxially on the Si (111) substrate. The dashed line in the high resolution TEM (HRTEM) image represents the edge of the substrate-NW interface. As can be seen, no grain boundaries, abrupt interfaces, or misfit dislocations were observed in this region, and the interface appears to be coherent, unstrained, and epitaxial silicon to silicon. To achieve the suspended NW architecture as shown in Figure 1d, the synthesis parameters were chosen so that the [111] oriented Si-NWs grow perpendicular to the SOI substrate. We fabricated 70 suspended devices in parallel on a chip as shown in Figure 3a with no restrictions to further scaling. An example of a device with only a single NW is shown in the inset of Figure 3a. If a reliable connection can form during nanowire growth, such clamped NW architectures may become increasingly attractive for sensors and other vertical device applications requiring electrical conduction. It was already previously Nano Lett., Vol. 9, No. 5, 2009

demonstrated that epitaxially grown semiconductor nanowires make good electrical and mechanical connections to the substrate.29-31 The total resistance of these suspended SiNW devices, i.e., from the top contact to the substrate, can easily be measured by a two-probe method as schematically shown in Figure 1d. Such measurements comprise two parts: the intrinsic resistance of the Si-NW and the contact resistance between the Si-NW and the electrodes. To eliminate the contribution of contact resistance, separate fourprobe measurements on individual NWs on an isolating sample with planar contacts were carried out revealing that the intrinsic resistivity of such a single Si-NW is about FNW ) 20 Ω cm (see Supporting Information). The resistance of the Ti/Au contacts to this type of wires was calculated to be about 2,5 GΩ. Moreover, gate-dependent current versus bias voltage measurement of separately prepared FETs with back gate geometry have shown that the VLS grown Si-NWs exhibit a field effect response characteristic of a p-type semiconductor with a rather low mobility of about 1,5 cm2 1831

Figure 3. (a) SEM image showing a proof-of-concept demonstration of Si-NW integration into arrays on 70 prefabricated electrode configurations. The inset shows a single Si-NW growing vertically from the (111)-oriented SOI handle wafer face toward the opposing Si cantilever face leading to a self-aligned contact formation. (b) Linear and semilog plot (in the inset) of the I/V characteristic of the single Si-NW grown vertically from the (111)-oriented SOI handle wafer face toward the opposing Si cantilever. The measurement was performed by applying a voltage to top contact, while the SOI substrate wafer was held at a constant potential.

Figure 4. Schematic of the surround gated Si-NW FET structure. The channel of the FET is generated via VLS Si-NW synthesis with self-aligned contact formation. Gate dielectric and metal formation was completed by first depositing a 30 nm thick Al2O3 layer on the entire device using ALD. The Pt wrapped around the gate electrode was deposited again by ALD and structured by photolithography and wet etching with aqua regia. The gate length is controlled by the BOX layer thickness of the origin SOI wafer.

V-1 s-1. The p-type behavior is the common observation in field-effect measurements of Si-NWs without intentional doping32-34 and may be due to the Au catalyst.35 To characterize the overall electrical properties of our suspended Si-NW device, we performed current-voltage (I/ V) measurements by applying a voltage sweep from -10 to 10 V to the top contact and simultaneously reading the current flowing in the circuit, while the SOI substrate wafer was held at a constant potential. Figure 1d shows a schematic of the typical two-terminal I/V measurement setup. The measurement reveals a strong rectifying behavior with a 2 orders of magnitude decrease in current at positive voltages (see inset of Figure 3b). The rectifying behavior was expected as there are two different contacts to the Si-NW. Combining electrical measurements and HRTEM investigations, we proposed an epitaxial contact between the heavily doped p-Si substrate and the unintentionally low p-doped NW. The nature of the connection of the impinging nanowire to the opposing Si plane is expected to be different from that of the epitaxial plane on the base of the NW. We suppose that a Schottky type contact occurs when the Si-NW with the Au droplet atop impinges the heavily p-doped cantilever. This Au/Si Schottky contact may dominate the I-V behavior, which will lead to the asymmetric electrical behavior. 1832

However, the total resistance of the suspended Si-NW extracted from I/V measurements comprises resistance of the NWs, contact resistance between the NW and the Si electrodes, and the resistance between the electrodes and the probe needles. For the heavily doped electrode regions, the contribution of resistance between the electrodes and the probes was found to be negligible. Assuming the resistivity of the Si-NW as FNW ) 20 Ωcm, the resistance of a NW of length of LNW ) 2 µm, and a cross-section area of ANW ) 7.9 × 10-11 cm2 (ØNW ) 100 nm) is given as follows: RNW ) FNW × LNW /ANW ) 50.5 MΩ

(1)

The total resistance of the suspended NW structure extracted from linear regime I/V measurements was calculated to be Rtot) 120 MΩ for negative voltages. Subtracting the NW resistance RNW from the total resistance Rtot, we calculated the contact resistance RC to be 35 MΩ. Therefore, the calculated contact resistivity of 2.7 × 10-3 Ωcm2 reflects more than 2 orders of magnitude improvement than that of our planar Ti/Au contacts with a contact resistivity of 1.5 Ωcm2 (see Supporting Information). However, the two contacts of the NW to the electrodes are not expected to be identical in performance. It is expected that VLS growth of Si-NWs leads to a better contact at the root of the NW as compared to the impinging end.36 Comparing both sweep directions when the voltage at the top contact is varied from negative to positive values and vice versa, we observe a hysteresis. This behavior is indicative of charge-trapping states, which may originate from the large number of surface defects, dangling bonds, and surface charges. As the suspended NWs exhibit a high surface-to-bulk ratio, the influence of the surface on the electrical conduction of semiconductors becomes significant. Therefore, it is well known that electrical conduction in a Si-NW with exposed surface is quite sensitive to charges trapped at the wire surface and exhibits hysteresis in current voltage characteristics.37,38 To demonstrate the potential of our approach for vertical device integration of epitaxial nanowires, we fabricated a Nano Lett., Vol. 9, No. 5, 2009

Figure 5. (a) Linear and semilog plot (inset) of IDS vs VDS with VGS ranging form -2 to 0 V in 0.2 V steps, from bottom to top. (b) Transconductance measurement for the vertical surround gated NW FET. The inset in b shows the semilog plot of the full IDS vs VGS spectrum at VDS) -1 V.

vertical surround gated Si-NW FET transistor utilizing fully CMOS-compatible technology, but in the same way one can think about CMOS compatible freestanding nanosensors on the industrial scale. Typically, Si-NW transistors have a horizontal, planar layout with either a top or back gate geometry.39,40,4 A surrounding gate geometry is the natural next step for advanced solid state nanoelectronic devices, yet with conventional top-down fabrication processing, it is not easy to realize such a device architecture with nanoscale features. Referring to our novel nanoarchitecture, a transistor gate can easily be wrapped around the suspended and vertical oriented NW. Such an all around gate will enable better electrostatic control as compared to other gate designs such as FinFET or trigate transistors and offers the potential to drive more current per device area than is possible in a conventional planar architecture.41 Furthermore, pushing the transistor geometry into the third dimension could result in ultrahigh transistor densities, and the application of vertical transistors in memory devices is especially sought after because of its potential in shrinking individual devices and its capability of multilevel memory structures threedimensionally. In detail, the surround gated NW FET was completed by first depositing a 30 nm thick Al2O3 layer on the entire device using atomic layer deposition (ALD). Subsequently, a Pt wrapped around gate electrode was deposited again by ALD and structured by photolithography and wet etching with aqua regia. Most significantly, this method is a parallel nanofabrication process, which does not require serial device fabrication. The previously VLS grown unintentionally low p-doped Si-NWs form the conducting channel connecting the heavily p-doped source and drain regions. The schematic of the final device with a single NW as channel is shown in Figure 4. Depending on the number of deposited Au colloids, the nanodevice will comprise single or multiple NWs finally bridging the gap between the Si plane and the cantilever. Most of the nanowire FETs reported in the literature typically use Schottky metal or silicide-source/drain contacts.42 Our process does not require any source and drain doping or silicide formation, thereby allowing a simple process without thermal annealing and overcomes the issue of aligning the gate, source, and drain contacts to the different doped segments of the nanowire. Thus, the device structure Nano Lett., Vol. 9, No. 5, 2009

can be formed with minimal process steps and without high temperature processes. The electrical transport measurements of the surround gated Si-NW FET were performed at room temperature and ambient pressure. Typical drain source current (IDS) versus drain source voltage (VDS) measurements at various gate voltages (VGS) exhibit ambipolar characteristics. The ambipolar IDS - VGS exhibits higher hole current than electron current. This is probably due to the Au/Si Schottky top contact, which will lead to asymmetric electrical contact behavior. For negative VDS, the IDS strongly depends on VGS. With increasing negative VGS values, the IDS increases markedly, whereas with increasing positive VGS, it is reduced. For positive VDS values, the gate voltage dependence of IDS is similar but less pronounced. The gate modulation efficiency was further investigated by plotting IDS - VGS for a variety of source-drain voltages (Figure 5b). For such a device, the threshold was found to be about 1 V. The Ion/Ioff current ratio and the subthreshold slope S was extracted by plotting IDS versus VGS on a logarithmic scale (inset of Figure 5b) and were found to be Ion/Ioff ) 103 and S ) 980 mV/decade at a VDS of -1 V. Additionally, no dependence of the scan rate or direction of VGS on the threshold voltage was observed in any of our devices. This behavior is indicative of a small number of charge-trapping states in or near the Si/Al2O3 gate oxide interface and illustrates that consistent, reproducible transistor performance can be achieved with minimal outside ambient dependence by embedding these devices in high-k dielectrics. In summary, a nanodevice fabrication method was described which is based on the combination of a bottom-up method and conventional top-down ICs manufacturing techniques. The VLS approach provides the epitaxial growth of vertical Si-NWs from individual Au catalysts and allows us to control the nanowire location and its orientation and thereby their alignment to the prepatterned nanoarchitecture. NWs are grown where the device is fabricated. Our method is scalable, i.e., this could be done on 6-8 inch wafers, and one can make many of them. We have shown that these suspended nanowire architectures can be developed into surround gated MOSFETs. In the demonstrated device, unintentionally p-doped Si-NWs 1833

grown epitaxially on a p-doped substrate were used as active channel material. These first-generation, unoptimized devices already show a gate-voltage-dependent current increase of more than 3 orders of magnitude. This technique in combination with other nanofabrication methods because of its scalability and ease of device fabrication goes beyond the current state-of-the-art assembly of NW based devices such as transistors and sensors and may be used as a platform for building more complex architectures such as hierarchical three-dimensional modules. Such three-dimensional device architectures could further increase transistor density through the additional ability to integrate multiple gates and source/drain connections along the length of these high aspect ratio channels. Although the nanowires were grown with Au colloids, similar results have been achieved using semiconductor industry friendly catalyst compositions such as Pt, Ti, or Al.43,44 The ability to synthesize longitudinal and coaxial heterostructures of NWs as well as other SOI wafers (orientation and doping) will allow additional design flexibility. Acknowledgment. This work is partly funded by the Austrian Science Fund (Project No. 18080-N07) and the Austrian Society for Micro- and Nanoelectronics (GMe). Technical Support by USTEM TU-Wien is gratefully acknowledged. Supporting Information Available: SEM image of a single nanowire with four-probe contact pads, I-V curves of the four-probe measurement, field effect measurements and calculation of the channel mobility, and drain current vs gate voltage curves in linear and logarithmic scales. This material is available free of charge via the Internet at http:// pubs.acs.org. References (1) Huang, Y; Duan, X.; Lauhon, L. J.; Kim, K. H.; Lieber, C. M. Science 2001, 294, 1313. (2) Thelander, C.; Nilsson, H. A.; Jensen, L. E.; Samuelson, L. Nano Lett. 2005, 5, 635. (3) Ng, H. T.; Han, J.; Yamada, T.; Nguyen, P.; Chen, Y. P.; Meyyappan, M. Nano Lett. 2004, 4, 1247. (4) Cui, Y.; Lieber, C. M. Science 2001, 291, 851. (5) Mathur, N. Nature (London) 2002, 419, 573. (6) Cui, Y.; Wei, Q.; Park, H.; Lieber, C. M. Science 2001, 293, 1289. (7) Hahm, J.; Lieber, C. M. Nano Lett. 2004, 4, 51. (8) Fan, Z.; Lu, J. G. Appl. Phys. Lett. 2005, 86, 123510. (9) Huang, M. H.; Mao, S.; Feick, H.; Yan, H.; Wu, Y.; Kind, H.; Weber, E.; Russo, R.; Yang, P. Science 2001, 292, 1897. (10) Barrelet, C. J.; Greytak, A. B.; Lieber, C. M. Nano Lett. 2004, 4, 1981. (11) K onenkamp, R.; Word, R. C.; Schlegel, C. Appl. Phys. Lett. 2004, 85, 6004.

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NL803776A

Nano Lett., Vol. 9, No. 5, 2009