Letter pubs.acs.org/NanoLett
Scaling and Graphical Transport-Map Analysis of Ambipolar Schottky-Barrier Thin-Film Transistors Based on a Parallel Array of Si Nanowires Dae-Young Jeon,†,‡ Sebastian Pregl,†,‡,§ So Jeong Park,†,‡ Larysa Baraban,§ Gianaurelio Cuniberti,§,‡ Thomas Mikolajick,†,‡,∥ and Walter M. Weber*,†,‡ †
Namlab gGmbH, Nöthnitzer Strasse 64, 01187 Dresden, Germany Center for Advancing Electronics Dresden (CfAED), §Institute for Materials Science and Max Bergmann Center of Biomaterials, and ∥ Chair for Nanoelectronic Materials, TU Dresden, 01062 Dresden, Germany
‡
S Supporting Information *
ABSTRACT: Si nanowire (Si-NW) based thin-film transistors (TFTs) have been considered as a promising candidate for nextgeneration flexible and wearable electronics as well as sensor applications with high performance. Here, we have fabricated ambipolar Schottky-barrier (SB) TFTs consisting of a parallel array of Si-NWs and performed an in-depth study related to their electrical performance and operation mechanism through several electrical parameters extracted from the channel length scaling based method. Especially, the newly suggested current−voltage (I−V) contour map clearly elucidates the unique operation mechanism of the ambipolar SB-TFTs, governed by Schottky-junction between NiSi2 and Si-NW. Further, it reveals for the firsttime in SB based FETs the important internal electrostatic coupling between the channel and externally applied voltages. This work provides helpful information for the realization of practical circuits with ambipolar SB-TFTs that can be transferred to different substrate technologies and applications. KEYWORDS: Si nanowire, Schottky barrier, thin-film transistors, channel length scaling, current−voltage contour map
T
transistors (FET) show a very steep junction profile when combined with different metallic silicides (i.e., NixSiy, CoxSiy, PtxSiy, and PdxSiy).9,10 This allows a transistor operation giving high modulation without the need for source/drain (S/D) doping. Ambipolar current−voltage (I−V) characteristics are also obtained owing to their unique operation mechanism limited by SB condition near S/D.9,10 These can lead to a new device concept for future electronics such as reconfigurable transistors with electrically tuned polarity for complementary logic circuits.11−13 Moreover it was shown recently, that silicon nanowire SB FET arrays fabricated by the bottom-up technique can be implemented in the promising new application field of flexible electronics.14 However, although significant advance-
hin-film transistors (TFTs) based on a parallel array of bottom-up grown Si nanowire (Si-NW) have several promising advantages for the development of next-generation flexible and wearable electronics in the area of displays, touch screens, energy conversion, and sensors related to healthcare.1−4 For instance, the Si-NW array based TFTs can be fabricated on flexible/transparent plastic substrates at lowtemperatures with a considerable carrier mobility value, different from polycrystalline-Si TFTs requiring higher process temperatures or amorphous-Si and organic TFTs with comparatively low mobility values. There are also less instability and material degradation issues in Si-NW TFTs as compared to oxide based TFTs.5 In addition, enhanced functionality can be added to such systems since the Si-NW based transistors are ideal candidates for single-molecule and multiplexed sensing, owing to nanoscale channel diameter comparable to the Debye screening length.6−8 However, Schottky-barrier (SB) field-effect © XXXX American Chemical Society
Received: March 27, 2015 Revised: June 4, 2015
A
DOI: 10.1021/acs.nanolett.5b01188 Nano Lett. XXXX, XXX, XXX−XXX
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Nano Letters ment has been observed in the ambipolar SB-TFTs based on Si-NW,1,3,15,16 the important scaling properties and performance estimation have not been reported yet. In this Letter, ambipolar SB-TFTs consisting of a parallel array of bottom-up grown Si-NW have been fabricated and their electrical performance and operation principle were investigated in detail, through several electrical parameters extracted by I−V and capacitance−voltage (C−V) characterization. In particular, I−V and transconductance (gm) contour map were suggested for a better understanding of physical operation mechanism of the ambipolar SB-TFTs. For this study, ambipolar SB-TFTs were fabricated on Si/ SiO2 substrates (degenerately doped P-type Si/400 nm thermal SiO2) with a parallel array of undoped Si-NW aligned by contact printing method.15,16 Interdigitated S/D electrodes of Ni were defined by photolithography, and then, silicidation process at 500 °C for 30 s was carried out for the formation of an abrupt Schottky junction between NiSi2 and Si-NW near S/ D. The temperature can be also kept as low as 270 °C to induce the silicidation.17 There are approximately 103 Si-NWs in parallel with mean diameters of 20 nm. Typical NW lengths vary between 10 to 40 μm, and the Si-NWs surrounded by a SiO2 shell of ∼8 nm were covered by a 20 nm-thick Al2O3 deposited by ALD process as an insulating layer. Gate electrode is composed of 20 nm Ni/10 nm Pt. The designed channel length (on-mask Lm) ranged from 16 μm down to 4 μm. Figure 1 displays the schematic architecture of the fabricated
Figure 2. (a) Id vs Vg characteristics of the ambipolar SB-TFTs with Lm variation (4 to 16 μm). Devices are biased with small drain voltage, |Vd| = 50 mV. (b) Corresponding Cgc vs Vg characteristics obtained with the compensation of the gate-dependent offset-capacitance. A 50 mV small signal at 10 kHz was used for C−V measurements.
clearly show an ambipolar behavior of carrier transports. A Schottky barrier (SB) resulting from the NiSi2/Si heterojunction can induce both electron and hole injection from source, according to a bias condition of Vg. In the case of Vg < flat-band voltage (Vfb) for negative small Vd, the injection probability of hole carriers by tunneling through SB can be raised since the effective SB width (SB-Weff) for hole is reduced with decreasing Vg (see the schematic band-diagram in Supporting Information). On the contrary, the electron injection through SB can be increased at the condition of Vg > Vfb for small positive Vd. In addition, the estimated SB height (SB-H) for electron (qφBe ≈ 0.66 eV) is higher than that for hole (qφBh ≈ 0.46 eV)13 since the Fermi level of NiSi2 is closer to valence band of Si-NW. This can cause the asymmetric ambipolar tendency on the Id vs Vg curves. It should be also mentioned that there was no significant hysteresis behavior on the transfer curves of the ambipolar SB-TFTs (see Supporting Information). Moreover, corresponding gate-to-channel capacitance (Cgc) curves were obtained as shown in Figure 2b, after the compensation of the gate-dependent offset-capacitance originated in the particular structure of the device with Si-NWs (see Supporting Information). Total resistance (Rtot = Vd/Id at Vg = −5 V) of the ambipolar SB-TFTs, including the serial junction (Rsd) and channel resistance (Rch), was plotted with varying Lm as shown in Figure 3a. Interestingly, the nonlinear behavior was observed on Rtot vs Lm, this feature is strongly different from conventional Si transistors.18 A long Lm device has less probability of having SiNWs bridging between both S and D contacts as illustrated in the inset of Figure 3a since the Si-NW has a finite length in the
Figure 1. Schematic architecture illustrating the structure of fabricated ambipolar SB-TFTs and SEM image showing clearly a well-defined NiSi2/Si-NW interface. There are approximately 103 Si-NWs connected in parallel by contact printing method in a device, and a 20 nm-thick Al2O3 layer covers the Si-NW surrounded by a SiO2 shell (∼8 nm).
ambipolar SB-TFTs, as well as typical scanning electron microscope (SEM) image of a well-defined NiSi2/Si-NW interface, prior to Al2O3 deposition. More detailed information regarding the fabrication process and Si-NW growth method has been described in previous papers.15,16 The I−V and C−V characteristics were recorded using Keithley 4200 and Agilent B1505A measurement units. Drain current (Id) of the ambipolar SB-TFTs was measured as a function of gate voltage (Vg) with Lm variation (4 to 16 μm), in the small drain bias regime (|Vd| = 50 mV) where Vd does not affect mobile carrier concentration in the channel region, as shown in Figure 2a. The transfer curves of Id vs Vg B
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Figure 3. (a) Rtot vs Lm of the ambipolar SB-TFTs at Vg = −5 V, showing the nonlinear behavior, due to less probability of Si-NW obviously connected to both S and D in a longer length. (b) The linear relationship between Cgc and Lm at Vg = −5 V. ΔL of ∼2.5 μm was estimated from the best-fit (blue line) with eq 1.
range of 10 to 40 μm.15 Therefore, both Rch and Rsd can be increased exponentially as raising Lm, this induces the nonlinear tendency of Rtot with Lm. However, the Cgc vs Lm in Figure 3b showed a typical linear behavior like conventional Si transistors19 since even the interrupted Si-NW segments (blue one in the inset of Figure 3a), which are connected to S or D, can contribute to the capacitance value. The linear relationship between Cgc and Lm can provide the channel length reduction (ΔL) owing to mean NiSi2 length and typical variation during the fabrication process as compared to a designed structure. Indeed, Cgc can be given as Cgc = CoxWeff (Lm − ΔL)
Figure 4. (a) Rtot as a function of Lm = 4, 6, and 8 μm only, showing a linear tendency owing to higher probability of the Si-NW to be connected to both S and D in the relatively smaller length devices. (b) The gate bias-dependent Rsd extracted by eq 2 with ΔL of ∼2.5 μm. Gate voltage overdrive (Vgt = Vg − Vth) was used for a better accuracy after determination of threshold voltage (Vth) with constant current technique.21 The inset shows the fitted lines with eq 2 at different Vgt in the range from −2 to −3.9 V. (c) Maximum field effect mobility (μfe_max) vs effective channel length (Leff). The overestimated Cgc in a longer length device results in opposite trend of μfe_max vs Leff as compared to conventional Si transistors.
(1)
intersection point of the fitted lines (blue) at different gate voltage overdrive (Vgt) was not observed in Figure 4a and the inset of Figure 4b, in contrast with conventional Si transistors with a constant Rsd.18 The varying width of the SB in ambipolar SB-TFTs as modulated by changing Vg can be the origin of gate bias-dependent Rsd offset in the device. Therefore, the Rtot of the ambipolar SB-TFTs with Rsd(Vg) can be expressed by
where Cox and Weff denote the oxide capacitance per unit area and effective channel width, respectively. ΔL of ∼2.5 μm was estimated from the best-fit with eq 1 and the number of SiNWs connected to source or drain in a device was calculated as N ≈ 1.6 × 103 from the capacitance value with assumption of a perfectly surrounded gate (see Supporting Information). These values are comparable to those (∼3.0 μm and ∼1.0 × 103) from a statistical analysis using SEM in consideration of variation of nanowire diameters and assumptions regarding gate geometry. A linearity between Rtot and Lm can be still assumed for smaller length devices since there could be higher probability of the Si-NW connected to both S and D in the device group. Indeed, Figure 4a shows the Rtot is linearly proportional to Lm in the regime (Lm = 4, 6, and 8 μm) only. However, a common
R tot(Vg) =
ρch (Vg) Weff
(Lm − ΔL) + R sd(Vg)
(2)
where ρch is the channel sheet resistance. The Rsd depending on Vg was extracted using eq 2 and the previously assumed ΔL ≈ 2.5 μm in Figure 3b and is shown in Figure 4b. The extracted Rsd(Vg) is reduced as increasing |Vg| since the SB width of the C
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Figure 5. (a) Unique output characteristics and corresponding 3D surface plots of the ambipolar SB-TFTs (Lm = 6 μm). (b) Newly suggested I−V contour map for a better understanding of physical operation of the ambipolar SB-TFTs. Log(Id) was plotted as a function of Vd and Vg and color in the I−V map means the amplitude of log(Id). Hole and electron conduction regime can easily be separated by the dotted black line denoting a transition borderline. Moreover, TE, TFE, and FE dominant area can be estimated with blue, green, and red color, respectively.
ambipolar SB-TFTs is getting narrower at higher |Vg|, and this allows the increased carrier injection by tunneling. Furthermore, Bhandari et al. had investigated the Vg-dependent Rsd in another type of Schottky-barrier transistor.20 Figure 4c shows the maximum field effect mobility (μfe_max) as a function of effective channel length (Leff = Lm − ΔL). The μfe_max was deduced from the maximum transconductance (gm_max) and saturated Cgc (Csat) at high |Vg|, where a drift conduction can be assumed in the Si region, with following equation:18 μfe_max =
underestimated due to the overestimated Cgc. Moreover, one can note the μfe_max of ∼15 cm2/(V s) in these ambipolar SBTFTs is quite comparable to a state of the art oxide based TFT, as well as much higher than that of typical amorphous-Si and organic TFTs (∼1.0 cm2/(V s)).1,5 The electron and hole transport of the ambipolar SB-TFTs is mainly limited by the transmissibility through the SB according to the bias conditions of Vg, Vd, and Vs. This leads to unique output characteristics as shown in Figure 5a. For Vd > 0 and Vg > 0 in the right plot of Figure 5a, one can expect that there could be a transition from hole conduction to electron conduction for increasing Vg, while a typical output behavior like conventional p-type transistors was observed in the left plot with Vd < 0 and Vg < 0. The I−V contour map as shown in Figure 5b is suggested here as a novel presentation method to understand more easily these interesting output curves of the ambipolar SB-TFTs. The dotted black line in the I−V map distinguishes clearly between hole (left-hand side) and electron (right-hand side) conduction dominant regime. Indeed, a transition point from hole to electron transport along the arrow B-line, corresponding to the bias condition of the right plot in Figure 5a, was investigated unambiguously through the I−V map. On the contrary, the arrow A-line in the I−V map always
gm_max Leff 2 CsatVd
(3)
The μfe_max is degraded for increasing Leff. This result is contrary to conventional Si transistors, for which the mobility increases at long Leff due to the absence of short channel effects (SCEs).21 Interrupted SiNWs as illustrated schematically by the blue color Si-NW in Figure 4c, which are connected to S or D only, can still contribute to the Cgc value although they are not able to provide any Id. Therefore, the μfe_max of ∼15 cm2/(V s) in the shortest Leff can give more exact value of the ambipolar SB-TFTs since mobility in the longer device could be D
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In the case of Vd > 0, the same equation through similar procedure was also derived with eq 6 (see Supporting Information). Indeed, the value of dVd/dVg = 2 in eq 6 was perfectly consistent with the slope (∼2) of the transition border in the experimentally obtained I−V map. Moreover, the Vc of ∼0.41 V was estimated from the intersection point between the borderline and the Y-axis in the I−V map with eq 6. Further, the transition border together with eq 6 reveals the actual internal electrostatic coupling between the surface potential of the Si channel with the applied external electric fields. This coupling is significantly different to the case of conventional MOSFETs due to the Schottky barriers at the junctions. Therefore, the coupling cannot be extracted from standard transfer and output characteristics. This is the first report on all types of Schottky FETs of any material and geometry known to us, where the internal potential (e.g., flat band condition at the injecting barrier) can be directly extracted. This reading helps to properly design Schottky based FETs and to understand their scaling phenomena. Furthermore, our findings are transferable to all types of emerging devices including energy barriers in the on-state, such as tunnel FETs, resonant tunneling FETs, and Schottky FETs, for identifying the potential in the inner semiconductor region. Figure 7 shows the transconductance (gm) contour map of the ambipolar SB-TFTs. It is known that gm of SB transistors continually increased with rising Vg due to the enhanced carrier injection by tunneling with the reducing SB width, while conventional Si transistors with highly doped S/D regions show a peak and then degradation of gm for increasing Vg, owing to surface roughness scattering at the interface between channel and insulator under high Vg. However, further increased Vg in the SB transistors could result in a saturation of SB width, where the SB width reaches a minimum value and gm starts to be degraded.23,24 For Vd > 1 V and Vg < −2 V, a peak and degradation behavior of gm was clearly observed in the gm contour map, this means the SB width for hole at the drain junction reaches a minimum value, and hole injection is saturated with the bias condition only. In the case of all other bias regimes, the SB width at both drain and source could be still continually reduced, due to asymmetric Schottky barrier height values between φBe and φBh. In summary, ambipolar SB-TFTs based on a parallel array of bottom-up grown Si-NW have been fabricated, and their operation mechanism and electrical performance were investigated through an in-depth study with several electrical parameters. The nonlinear tendency of Rtot with Lm, gate bias-dependent Rsd, and unique output characteristics were observed due to the characteristic structure of the device with a finite length of Si-NW and the SB limited carrier transport. In particular, the I−V contour map was newly suggested for a better and simpler understanding of operation principle of the ambipolar SB-TFTs, and the offset-voltage (Vc) of ∼0.41 V at equilibrium state was estimated with the I−V map. In addition, it reveals the internal channel to electrode electrostatic coupling, which is a parameter that has not been available from previous studies. The gm contour map revealed a specific bias regime, where the SB width reaches a minimum value. Moreover, the extracted carrier mobility μfe_max of the ambipolar SB-TFTs was ∼15 cm2/(V s), which can be a suitable value for the realization of the next-generation flexible and wearable electronics. It should be also noted that the technology combines the advantages of high quality Si/SiO2 interface with a low interface trap density and Si technology
followed the hole transport region. In addition, the thermionic (TE), thermionic-field (TFE), and field emission (FE) dominant regime of the ambipolar SB-TFTs can be assumed to be located within the blue, green, and red color regimes in the I−V map, separately. Next, the equilibrium state is analyzed. For this, the I−V map representing mostly the TE regime of the ambipolar SB-TFTs is shown again in Figure 6 for an in-depth study of the inter-
Figure 6. I−V contour map representing mostly the TE regime of the ambipolar SB-TFTs for an in-depth study of the inter-relationship among the transition borderline (the dotted black line), SB height, and the Vc (Lm = 6 μm). It was assumed that Ih could be the same as Ie on the borderline.
relationship between the transition borderline, SB height (for electron and hole) and the offset-voltage (Vc) to make the energy band of the NiSi2/Si interface effectively flat at equilibrium state where Vg = Vd = Vs = 0 V.22 The Vc might be originated from surface states, interfacial layer in a SB junction. Charged traps in the insulator and work function of gate metal could also affect the Vc. For Vd < 0 in the TE regime, hole (Ih), and electron current (Ie) near the transition borderline can be assumed as follows, respectively (see Supporting Information):10,22 Ie ≈ A*T 2 exp(−φBe /(kT / q)) exp(Vg − Vd − Vc /(kT / q))
(4)
Ih ≈ B*T 2 exp(−φBh /(kT / q)) exp(Vs− Vg + Vc /(kT / q))
(5)
where A* and B* denote the Richardson constant of electron and hole, respectively, and T is absolute temperature. Finally, one can derive a simple equation, with another assumption of Ih ≈ Ie on the border (the dotted black line in the I−V map of Figure 6) of the transition between hole and electron, as below: Vd ≈ 2Vg + (φBh − φBe) − 2Vc
(6) E
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Figure 7. Transconductance (gm) contour map of the ambipolar SB-TFTs. A peak and degradation behavior of gm was observed for Vd > 1 V and Vg < −2 V only, meaning the SB width for hole reaches a minimum value and the carrier injection by tunneling is saturated with the bias condition. (7) Zheng, G.; Patolsky, F.; Cui, Y.; Wang, W. U.; Lieber, C. M. Nat. Biotechnol. 2005, 23 (10), 1294−1301. (8) Stern, E.; Wagner, R.; Sigworth, F. J.; Breaker, R.; Fahmy, T. M.; Reed, M. A. Nano Lett. 2007, 7 (11), 3405−3409. (9) Knoch, J.; Zhang, M.; Appenzeller, J.; Mantl, S. Appl. Phys. A: Mater. Sci. Process. 2007, 87 (3), 351−357. (10) Sze, S. M.; Ng, K. K. Physics of Semiconductor Devices; John Wiley & Sons: New York, 2006. (11) Ernst, T. Science 2013, 340 (6139), 1414−1415. (12) Weber, W.; Heinzig, A.; Trommer, J.; Martin, D.; Grube, M.; Mikolajick, T. Solid-State Electron. 2014, 102, 12−24. (13) Heinzig, A.; Slesazeck, S.; Kreupl, F.; Mikolajick, T.; Weber, W. M. Nano Lett. 2011, 12 (1), 119−124. (14) Karnaushenko, D.; Ibarlucea, B.; Lee, S.; Lin, G.; Baraban, L.; Pregl, S.; Melzer, M.; Makarov, D.; Weber, W. M.; Mikolajick, T.; Schmidt, O. G.; Cuniberti, G. Adv. Healthcare Mater. 2015, in press. (15) Pregl, S.; Weber, W. M.; Nozaki, D.; Kunstmann, J.; Baraban, L.; Opitz, J.; Mikolajick, T.; Cuniberti, G. Nano Res. 2013, 6 (6), 381− 388. (16) Pregl, S.; Zorgiebel, F.; Baraban, L.; Cuniberti, G.; Mikolajick, T.; Richter, C.; Weber, W. In Channel length dependent sensor response of Schottky-barrier FET pH sensors. 2013 IEEE Sensors; IEEE: New York, 2013; pp 1−4. (17) Kim, E.; Forstner, H.; Foad, M.; Tam, N.; Ramamurthy, S.; Griffin, P.; Plummer, D. Ni2Si and NiSi Formation by Low Temperature Soak and Spike RTPs. In 13th IEEE Int. Conf. Adv. Therm. Process. Semicond., 2005; pp 177−181. (18) Ghibaudo, G. Microelectron. Eng. 1997, 39 (1), 31−57. (19) Sheu, B.; Ko, P. IEEE Electron Dev. Lett. 1984, 5 (11), 491−493. (20) Bhandari, J.; Vinet, M.; Poiroux, T.; Sallese, J. M.; Previtali, B.; Deleonibus, S.; Ionescu, A. M. Investigation of bias-dependent series resistances and barrier height in Double Gate Schottky MOSFETs. In 2009 IEEE International SOI Conference; IEEE: New York, 2009; pp 1−2. (21) Jeon, D.-Y.; Park, S.; Mouis, M.; Berthomé, M.; Barraud, S.; Kim, G.-T.; Ghibaudo, G. Solid-State Electron. 2013, 90, 86−93. (22) Beister, J.; Wachowiak, A.; Heinzig, A.; Trommer, J.; Mikolajick, T.; Weber, W. M. Phys. Status Solidi C 2014, 11 (11−12), 1611−1617.
with a simple printable bottom-up technique that only requires a low thermal budget. As such it becomes possible to separate high temperature processing such as oxidation and forming gas annealing in the Si-NWs growth substrate from the final device structure on a host substrate.14
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ASSOCIATED CONTENT
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AUTHOR INFORMATION
S Supporting Information *
Experimental details and additional figures and references. The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.5b01188. Corresponding Author
*E-mail:
[email protected]. Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS This work was supported by the DFG projects Repronano II (WE 4853/1-2 and MI 1247/6-2) and was carried out in collaboration with the DFG cluster for Excellence Center for Advancing Electronics Dresden (CfAED).
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REFERENCES
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