pubs.acs.org/NanoLett
Self-Aligned Memristor Cross-Point Arrays Fabricated with One Nanoimprint Lithography Step Qiangfei Xia,* J. Joshua Yang, Wei Wu, Xuema Li, and R. Stanley Williams Hewlett-Packard Laboratories, 1501 Page Mill Road, Palo Alto, California 94304 ABSTRACT We demonstrate a technique to fabricate memristor cross-point arrays using a self-aligned, one step nanoimprint lithography process that simultaneously patterns the bottom electrode, switching material film and the top electrode. Since this process does not require overlay alignment, the fabrication complexity is greatly reduced and the throughput is significantly increased. The critical interfaces are exposed to much less contamination and thus under better chemical control. With this technique, we fabricated arrays of TiO2-based memristive devices (junction area 100 nm by 100 nm) that did not require electrical forming and were operated with nanoampere currents. KEYWORDS Memristor, memristive device, nanoimprint lithography, resistive memory, nonvolatile memory, crossbar
M
etal/insulator/metal (MIM) is a common material structure for modern thin film electronic devices, such as magnetic tunnel junctions,1 Josephson 2 junctions, and resistance switches.3,4 Since the interfaces are crucial for the properties of these devices,5,6 fabrication processes play a pivotal role for the device performance, especially when the devices become smaller and the interface-to-volume ratio increases. Memristors and memristive devices7-10 are a family of electronic circuit elements possessing such MIM geometry. With a switching material layer sandwiched between two metal nanowire electrodes, these devices are easy to fabricate and highly scalable. Utilizing a crossbar architecture,11 memristors12 can be conveniently integrated into ultrahigh density circuit arrays using cost-effective fabrication technologies such as nanoimprint lithography (NIL).13-16 The high density and long state retention make them promising candidates for nonvolatile random access memory (NV-RAM).3,17 In addition, applications of memristors as the configuration bits and switches in a data routing network18 and as the electronic synapses in a neuromorphic network19 have been discussed. Previously, NIL has been demonstrated for making highdensity crossbar arrays.20,21 In these demonstrations, two NIL steps were required to fabricate the MIM structure, one for the bottom electrodes and the other for the top. During the processing, the critical interfaces between the switching material and the two electrodes were exposed to wet chemicals, resists, charged particles during reactive ion etching (RIE), and so forth, which may contaminate the interfaces and degrade device performance. Two NIL steps
also require accurate overlay alignment, which increases the fabrication time and cost and lowers the throughput. The device yield may also suffer from defects that are multiplied with more than one NIL step. In this letter, we demonstrate a new fabrication approach for crossbar arrays using only one lithography step for all three layers (two electrodes and the switching layer). We successfully fabricated and characterized memristor crosspoint arrays with junction areas of 100 nm ×100 nm. With only one lithography step, there is no requirement for overlay alignment. The time and effort associated in the fabrication are reduced, hence greatly reducing the cost. One step NIL should induce fewer structural defects, increasing the yield of devices. Most importantly, the critical electrode/ switching layer/electrode interfaces are protected. The first step in the fabrication process was to make a NIL cross bar mold on an optical grade quartz wafer. Double layer resists (an acetone soluble transfer layer and a UVcurable liquid layer) were first sequentially spin-coated onto the quartz surface. A Si master mold with nanowires of 100 nm half pitch (defined by electron beam lithography, EBL) and microscale fan-outs and contact pads (defined by photolithography) was used to pattern the UV-curable resist during NIL. After RIE of the residual UV-resist and the transfer layer, an 8 nm thick Cr film was deposited in an electron beam evaporator, followed by a liftoff process in acetone. A second NIL was carried out on the same quartz substrate using the same Si mold, which was rotated 90°. After RIE, metallization, and liftoff, a second set of Cr nanowires were fabricated on the substrates. The two sets of Cr nanowires formed a cross bar array. Using Cr as the etching barrier, the exposed quartz substrate was then etched to a depth of 50 nm by RIE. After the residual Cr was removed using CR-7 chromium etchant (Cyantek, CA), the
* To whom correspondence should be addressed. E-mail:
[email protected]. Received for review: 03/24/2010 Published on Web: 06/30/2010 © 2010 American Chemical Society
2909
DOI: 10.1021/nl1017157 | Nano Lett. 2010, 10, 2909–2914
deposition technique, which provides conformal coverage of the bottom electrode so that the edge shorting problem can be avoided (Figure 1d). The top electrodes (12.5 nm Pt) were deposited back in the electron beam evaporator in two steps using 20° shadow evaporation, with the samples rotated 180° between the depositions (Figure 1e). A liftoff in acetone with 30 s sonication concluded the crossbar array fabrication, leaving a memristor at each cross point (Figure 1f). The devices were imaged using an optical microscope, an atomic force microscope (AFM), and a scanning electron microscope (SEM) and electrically characterized using an Agilent 4156C semiconductor parameter analyzer. Figure 2 shows images of a 1 × 21 device array with the single horizontal wire at the bottom. The optical image (Figure 2a) demonstrates that the microscale fan-out structures were fabricated for both directions for the 1 × 21 device array. There are three fan-out leads connected to the single horizontal nanowire to provide redundancy for the electrical wiring. The SEM image in Figure 2b shows the linear array of 100 nm ×100 nm devices, while Figure 2c is the AFM image for part of the array. Although the optical and SEM images of these arrays are indistinguishable from those that have been fabricated using a two-step NIL process,10 the device geometry is actually different. For devices fabricated using 2-step NIL, the top electrodes usually reside on a blanket of TiO2 thin film, but in the current case the TiO2 is isolated by the trench pattern. This difference can be observed when measuring the height of the nanowires in the AFM image, which is the sum of TiO2 film and metal nanowire thicknesses. Figure 3 shows the typical electrical switching behavior of the memristors that are fabricated with one NIL step with the electrodes deposited at 20°. A device was turned ON by -3 V applied to the top electrode (bottom electrode grounded), and remained ON afterward. It was turned off by +3 V applied to the top electrode and remained in the OFF state at zero bias, demonstrating nonvolatile bipolar switching. The OFF/ON resistance ratio at 1 V was over 1000. Two notable features of the device behavior were observed for these devices. First, the devices did not require a high-current electrical “forming” process to create conductive channels. Such forming steps have been observed to produce significant material and structural damage to devices because of excessive heating and/or gas eruption.23 Second, the switch current for these devices was fairly low. This leads to lower power consumption and less heat generated during the device operation. To make the current method feasible for a foundry environment, a collimated flux is required during the metal evaporations. The sizes of the evaporation source and the sample substrate as well as the source-substrate distance play important roles in the uniformity of the deposited films across the sample. For the depositions reported here, the sample size was relatively small (1 in. square), and the
FIGURE 1. Schematic of the self-aligned fabrication approach with one NIL step. The cross-shaped trenches are patterned by one NIL step and RIE in resists; after depositing the three layers, a liftoff process concludes the fabrication. The metal electrodes were deposited using angle evaporation so that the metals reach the bottom of one trench but not the other. (a) Spin double layer resists on the substrate; (b) NIL with a cross-bar mold and RIE; (c) deposit bottom electrodes using shadow evaporation; (d) deposit-switching materials layer using sputtering; (e) deposit top electrodes using shadow evaporation; (f) liftoff in solvent. The arrows in (c) and (e) indicate the shadow evaporation directions.
mold surface was cleaned and treated with an antisticking monolayer22 before it was used for fabricating the device arrays. To fabricate the memristive devices, a Si substrate with 100 nm thick thermal oxide was cleaned and spin-coated with double layer resists, similar to that described earlier for the mold fabrication (Figure 1a). NIL was performed using the crossbar quartz mold. After the residual layer and the transfer layer were etched away, the crossbar-shaped trenches remained on the substrate (Figure 1b). We intentionally over etched the transfer layer to create undercuts that ensured a good final liftoff process. Shadow evaporation with an oblique angle of 20° was then carried out for the bottom electrodes. With this angle, the actual thickness of the metal was calibrated to be 70% of the nominal thickness reading. The bottom electrodes (3.5 nm Ti/9 nm Pt, the actual film thicknesses after calibration) were deposited in an electron beam evaporator with a base pressure better than 4 × 10-7 Torr (Figure 1c). The sample was then immediately transferred to a direct current (DC) sputtering system to deposit 13 nm TiO2 at ambient temperature. Sputter-deposition or atomic layer deposition (ALD) was preferred for the TiO2 layer because it is a nondirectional © 2010 American Chemical Society
2910
DOI: 10.1021/nl1017157 | Nano Lett. 2010, 10, 2909-–2914
FIGURE 3. Typical switching behavior of the memristive devices fabricated using one NIL step with oblique deposition angles of 20°. The devices were fabricated on a Si wafer with 100 nm thick thermal oxide with 13 nm thick TiO2 sandwiched between the 12.5 nm thick Pt top electrodes and the 9 nm Pt/3.5 nm Ti bottom electrodes (geometry shown in the inset; not to scale). Device junction area is 100 × 100 nm2. The devices exhibit nonvolatile switching behavior with an ON/OFF ratio larger than 1000 at 1 V. No forming step was necessary and the switching current was much lower than usually observed for similar devices fabricated using a multistep lithography process.
for mass production in which large substrates are used, a much longer distance from the source to the substrate is impractical. Thus, deposition techniques such as ion beamassisted deposition (IBAD), which provides a large source as well as a directional flux, can be adopted,24 or systems in which the substrates are translated under a high flux collimated beam of metal atoms would be required. The choice of incidence angle is critical to avoid deposition of metal into the perpendicular nanotrenches,25-28 and is determined by the aspect ratio of the trenches. A higher aspect ratio enables a higher evaporation angle, but also makes the trench fabrication more difficult. Figure 4 is an idealized illustration of the evaporation angle as a function of the trench aspect ratio. The maximum angle is chosen such that only the top half of the trench wall is exposed to the incident metal, which should then be readily removed by the liftoff process. In our study, we experimented with evaporation angles of 20, 30, 45, and 60° (shown as blue dots in Figure 4) on trenches with a depth/opening aspect ratio ranging from 1.3 to 3. For the samples discussed in this paper, we chose a smaller evaporation angle (20°) than the maximum value for the 100 nm wide and 130 nm deep trenches in the resist stack. Because the nanoscale trenches and the microscale fanout structures were fabricated at the same time, the aspect ratios were not uniform across the sample. Thus, metal entered the microscale fanouts that connect to the nanowires in both directions during the depositions (Figure 2a), but this had no effect on the actual device junction structures and electrical behavior.
FIGURE 2. Images of a 1 × 21 array of memristors fabricated using one NIL step. (a) Optical microscope image. The three fan-out microwires in the horizontal direction are connected to a single nanowire. (b) SEM image of the cross-point array. The junction area for each device is 100 × 100 nm2. (c) AFM image of part of the array.
distance from the source was about 4 ft. As a result, the projected angular divergence onto the 20° titled sample (maximum angle variation at the sample edges) was within (0.2°, or 1% of the sample tilt angle. To scale this technique © 2010 American Chemical Society
2911
DOI: 10.1021/nl1017157 | Nano Lett. 2010, 10, 2909-–2914
FIGURE 4. The idealized illustration of the relationship between the maximum evaporation angle (θ) and the trench aspect ratio (h/w). A smaller deposition angle is required for trenches with a lower aspect ratio. The inset schematically illustrates the geometry of the trench and deposition angle. The angles we explored in this study are indicated by the blue dots.
The angle evaporation scheme did result in a larger rootmean-square (rms) surface roughness of the electrode materials on a planar surface, as well as a certain amount of spikes on the film surface. To observe this effect, we deposited 3 nm Ti/15 nm Pt (nominal thickness, hence 12.5 nm calibrated total thickness for the 20° tilted sample) onto 100 nm thermal dioxide substrates at 90 and 20° incidence angles with a 0.3 Å/s deposition rate in the same chamber. We used AFM (tapping mode) to scan and analyze the surface morphology. The rms roughness of the surface over a 2 µm by 2 µm area for normal incidence was 0.50 nm, while that for 20° incidence was 0.98 nm (Figure 5). The higher surface roughness is likely caused by “self-shadowing” at the low deposition angle in which small variations in the initially deposited film are amplified by shadowing of later arriving atoms.29 As shown in Figure 5b, the 20° incidence caused nanoscale pillars up to 6 nm high. Although this is certainly a cause for concern, such features on the bottom electrode may actually be beneficial for memristor fabrication. To better understand the effect of the bottom electrode morphology on the electric field distribution, we conducted numerical simulations using the COMSOL multiphysics software package (V 3.5a).30 The device geometries used in the simulation were the same as the devices we fabricated (12.5 nm bottom electrode/13 nm TiO2/12.5 nm top electrode). The dielectric constant of TiO2 we used was 60.31 To create a similar surface morphology as measured in Figure 5, we used sinusoidal functions to describe the bottom electrode surface profile, assuming 10 nm grain size. Figure 6 shows the calculated electric field distributions for the two cases considered with 3 V applied voltages. For a rms roughness of 0.5 nm, the electric field in the oxide layer was fairly © 2010 American Chemical Society
FIGURE 5. AFM images of planar film surfaces with different deposition angles. A smaller deposition angle results in a rougher surface. (a) For 90° incidence, the rms roughness was 0.50 nm. (b) For 20° incidence, the rms roughness was 0.98 nm. There are several pillars with heights up to 6 nm in (b).
uniform, and the maximum field strength was 2.8 × 108 V/m (Figure 6a). However, with a rougher bottom electrode surface (0.98 nm rms with 6 nm high metal pillars), the electric field had a significant variation with a maximum strength of 6.4 × 108 V/m at the tip of a pillar (Figure 6b). The field concentration at the metal pillars may facilitate the creation of conductive channels in the devices at relatively low applied bias voltages and thus result in lower switching current,32 leading to the forming-free and low-switchingenergy memristors tested in this study. The electrode deposition angle also affects the device operation and yield. We have noticed that for the devices with electrodes deposited at 30°, the operation current was larger than those made at 20° (see Supporting Information Figure S1). The difference in operational current could be explained by the surface roughness. With a smaller angle and rougher surface, it is more likely to form the predefined nanoscale metal filaments that lead to smaller operation 2912
DOI: 10.1021/nl1017157 | Nano Lett. 2010, 10, 2909-–2914
correction procedures have been developed to handle arrays with nonfunctional devices.33 Although the current demonstration was for orthogonal lines, this procedure should work for structures with an arbitrary angle configuration as long as the trenches in the resist stack have a large enough aspect ratio. Another issue is the critical dimension (CD) control of the top metal nanowire, because the earlier deposition steps narrow the opening of the trenches. Appropriate design of the cross bar dimensions and control in the RIE and deposition process are needed to compensate for trench narrowing. The one-step NIL fabrication process produced formingfree and low-power memristive nanodevices. With an appropriately designed deposition system for both metals and dielectric, all the critical layers could be deposited without breaking the vacuum, which would enable an even better control of the sensitive interfaces. To scale the present technique for mass production would require a means for producing either a large area and unidirectional metal flux or the ability effectively scan a collimated metal flux across a large surface area. Acknowledgment. We thank the U.S. Government’s NanoEnabled Technology Initiative for financial support. Q. X. thanks Dr. S. Bai for help in preparing the schematic illustrations in Figure 1. Supporting Information Available. I-V curves for the nonvolatile operation of devices with electrodes deposited at 30°, typical I-V curves for the all the devices in that array, and device properties statistics. This material is available free of charge via the Internet at http://pubs.acs.org. REFERENCES AND NOTES FIGURE 6. Simulation of the effect of bottom electrode surface roughness on the electric field distribution. The device geometries are 12.5 nm thick Pt top electrode (TE), 13 nm thick TiO2 switching layer, and 12.5 nm thick bottom electrode (BE) for both cases. Sinusoidal surface profiles with 10 nm grain size are assumed for the bottom electrodes. The rms roughnesses are 0.5 and 0.98 nm for (a) and (b), respectively, and the metal pillars in (b) are 6 nm high, corresponding to the measured values in Figure 5. With a rougher surface, the electric field is more localized at the tips of the metal pillars. For 3 V applied voltages, the calculated maximum electrical field for (a) and (b) are 2.8 × 108 and 6.4 × 108 V/m, respectively.
(1)
Moodera, J. S.; Kinder, L. R.; Wang, T. M.; et al. Large magnetoresistance at room temperature in ferromagnetic thin film tunnel junctions. Phys. Rev. Lett. 1995, 74, 3273. (2) Makhlin, Y.; Scho¨n, G.; Shnirman, A. Quantum-state engineering with Josephson-junction devices. Rev. Mod. Phys. 2001, 73, 357. (3) Waser, R.; Aono, M. Nanoionics-based resistive switching memories. Nat. Mater. 2007, 6, 833–840. (4) Waser, R.; Dittmann, R.; Staikov, G.; et al. Redox-based resistive switching memories -Nanoionic mechanisms, prospects, and challenges. Adv. Mater. 2009, 21, 2632–2663. (5) Blackstock, J. J.; Donley, C. L.; Stickle, W. F.; et al. Oxide and carbide formation at titanium/organic monolayer interfaces. J. Am. Chem. Soc. 2008, 130, 4041–4047. (6) Yang, J. J.; Xiang, H.; Ji, C. X.; et al. Origin of inverse tunneling magnetoresistance in a symmetric junction revealed by delaminating the buried electronic interface. Appl. Phys. Lett. 2009, 95, 233117. (7) Chua, L. O. Memristor - the missing circuit element. IEEE Trans. Circuit Theory 1971, 18, 507–519. (8) Chua, L. O.; Kang, S. M. Memristive devices and systems. Proc. IEEE 1976, 64, 209–223. (9) Strukov, D. B.; Snider, G. S.; Stewart, D. R.; Williams, R. S. The missing memristor found. Nature 2008, 453, 80–83. (10) Yang, J. J.; Pickett, M. D.; Li, X.; et al. Memristive switching mechanism for metal/oxide/metal nanodevices. Nat. Nanotechnol. 2008, 3, 429–433. (11) Kuekes, P. J.; Snider, G. S.; Williams, R. S. Crossbar nanocomputers. Sci. Am. 2005, 293, 72–79.
current. However, the device yield for a larger oblique angle was higher. For example, out of the 21 devices in the 1 × 21 array that were fabricated at 20°, only 5 operated successfully (major failure mode was broken wire). However, increasing the deposition angle to 30° resulted in satisfactory operation of up to 20 devices (a 95.2% yield), which is a reasonable yield for laboratory-fabricated devices (see Supporting Information Figure S2 for the I-V curves and Figure S3 for resistance statistics). Some level of defects are anticipated even for foundry-built nanodevices, and error © 2010 American Chemical Society
2913
DOI: 10.1021/nl1017157 | Nano Lett. 2010, 10, 2909-–2914
(12) Yang, J. J.; Julien, B.; Murphy, D.; et al. A family of electronically reconfigurable nanodevices. Adv. Mater. 2009, 21, 3754–3758. (13) Chou, S. Y.; Krauss, P. R.; Renstrom, P. J. Imprint of sub-25 nm vias and trenches in polymers. Appl. Phys. Lett. 1995, 67, 3754– 3758. (14) Chou, S. Y.; Krauss, P. R.; Renstrom, P. J. Imprint lithography with 25-nanometer resolution. Science 1996, 272, 85–87. (15) Haisma, J.; Verheijen, M.; vanden Heuvel, K.; vanden Berg, J. Mold-assisted nanolithography: A process for reliable pattern replication. J. Vac. Sci. Technol., B 1996, 14, 4124–4128. (16) Colburn, M.; Johnson, S.; Stewart, M.; et al. Step and flash imprint lithography: A new approach to high-resolution patterning. Proc. SPIE 1999, 3676, 379–389. (17) Meijer, G. I. Who wins the nonvolatile memory race. Science 2008, 319, 1625–1626. (18) Xia, Q. F.; Robinett, W.; Cumbie, M. W.; et al. Memristor-CMOS hybrid integrated circuits for reconfigurable logic. Nano Lett. 2009, 9, 3640–3645. (19) Snider, G. S. Self-organized computation with unreliable, memristive nanodevices. Nanotechnology 2007, 18, 365202. (20) Jung, G. Y.; Ganapathiappan, S.; Ohlberg., D. A. A.; et al. Fabrication of a 34 × 34 crossbar structure at 50 nm half-pitch by UVbased nanoimprint lithography. Nano Lett. 2004, 4, 1225–1229. (21) Wu, W.; Jung, G. Y.; Olynick, D. L.; et al. One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography. Appl. Phys. A 2005, 80, 1173–1178. (22) Jung, G. -Y.; Li, Z.; Wu, W.; et al. Vapor-phase self-assembled monolayer for improved mold release in nanoimprint lithography. Langmuir 2005, 21, 1158–1161. (23) Yang, J. J.; Miao, F.; Pickett, M. D.; et al. The mechanism of electroforming of metal oxide memristive switches. Nanotechnology 2009, 20, 215209.
© 2010 American Chemical Society
(24) Smidt, F. A. Use of ion-beam assisted deposition to modify the microstructure and properties of thin films. Int. Mater. Rev. 1990, 35, 61–128. (25) Chou, S. Y.; Fischer, P. B. Double 15-nm-wide metal gates 10 nm apart and 70 nm thick on GaAs. J. Vac. Sci. Technol., B 1990, 8, 1919–1922. (26) Horn, M. W.; Pickett, M. D.; Messier, R.; et al. Blending of nanoscale and microscale in uniform large-area sculptured thinfilm architectures. Nanotechnology 2004, 15, 303–310. (27) Schvartzman, M.; Wind, S. J. Robust pattern transfer of nanoimprinted features for sub-5-nm fabrication. Nano Lett. 2009, 9, 3629–3634. (28) Sun, L. F.; Chin, S. N.; Marx, E.; et al. Shadow-evaporated nanometre-sized gaps and their use in electrical studies of nanocrystals. Nanotechnology 2005, 16, 631–634. (29) Vick, D.; Friedricha, L. J.; Dewa, S. K.; Bretta, M. J.; Robbiea, K.; Setoa, M.; Smyb., T. Self-shadowing and surface diffusion effects in obliquely deposited thin films. Thin Solid Film 1999, 339, 88– 94. (30) COMSOL multiphysics software package. http://www.comsol. com. Accessed May 6, 2010. (31) Stamate, M. D. Dielectric properties of TiO2 thin films deposited by a DC magnetron sputtering system. Thin Solid Films 2000, 372, 246–249. (32) Yang, J. J.; Strachan, J. P.; Xia, Q. F. Diffusion of adhesion layer metals controls nanoscale memristive switching. Adv. Mater., in press. (33) Snider, G. S.; Kuekes, P.; Williams, R. S. CMOS-like logic in defective, nanoscale crossbars. Nanotechnology 2004, 15, 881– 891.
2914
DOI: 10.1021/nl1017157 | Nano Lett. 2010, 10, 2909-–2914
