Self-Assembled Sn nanocrystals as the floating gate of non

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Self-Assembled Sn nanocrystals as the floating gate of non-volatile flash memory Jaswant Rathore, Rajveer S Fandan, Shalini Srivastava, Krista R Khiangte, Sudipta Das, Udayan Ganguly, Apurba Laha, and Suddhasatta Mahapatra ACS Appl. Electron. Mater., Just Accepted Manuscript • DOI: 10.1021/acsaelm.9b00379 • Publication Date (Web): 26 Aug 2019 Downloaded from pubs.acs.org on August 30, 2019

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ACS Applied Electronic Materials

Self-Assembled Sn nanocrystals as the floating gate of non-volatile flash memory Jaswant S. Rathore1, Rajveer Fandan2, †, Shalini Srivastava2, Krista R. Khiangte1, Sudipta Das1, 2, Udayan Ganguly2, Apurba Laha2, Suddhasatta Mahapatra1, * 1Department

of Physics, Indian Institute of Technology Bombay, Mumbai 400076, India

2Department

of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai 400076,

India †Current

Address: Escuela Técnica Superior de Ingenieros de Telecomunicación, Universidad

Politécnica de Madrid *Corresponding

Author: [email protected]

ABSTRACT: As demands for data storage capability continues to increase, non-volatile memory devices with discrete nanocrystals as the charge storage nodes, are being extensively investigated. To alleviate scaling issues, use of metal-nanocrystal based ultrahigh-bit-density memory devices, capable of multilevel cell operations, have been proposed and studied widely. Here we propose a non-volatile charge-trapping memory, utilizing nanocrystals of the group-IV metal, -Tin (-Sn), which spontaneously self-assemble on a variety of high-k dielectric oxides and silicon, during molecular beam epitaxy at low temperatures. In metal-oxide-semiconductor memory devices, we demonstrate a large memory window (~ 3 V) at moderate operating voltages of ± 6 V and investigate the retention and endurance characteristics. The observed results are promising for realization of memory devices, compatible with the silicon complementary-metaloxide-semiconductor technology. KEYWORDS: Non-volatile memory, Tin nanocrystals, Self-assembly, Molecular beam epitaxy, CMOScompatible.

Introduction Non-volatile flash memory is a key component of a variety of portable electronic devices in widespread use nowadays. Driven by the continuously increasing demand for information storage, unprecedented progress has been made over the past couple of decades, in the development of high-density and high-reliability, yet low-cost and less-power-consuming flash memory devices. The conventional polysilicon-based floating-gate, invented in 1967 by Sze and Kahng1, continues to be the mainstay of flash memory structure. However, to keep up with the aggressive downscaling of the complementary-metal-oxide-semiconductor (CMOS) technology, this traditional design has faced many challenges in maintaining device performance and reliability. Considerable emphasis has therefore been directed to the search for new materials and structures, which can be used as a storage node in flash memory devices2-4.

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Replacement of the continuous (polysilicon) floating-gate with a layer of discrete nanocrystals (NCs) is one of the promising ways to achieve high scalability, high-speed operation, low programming/erasing voltages, and good charge retention characteristics of NVMs. Due to the discrete nature of the NC-based floating-gate, charge leakage due to defects in the underlying thin tunnel-oxide is limited only to a small number of NCs, thus improving the charge retention and endurance characteristics. Moreover, the discreteness of the charge storage nodes enables multibit-per-cell storage, without resorting to the multilevel approach5, 6. In the recent past, many research efforts have therefore focussed on the use of NCs of semiconductors7-13, metals6, 14-25, metal silicides26, or high-k dielectrics27-30, to form the discrete floating-gate of NVMs. As one of the candidates for discrete charge storage nodes, metal NCs provide several advantages over their semiconductor counterparts6. Firstly, metals have a high density of states (DOS) near the Fermi energy (𝜀𝐹). This implies that metal NCs are more immune to small fluctuations in 𝜀𝐹, which may be caused by contamination or unwanted intermixing with the surrounding matrix. Secondly, unlike in the case of semiconductor NCs, three-dimensional carrier confinement effects are negligible in case of metal NCs, even down to length scales of a few nanometres5. Thus, size fluctuations are of less concern in case of metal NCs. Metal NCs are also much more amenable to scalability of both size and areal density. Finally, metals provide a variety of work functions (𝜙𝑀) from which a (combination of) suitable candidate(s) 3, 6 for efficient charge storage may be chosen. The work function of the metal affects both the potential barrier height and the DOS available to the charge carriers. Metal NCs whose 𝜙𝑀 can be tuned to lie in the Si band gap under charge retention, and above the conduction band edge during the erase operation, allow large memory retention and high memory speeds at the same time6. Another important consideration in the choice of a metal for charge storage in memory devices is the compatibility of its formation method with the established Si CMOS technology. Several metal NC formation methods require rapid thermal annealing (RTA) of the corresponding metal films, deposited on top of thin tunnel-oxides3, which in turn, are grown on suitable silicon substrates. Alternatively, NCs are formed by ion-implantation followed by RTA3, 6 or are obtained from chemical-synthesis routes19, 20 and aerosol techniques31. While ion-implantation techniques suffer from spatial controllability issues, RTA and spin coating techniques may be undesirable due to thermal budget restrictions and chemical contamination issues32, respectively. In this work, we report a novel low-temperature approach for fabricating NC-based non-volatile memory devices, exploiting the natural propensity of the group-IV metal, 𝛽 –Tin (𝛽 ― Sn), to spontaneously self-assemble on a variety of (oxide) surfaces during molecular beam epitaxy (MBE). We demonstrate a large memory window ( ~ 3 V) at moderate operating voltages of ± 6 V and good retention characteristics of metal-oxide-semiconductor (MOS) memory structures, fabricated with nearly-spherical nanocrystals of 𝛽 ― Sn, self-assembled on HfO2 and Al2O3 tunnel oxides, and encapsulated by an Al2O3 control oxide.The observed memory characteristics, and the possibility of using a group-IV metal in a low temperature fabrication process, may pave new avenues for the development of NC-based NVMs in the near future.


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Similar to silicon (Si) and germanium (Ge), Sn is a group-IV element, which is non-toxic and inexpensive. At room temperature, 𝛽 ― Sn is the stable allotropic form of tin, which is metallic in nature and has a body-centred tetragonal crystal structure. Tin is highly resistant to oxidation in ambient conditions and has a low solid-solubility in both Si and Ge. In previous works, Sn has been found to exhibit a strong tendency to segregate from the bulk of Si33, Ge34, and GaAs35 substrates. This tendency to segregate is possibly driven by the low surface energy () of Sn ( 𝛾Sn(001) = 0.611 𝐽/𝑚2, while 𝛾Si(001) = 2.13 𝐽/𝑚2), coupled to a high mismatch of the Sn lattice parameter with those of the technologically important semiconductors. Despite a lower surface energy, 𝛽 ― Sn self-assembles in nano-sized, nearly-spherical islands on Si(001), which is reminiscent of the Volmer-Weber (VW) growth mode in heteroepitaxy.This is counter-intuitive to the established view of metal epitaxy on semiconducting and oxide surfaces, wherein VW growth is driven by a higher surface energy of the metal, compared to that of the substrate material36. Nonetheless VW growth of 𝛽 ― Sn is observed for growth on a variety of (poly-)crystalline oxides grown on Si(001) substrates, such as HfO2/Si(001), Al2O3/Si(001), and Gd2O3/Si(001). Figures 1 (a), (b), and (c) show scanning electron microscope (SEM) images of self-assembled Sn NCs on HfO2/Si(001), Al2O3/Si(001),and Si(001) surfaces, respectively. Atomic force microscope (AFM) images of the first two samples are shown in the insets of Figures 1 (d) and 1 (e), respectively. The Sn NCs have been grown by evaporating 6N-purity Sn (for 30 min) from a standard effusion cell (maintained at 𝑇𝑆𝑛 = 900C) in a solid-source molecular beam epitaxy (MBE) system, at a growth temperature of 𝑇𝐺 = 150 C. From the SEM images (Figs. 1(b) and 1(d)), we estimated the average diameter and areal density of the NCs to be ~ 12 ± 1 nm ( ~ 14 ± 1nm) (See Supplementary Figure S1) and ~ 3 × 1011 cm-2(~ 1 × 1011 cm-2) for selfassembly on the HfO2/Si(001) (Al2O3/Si(001)) surface. A very large tunability of both the size and areal density of the self-assembled NCs can be achieved, by suitably tailoring the duration and temperature of MBE growth (Supplementary Fig. S2). Grazing incidence X-ray diffraction (GIXRD) data, collected from Sn/HfO2/Si(001) and Sn/Al2O3/Si(001) samples, are shown in Figures 1 (d), and 1 (e), respectively. The diffractograms reveal that Sn exists in the NCs entirely in its 𝛽- allotropic form. This is not surprising, since the other (semiconducting) allotropic form (𝛼-Sn) is stable only below 13.2 C. The high resistance to oxidation of Sn is reflected by the fact that no features due to oxides of Sn are visible in the GIXRD data, albeit that the diffractogram of Figure 1 (d) was collected after 12 months of storage, under ambient conditions. Existence of Sn in its metallic form (𝛽 ― Sn) and its high resistance to oxidation are both very promising attributes for their use as charge trapping elements in flash memory devices. Metals which tend to oxidise easily, such as cobalt37, result in formation of NCs with a metallic-core and insulating-shell, making erasing operation difficult. The details of the MOS memory structures studied in this work are listed in Table 1. For all MOS structures (and the uncapped samples discussed before), RCA-cleaned, p-type Si (001) substrates have been used, and all oxides have been grown by atomic layer deposition (ALD), at 200 C



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(except the control oxide of sample A, which has been deposited at room temperature in a physical vapour deposition (PVD) system). For sample A, the tunnel oxide was annealed at 600 C for 60 seconds, in a 95% N2 and 5% H2 ambient. The top gates were defined by electron beam evaporation of Pt (capped with Al) at a base pressure of 1×10-6 Torr. Sample ID Sample A Sample B

Tunnel oxide HfO2 (8 nm) Al2O3 (4 nm)

Control Oxide

Gate

Al2O3 (55 nm) Al2O3 (20 nm)

Pt (50 nm)/Al (200 nm) Pt (15 nm)/Al (120 nm)

Table 1. Details of the two types of MOS memory structures studied here. In both cases the charge trapping layer is an ensemble of self-assembled Sn NCs, obtained by MBE deposition (for 30 min) of Sn at TG = 150C, with the Sn-effusion cell maintained at 𝑇𝑆𝑛 = 900C. Considering the relative dielectric constant of HfO2 (Al2O3) to be 𝜖𝐻𝑓𝑂2 = 16 (𝜖𝐴𝑙2𝑂3 = 8), the effective oxide thickness (EOT) of the both tunnel oxides is 1.9 nm.

Figure 2 (a) shows a large area cross-sectional transmission electron microscopy (TEM) image of an Al2O3 (55 nm)/Sn-NC/ HfO2 (8 nm)/p-Si (001)) stack (similar to sample A, but without the metal gates on top), wherein the layer of discrete Sn NCs, atop the HfO2 tunnel oxide, is clearly visible. The close-up TEM image of one such Sn-NC, shown in Figure 2 (b), suggests that the NCs are near-spherical in shape, subtending a very large contact angle with the underlying HfO2 surface. Capping with the Al2O3 blocking layer does not significantly alter the chemical purity of the nanocrystals. This fact, which is crucial for the memory performance, is revealed in the energydispersive X-ray (EDX) elemental map of Sn, shown in Figure 2 (d). This map was recorded for the selected cross-sectional area of the MOS structure shown in Figure 2 (c), wherein the presence of Sn is seen only within the discrete NC-regions. Also shown in Figures 2 (e) and 2 (f) are the corresponding maps for Al and Hf, respectively. The latter is strictly confined to the tunnelling layer, underneath the NCs. It is noteworthy that the HfO2 tunnel-oxide is fully epitaxial in nature. An analysis of the angle between the observed lattice planes (See Supplementary Figure S3), and comparison with similar HRTEM data for HfO2/Si(001) and HfO2/GaAs(001) systems, reported by Kukli et. al.38 and Liou et. al.39 suggest that the HfO2 epilayer has an monoclinic (a = 5.119 Å, b = 5.169 Å, and c = 5.297Å,  = 99) crystal structure. Programming (erasing) of information in a floating-gate non-volatile memory is performed by injecting (removing) charges onto (from) the floating gate, which in this case is defined by the ensemble of Sn NCs. In order to probe the feasibility of storing charges on the Sn NCs, real-space imaging of the programmed and erased states have been obtained from an Al2O3 (20-nm)/Sn-NC/ Al2O3 (4-nm)/p-Si(001) stack (similar to sample B, but without the metal gates on top) by scanning Kelvin probe microscopy (SKPM). By mapping the contact potential difference (CPD) between the metallic scanning tip and the surface of the control oxide, charges stored within the Sn NCs are detected by SKPM (as discussed in previous reports19, 20, 40). The SKPM measurement consists


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of two steps. In the first step, the probe is scanned in contact mode over a certain area, with a DC bias applied to the substrate. In this step, electrons tunnel from (to) the substrate to (from) the SnNCs (across the 4-nm-thick Al2O3 tunnel-oxide), for an applied negative (positive) bias, yielding the programmed (erased) state. In the second step, the CPD map is obtained for a larger area, by recording the real-time deflection of the cantilever in a constant-tip-height (50 nm) mode, with the bias removed from the substrate. Figure 3 (b) to 3 (d) show the surface potential maps for programmed and erased states, collected from an area of 5 × 5m2, for different bias voltages applied to the substrate. The clear difference in the contrast of the programmed/erased state, with respect to the initial state, confirms the feasibility of charge storage/removal onto/from the embedded Sn-NC ensemble. The CPD is observed to increase with increasing substrate bias, indicating larger charge transfer to/from the NCs. As the maps at different substrate biases were collected from arbitrarily chosen areas of the sample, it may be inferred that the NC-density is fairly uniform over length-scales defined by the size of the scanned areas. Figure 3 (a) shows a surface potential map, wherein a 500 × 500 nm2 area has been erased within an initially programmed area of 1 × 1m2. This demonstrates that the ensemble of self-assembled Sn-NCs can yield memory characteristics with high density charge-storage at nanometre length-scales. For quantitative analysis of the memory characteristics, capacitance-voltage (C-V) data have been recorded from the MOS memory structures, using an Agilent B1500A semiconductor device parameter analyser at room temperature. Figures 4 (a) and 4 (b) show the high-frequency (10 kHz and 100 kHz) C-V characteristics of sample A (8-nm HfO2-tunnel oxide) and sample B (4-nm Al2O3-tunnel oxide), respectively, while the inset of Figure 4 (a) (along with the main panel) shows the same for a control sample, which is a Pt/55-nm-thick, PVD-deposited Al2O3/p-Si(001) MOS structure (with no embedded Sn NC within the oxide layer)41. Note that for the C-V measurements, the voltage has been applied to the gate terminal, with the back side of the substrate at ground potential. Thus, the C-V measurement configuration is reversed w.r.t. that of SKPM data, presented earlier. For the “program” state, the Pt-gate is biased positively with respect to the Si substrate. Consequently, electrons are injected to the NCs, from the (weak) inversion layer at the tunneloxide-p-Si interface, causing a positive shift of the flat band voltage. These electrons stored in the Sn NCs are lost either by reverse tunnelling or recombination with injected holes, when a negative bias is applied to the gate in the “erase state”. As a result, the flat band voltage shows a negative shift, thus yielding the hysteresis in the C-V characteristics. The positive shift of the flat band voltage after programming (with respect to the flat band voltage of the control sample) is larger compared to the negative shift after erasing. This indicates to the relative ease of electron injection to the NCs, compared to injection of holes, which may be understood by considering the schematic flat-band band diagrams corresponding to the MOS structures of samples A and B, shown in Figure 4 (c). It is observed that for both the Si-HfO2 and Si-Al2O3 interfaces, the conduction band offset



(and hence the barrier to electron tunnelling) is smaller than the valence band offset (and hence the barrier to hole-tunnelling). This explains the asymmetry in the program/erase flat-band-voltage shifts, observed in Figs. 4 (a) and 4 (b). We note that the Fermi level of (bulk) -Sn is ~ 300 meV below the conduction band edge and ~ 800 meV above the valence band edge of Si. The thick control oxide ensures that the leakage current from the gate is minimized during either of the program/erase operations. The nearly-hysteresis-free C-VG plot of the control sample indicates negligible contribution of interface traps and fixed oxide charges to the memory effect. The memory window of the device, defined by the shift in the flat-band-voltage (Δ𝑉𝐹𝐵), is observed to be ~ 4 V (~ 3 V) for sample A (sample B), for a bias range of ± 10 V (± 6V), and measurement frequency of 10 KHz. This large memory window is comparable to that obtained earlier for molybdenum (Mo)3 and silicon nanocrystals6, with SiO2 as the tunnel oxide in both cases (See Supplementary Table ST1). At 100 KHz, the memory window is observed to reduce significantly for sample B, while it appears to be almost unchanged for sample A. Reduction of Δ 𝑉𝐹𝐵 at higher measurement frequency may be explained by insufficient time for carrier tunnelling to the Sn NCs. The effect is more pronounced in sample B, possibly due to the larger barrier height for both electron and hole tunnelling across the Al2O3 tunnel-oxide (See Fig. 4(c)). Using the 1 𝜖𝑇 relation Δ𝑉 = (𝑛𝑁𝑒 𝜖 ) 𝑡 + 𝑑 22, the average number of electrons stored by each NC of 𝐹𝐵

𝑇

(

𝐶

2𝜖𝑁𝐶 𝑁𝐶

)

sample A (sample B), for Δ𝑉𝐹𝐵 = 4.22 V (3.23 V), is estimated to be 𝑁 ~ 22 (~ 68). Here, the permittivity of the tunnel oxide is taken to be 𝜖𝐻𝑓𝑂2 = 16 𝜖0 (𝜖𝐴𝑙2𝑂3 = 8𝜖042), and the permittivity of Sn is assumed to be 𝜖𝑁𝐶 = 65𝜖043 (𝜖0= 8.85 × 10 ―12 F/m is the permittivity of vacuum). The assumed relative dielectric constant of HfO2 is as expected for the monoclinic phase44. We directly determined the value from the C-V analysis of a Pt (65 nm)/3-nm-HfO2/n-Si(001) MOS capacitor (See Supplementary Figure S4), with the gate oxide deposited and annealed by the same recipe, as that of the tunnel oxide of sample A. The thickness of the Al2O3 blocking oxide is 𝑡𝐶 = 55 nm (20 nm), the average diameter of Sn NCs is 𝑑𝑁𝐶 = 12 nm (14 nm), the areal density of NCs is, 𝑛 = 3 × 1011cm ―2 (1 × 1011cm ―2),for sample A (sample B), and 𝑒 in the expression is the charge of an electron. The electrostatic energy (𝐸𝐶) needed to add one electron to each Sn NC can be calculated 2 from the relation 𝐸𝐶 = 𝑒 𝐶𝑁𝐶, where 𝐶𝑁𝐶 is the size-dependant capacitance of the NC, given by 𝐶𝑁𝐶 = 2𝜋𝜖0𝜖𝐴𝑙2𝑂3𝑑𝑁𝐶. Here, 𝜖𝐴𝑙2𝑂3 appears as the dielectric constant of the surrounding control oxide (for both samples). The calculated average electrostatic charging energy for the Sn NCs is 𝐸𝐶 = 29.94 meV (27.64 meV) for sample A (sample B). Figure 4 (d) shows the variation of the memory window with the bias voltage range, for both the samples. While for sample A, Δ𝑉𝐹𝐵 saturates beyond ~ 4 V, for sample B, it increases nearly linearly, reaching a value of 11.76 V for a bias range of ± 15 V. This suggests more efficient field-induced enhancement of charge tunnelling in case of the latter (with a 4-nm-thick tunnel oxide), compared to the former (with an 8-nm-thick tunnel oxide), despite the fact that the tunnelling barrier height for Al2O3 is significantly larger than that for HfO2.


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The reliability of a non-volatile memory is determined by its charge retention and endurance characteristics. To evaluate the charge retention properties of the Sn-nanocrystal-based memory, the MOS device of sample A (sample B), was initially programmed/erased by applying VG = 11 V (11 V)/-11 V (-11 V) for 5 s (1s). C-VG measurements were then performed at room temperature within a small range of voltages around 𝑉𝐹𝐵, and the flat-band voltage was measured after different time intervals. Figure 5 (a) and 5 (b) show the shift of the flat-band voltage with the retention time, both for programming and erasing operations, for sample A and sample B, respectively. Extrapolating the measured shift in 𝑉𝐹𝐵, the charge loss of the memory device in 10 years is estimated to be only~ 8 % for sample A. This is amongst the lowest values of charge loss, reported so far (See Supplementary Table ST1). However, it should be noted that the tunnel oxide in case of sample A is significantly thicker (~ 8 nm) than those reported usually (2 nm – 5 nm). While a thicker tunnel oxide improves charge retention, it is known to reduce the programming/erasing speed. On the other hand, for the thin tunnel oxide of sample B (~ 4 nm), the charge loss after 10 years is ~ 60 % (Fig. 5 (b)), though the programming/erasing speed is sufficiently high (See Supplementary Figure S5). This relatively high charge loss reflects that the ALD of the thin Al2O3 used as the tunnel oxide (and/or the Al2O3 blocking oxide) in sample B, possibly requires further optimization. In fact, for same thicknesses of the tunnel and control oxides as that of sample B, but nominally smaller Sn-NCs (corresponding to 5 min Sn deposition), the charge loss after 10 years was measured to be 35 % (See supplementary Figure S6). The same trend is also observed in endurance measurements, carried out at a sweep voltage range of VG = 11 V for both samples. The shift of 𝑉𝐹𝐵 as a function of the number of programming and erasing cycles is shown in Figures 5 (c) and 5 (d). It is observed that the reduction in the memory window after 106 (103) programming/erasing (P/E) cycles is 6.5% (35 %), for sample A (sample B). Thus, a comparison of the charge retention and endurance characteristics of the two samples indicates that, with optimized tunnel-oxide quality, very high stability and reliability may be obtained for Sn-nanocrystal-based floating-gate non-volatile memories, without significantly compromising the programming/erasing speed. Conclusion In conclusion, we have demonstrated that Sn nanocrystals self-assembled in low temperature molecular beam epitaxy can function as efficient charge storage nodes, for fabrication of nonvolatile flash memory. The largest memory window measured in this work is ~ 4.06 V and ~11.76 V (for operating voltage ranges of ± 14 V and ± 15 V, respectively), with an 8-nm-thick HfO2 and a 4-nm-thick Al2O3 as the tunnel oxide, respectively. Furthermore, a very low charge loss (8 % in 10 years) was obtained for the former device. The low temperature CMOS-compatible process45,



for realizing these nanocrystals, together with the demonstrated memory characteristics, makes this system a promising candidate for future flash memory applications. Acknowledgements: The research was funded by the Science and Engineering Research Board, Department of Science and Technology, Government of India. We acknowledge support from the Centre of Excellence in Nano-electronics, Indian Institute of Technology Bombay. Supporting Information: NC size distribution, Variation of NC density and size, Crystal structure of epitaxial HfO2 tunnel oxide, Dielectric constant of HfO2 tunnel oxide, Program/Erase speed, Retention and endurance of MOS device with smaller NCs. References (1) Kahng, D.; Sze, S. M. A Floating Gate and Its Application to Memory Devices. TheBell. Syst. Tech. J. 1967, 46, 1288–1295. (2) Lee, J. Progress in Non-volatile Memory Devices based on Nanostructured Materials and Nanofabrication. J. Mater. Chem.2011, 21, 14097. (3) Chang, T. C.; Jiana, F. Y.; Chen, S. C.; Tsai, Y.T. Developments in Nanocrystal Memory.Mater. Today. 2011, 14, 608–615. (4) Lee, J. Nano-Floating Gate Memory Devices. Electron. Mater. Lett. 2011, 7, 175-183. (5) Eitan, B.; Pavan, P.; Bloom, I.; Aloni, E.; Frommer, A.; Finzi, D. NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell. IEEE Electron. Dev. Lett. 2000, 21, 543–545. (6) Liu, Z.; Lee, C.; Narayanan, V.; Pei, G.; Kan, E.-C. Metal Nanocrystal Memories—Part I: Device Design and Fabrication. IEEE Trans. Electron. Dev. 2002, 49, 1606-1613. (7) Tiwari, S.; Rana, F.; Hanafi, H.; Hartstein, A.; Crabbé, E.; Chan, K. A Silicon Nanocrystals based Memory. Appl. Phys. Lett. 1996, 68, 1377-1379. (8) Kapetanakis, E.; Normand, P.; Tsoukalas, D.; Beltsios, K.; Stoemenos, J.; Zhang, S.; Van Den Berg, J. Charge storage and interface states effects in Si-nanocrystal memory obtained using low-energy Si+ implantation and annealing. Appl. Phys. Lett. 2000, 77, 3450. (9) Manna, S.; Aluguri, R.; Katiyar, A.; Das, S.; Laha, A.; Osten, H. J.; Ray, S. K. MBE-grown Si and Si1xGex quantum dots embedded within epitaxial Gd2O3 on Si(111) substrate for floating gate memory device. Nanotechnol. 2013, 24, 505709 (10) Bar, R.; Aluguri, R.; Manna, S.; Gosh, A.; Satyam, P. V.; Ray, S. K. Multilayer Ge nanocrystals embedded within Al2O3 matrix for high performance floating gate memory devices. Appl. Phys. Lett. 2015, 107, 093102


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(11) Lehninger, D.; Seidel, P.; Geyer, M.; Schneider, F.; Klemm, V.; Rafaja, D.; Borany, J. V.; Heitmann, J. Charge trapping of Ge-nanocrystals embedded in TaZrOx dielectric films. Appl. Phys. Lett. 2015, 106, 023116 (12) Lepadatu, A. M.; Palade, C.; Slav, A.; Maraloiu, A. V.; Lazanu, S.; Stoica, T.; Logofatu, C.; Teodorescu, V. S.; Ciurea, M. L. Single layer of Ge quantum dots in HfO2 for floating gate memory capacitors. Nanotechnol. 2017, 28, 175707 (13) Lehninger, D.; Beyer, J.; Heitmann, J. A Review on Ge Nanocrystals Embedded in SiO2 and High-k Dielectrics. Phys. Status Solidi A, 2018, 215, 1701028 (14) Liu, Z.; Narayanan, V.; Kim, M.; Pei, G.; Kan, E. Low Programming Voltages and Long Retention time in Metal Nanocrystal EEPROM devices. Device Research Conference. Conference Digest (Cat. No.01TH8561), 2001, 79-80. (15) Samanta, S. K.; Singh, P. K.; Yoo W. J.; Samudra, G.; Yeo, Y. C.; Bera, L. K.; Balasubramanian, N. Enhancement of Memory Window in Short Channel Non-Volatile Memory Devices Using Double Layer Tungsten Nanocrystals. IEDM Tech. Dig., 2005, 170-173. (16) Lee, J.; Kwong, D. Metal Nanocrystal Memory with High-k Tunnelling Barrier for Improved Data Retention. IEEE Trans. Electron. Dev. 2005, 52, 507-511. (17) Yim, S.; Lee, M.; Kim, K.; Kim, K. Formation of Ru Nanocrystals by Plasma Enhanced Atomic Layer Deposition for Non-volatile Memory Applications. Appl. Phys. Lett. 2006, 89, 093115. (18) Yang, F.; Chang, T.; Liu, P.; Yeh, P.; Yu, Y.; Lin, J.; Sze, S.; Lou, J. Memory Characteristics of Co Nanocrystal Memory Device with HfO2 as Blocking Oxide. Appl. Phys. Lett. 2007, 90, 132102. (19) Lee, J.; Cho, J.; Lee, C.; Kim, I.; Park, J.; Kim, Y.; Shin, H.; Lee, J.; Caruso, F. Layer-by-layer Assembled Charge-trap Memory Devices with Adjustable Electronic Properties. Nat. Nanotechnol. 2007, 2, 790-795. (20) Lin, C.-C.; Chang, T.-C.; Tu, C.-H.; Chen, W.-R.; Hu, C.-W.; Sze, S.-M.; Tseng, T.-Y.; Chen, S.-C.; Lin, J.-W. Charge Storage Characteristics of Mo Nanocrystal Dependence on Mo Oxide Reduction. Appl. Phys. Lett. 2008, 93, 222101. (21) Ping, M.; Zhi-Gang, Z.; Li-Yang, P.; Jun, X.; Pei-Yi, C. Nonvolatile Memory Characteristics with Embedded High Density Ruthenium Nanocrystals. Chinese Phys. Lett. 2009, 26, 056104. (22) Lee, J.; Kim, Y.; Kwon, J.; Shin, H.; Sohn, B.; Lee, J. Tunable Memory Characteristics of Nanostructured, Non-volatile Charge Trap Memory Devices Based on a Binary Mixture of Metal Nanoparticles as a Charge Trapping Layer. Adv. Mater.2009, 21, 178-183. (23) Hong, A.; Liu, C.; Wang, Y.; Kim, J.; Xiu, F.; Ji, S.; Zou, J.; Nealey, P.; Wang, K. Metal Nanodot Memory by Self-Assembled Block Copolymer Lift-Off. Nano Lett. 2010, 10, 224-229. (24) Hu C.-W.; Chang, T.-C.; Tu, C.-H.; Huang, Y.-H.; Lin, C.-C.; Chen, M.-C.; Huang, F.-S.; Sze, S.- M.; Tseng, T.-Y. High Density Ni Nanocrystals Formed by Co-evaporating Ni and SiO2 Pellets for the Nonvolatile Memory Device Application.Electrochem. Solid- State Lett. 2010, 13, H49 –H51



(25) Chen, S.-C.; Chang, T.-C.; Hsieh, C.-M.; Li, H.-W.; Sze, S.-M.; Nien, W.-P.; Chan, C.-W.; Yeh (Huang), F.-S.; Tai, W.-H. Formation and Nonvolatile Memory Characteristics of W Nanocrystals by Insitu Steam Generation Oxidation.Thin Solid Films (2010), 519, 1677 –1680 (26) Yeh, P.-H.; Yu, C.-H.; Chen, L.-J.; Wu, H.-H.; Liu, P.-T.; Chang, T.-C. Low-power Memory Device with NiSi2 Nanocrystals Embedded in Silicon Dioxide Layer. Appl. Phys. Lett. 2005, 87, 193504 (27) Lin, Y.-H.;Chien, C.-H.; Lin, C.-T.; Chang, C.-H.; Lei, T.-F. High-Performance Nonvolatile HfO2 Nanocrystal Memory.IEEE Electron. Dev. Lett. 2005, 26, 154 – 156 (28) Yang, S.-M.; Chien, C.-H.; Huang, J.-J.; Lei, T.-F. Nonvolatile Flash Memory Devices Using CeO2 Nanocrystal Trapping Layer for Two-Bit per Cell Applications.Japanese J. Appl. Phys.2007, 46, 3291 – 3295 (29) Khosla, R.; Rolseth, E. G.; Kumar, P.; Vadakupudhupalayam, S. S.; Sharma, S. K.; Schulze, J. Charge Trapping Analysis of Metal/Al2O3/SiO2/Si, Gate Stack for Emerging Embedded Memories. IEEE Trans. On Dev. and Mater. Reliability. 2017, 17, 80-89 (30) Spassov, D.; Paskaleva, A.; Krajewski, T. A.; Guziewicz, E.; Luka, G. Hole and electron trapping in HfO2/Al2O3 nanolaminated stacks for emerging nonvolatile flash memories. Nanotechnol. 2018, 29, 505206 (31) De Blauwe, J.; Ostraat, M.; Green, M.-L.; Weber, G.; Sorsch, T.; Kerber, A.; Klemens, F.; Cirelli, R.; Ferry, E.; Grazul, J.-L.; Baumann, F.; Kim, Y.; Mansfield, W.; Bude, J.; Lee, J.-T.-C.; Hillenius, S.-J.; Flagan, R.-C.; Atwater, H.-A. A Novel, Aerosol Nanocrystal Floating-gate Device for Non-volatile Memory Applications. IEEE Electron. Dev. Meeting. 2000, 683 – 686 (32) Lee, C.; Meteer, J.; Narayanan, V.; Kan, C.-E. Self-Assembly of Metal Nanocrystals on Ultrathin Oxide for Nonvolatile Memory Applications. J. Electron. Mater. 2005, 34, 1 – 11. (33) Min, K.; Atwater, H. Ultrathin pseudomorphic Sn/Si and SnxSi1-x/Si heterostructures. Appl. Phys. Lett. 1998, 72(15), 1884. (34) Li, H.; Chang, C.; Chen, T.; Cheng, H.; Shi, Z.; Chen, H. Characteristics of Sn segregation in Ge/GeSn heterostructures. Appl. Phys. Lett. 2014, 105, 151906. (35) Ploog, K.; Fischer, A. Surface Segregation of Sn During MBE of N-type GaAs Established by SIMS and AES. J. Vacuum Science and Technol. 1978, 15(2), 255. (36) Liu, F. Self-Assembly of Three-Dimensional Metal Islands: Nonstrained versus Strained Islands. Phys. Rev. Lett. 2002, 89, 246105. (37) Lee, C.; Kwon, J.-H.; Lee, J.-S.; Kim, Y.-M.; Choi, Y.; Shin, H.; Lee, J.; Sohn, B.-H. Nonvolatile Nanocrystal Charge Trap Flash Memory Devices Using a Micellar Route to Ordered Arrays of Cobalt Nanocrystals. Appl. Phys. Lett. 2007, 91, 153506. (38) Kukli, K.; Ritala, M.; Sundqvist, J.; Aarik, J.; Lu, J.; Sajavaara, T.; Leskelä, M.; Hårsta, A.; Properties of hafnium oxide films grown by atomic layer deposition from hafnium tetraiodide and oxygen. J. Appl. Phys. 2002, 92, 5698 - 5703


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Figure 1

Figure 1. Scanning electron microscope (SEM) images of Sn NCs on (a) HfO2/Si (001), (b) Al2O3/Si (001), and (c) Si (001) surfaces. Glancing incidence X-ray diffraction data collected from the (uncapped) layer of Sn-NCs, self-assembled on (d) HfO2/Si(001) and (e) Al2O3/Si(001), revealing reflections due to -Sn. Also shown is the ICDD XRD data (Ref. Code: 00-004-0673) of -Sn, for comparison. The corresponding atomic force microscope images are shown in the insets.


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Figure 2

Figure 2. (a) Cross-sectional transmission electron micrograph of Sn-NCs embedded between a HfO2 tunnel-oxide and the Al2O3control oxide. (b) A close-up view of one of the Sn-nanocrystals. (c) A section of the image in (a), showing the area over which elemental maps were recorded by energy-dispersive Xray analysis. (d), (e), (f) Elemental maps corresponding to Sn, Al, and Hf, respectively, recorded from the area depicted in (c).



Figure 3


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Figure 3. (a) 3D SKPM image of an Al2O3 (20-nm)/Sn-NC/ Al2O3 (4-nm)/p-Si (001) stack, programmed and erased within a single cell. The programmed area is1 × 1m2, while the erased area is 0.5 × 0.5m2(b) – (d) 3D SKPM maps of programmed (left) and erased (right) cells (of area 1 × 1m2), realized at arbitrary positions of the sample.



Figure 4

Figure 4. Plot of the normalized capacitance versus voltage applied to the top gates of the MOS memory device of (a) sample A and (b) sample B, recorded at 10 kHz and 100 kHz. The C-V characteristics (measured at 10 kHz) of a sample consisting of 55 nm of Al2O3 grown directly on the p-Si(001) substrate, and without Sn nanocrystals embedded in it, is also shown (in grey) in the main panel (along with a closeup in the inset). (c) Schematic energy band diagram of the MOS-memory under flat-band conditions, for sample A (left) and sample B (right). The b(d) Variation of the memory window (Δ𝑉𝐹𝐵) with the bias range, for both samples.


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Figure 5

Figure 5. Charge retention characteristics of the MOS memory device of (a) sample A and (b) sample B, extrapolated to show the charge loss after 10 years. Endurance characteristics of (c) sample A and (d) sample B.



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Self-Assembled Sn nanocrystals as the floating gate of non

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