Silica Core

May 9, 2007 - Moreover, the as-synthesized core−shell nanowires, with inherent gate-dielectric shell layer, provide a new opportunity for efficientl...
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J. Phys. Chem. C 2007, 111, 7661-7665

7661

Synthesis and Device Integration of Carbon Nanotube/Silica Core-Shell Nanowires Xianglong Li, Yunqi Liu,* Lei Fu, Lingchao Cao, Dacheng Wei, Yu Wang, and Gui Yu Center for Molecular Science, Institute of Chemistry, Chinese Academy of Sciences, Beijing 100080, People’s Republic of China ReceiVed: December 26, 2006; In Final Form: February 1, 2007

On the basis of high-density and uniform assembly of Au nanoparticles on carbon nanotube (CNT) surface and subsequently the convenient chemical vapor deposition technique, the nanowires with carbon nanotube core and uniform silica insulating shell were controllably synthesized and then efficiently integrated into top-gated FETs. The study provides a simpler, lower-cost, and more controllable methodology for the uniform coating/functionalizing of CNTs with shell layer materials such as oxide gate-dielectrics. Moreover, the assynthesized core-shell nanowires, with inherent gate-dielectric shell layer, provide a new opportunity for efficiently and conveniently fabricating of top-gated CNTFETs and other vertical surround-gated CNTFET devices, thus making for the development of more highly integrated circuits.

Introduction Carbon nanotubes (CNTs) with their exceptional structural and electronic properties such as ballistic transport over length scales of several hundred nanometers are very promising for potential applications in nanoscale systems including electronic nanodevices.1 Since the first demonstration of carbon nanotube field-effect transistors (CNTFETs) in 1998,2,3 tremendous research has led to a great improvement of device configuration and their transport properties.4 Simultaneously, the extreme sensitivity of CNTs or CNTFETs to their chemical environment is also documented commendably, and is a major obstacle in the field of nanotube device fabrication.5,6 Of the various possible geometries for CNTFETs, top-gated CNTFETs are the most promising not only due to their environment-independent merit, but also due to the feasibility of independently switching of individual device on the same substrate as well as the promise of higher-density integrating of a great deal of devices. Accordingly, considerable efforts7-9 have been made in recent years to devise top-gated CNTFET devices with different gatedielectric materials. On the other hand, the chemical functionalization of the open ends, the exterior walls, and the interior cavity of the CNTs are expected to play a vital role in the tailoring of their electronic properties and sensing sensitivities, the hierarchical buildingup of functional CNTs-based architectures, and the engineering of CNTs-based devices.10,11 Among them, however, since the sidewall of carbon nanotubes is chemically inert,12 the uniform and controllable coating or functionalizing of the nanotubes for developing and studying such CNT-based devices still presents a challenge. To date, many efforts to fabricate CNT-based core/ shell nanowire heterostructures for which CNTs serve as templates/cores have just begun. Wang et al.13 reported a chemical reduction route to prepare CNT/CdS core-shell nanowires with an enhanced surface photovoltage response. Recently we have developed a supercritical-solution route to coat CNTs with a nanometer-scale alumina gate-dielectric, subsequently constructing the top-gated CNTFETs.14 Further* Corresponding author. Tel: 86-10-62613253. Fax: 86-10-62559373. E-mail: [email protected].

more, on the basis of the colloidal method, CNT nanowires with silica shells have also been pioneeringly researched by Seeger et al.15,16 Such coating/functionalizing may meet the demand for future application of nanodevices, which allows the further miniaturization of integrated electronic and photoelectronic devices. In the study reported here, the nanowire heterostructures with CNT core and silica insulating shell were controllably synthesized and then efficiently integrated into top-gated FET devices. As illustrated in Figure 1, the method for synthesizing the nanowire heterostructures includes the high-density and uniform assembly17 of Au nanoparticles on CNT surface (a) and the subsequent uniform coating of silica insulating layer based on the convenient chemical vapor deposition (CVD) technique (b). The thickness of the silica shell could be controlled by regulating the heating time in CVD process for uniform coating. The methodology is simpler, lower-cost, and more controllable and efficient for the uniform coating/functionalizing of CNTs with shell layer materials such as oxide gate-dielectrics. Moreover, the as-synthesized core-shell nanowires, with inherent gatedielectric shell layer, could be conveniently integrated into topgated CNTFETs and/or other vertical surround-gated CNTFET devices,18 thus making for the development of more highly integrated circuits. Experimental Section The preparation of pristine CNTs was analogous to that reported in the literature,19 except that the Ar-H2 atmosphere was replaced by H2 gas. A flow of H2 (40 cm3 min-1) was introduced into the quartz tube during heating. After the central region of the furnace reached 950 °C, a quartz boat containing 0.05 g of iron(II) phthalocyanine was promptly placed in the 550 °C region of the furnace, and maintained 5-10 min. The CNTs grew in a direction normal to the substrate surface. Following our reported method,17 the resulting CNTs (2 mg) were sonicated in 2 mL toluene. Then 0.5 mL of a toluene solution of Au nanoparticles (Au NPs) prepared according to the literature20 was added in, and the mixture was shaken for 2 min. After centrifugation, the black solid (CNT-Au NP hybrids) was extensively washed with toluene until the washings

10.1021/jp0689417 CCC: $37.00 © 2007 American Chemical Society Published on Web 05/09/2007

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Figure 2. Typical TEM image of CNT-Au NP hybrids; the inset indicates SEM image of pristine CNTs.

Figure 1. Scheme of the preparation of CNT/silica core-shell nanowires.

appeared colorless. In a typical process for synthesizing CNT/ Silica core-shell nanowires, a certain quantity of CNT-Au NPs was deposited from an ethanol solution onto a clean silicon substrate, which was placed in the inner center of a clean quartz tube. Then the quartz tube was inserted into a tubular furnace and gradually moved until the silicon substrate with CNT-Au NPs was in center region of the furnace. After that, a known quantity (0.3 mL) of silicon tetrachloride (SiCl4, Acros, 99.8%) was injected into a quartz boat, which was then located at one end of the quartz tube (outside the furnace). A mixed flow of H2 (80 sccm) and Ar (80 sccm) gas was used as carrier gas, which diluted and transferred SiCl4 vapor through the quartz reactor. After the center region of the furnace was heated to the predetermined temperature of 800 °C and maintained for 5-30 min, the mixed flow was turned off. Herein, the residual trace amounts of oxygen in the CVD system was incorporated into the growth of silica shell. As the system was cooled to room temperature, the resulting product was ultrasonically dispersed in a gold etchant solution (TFA, Transene Co.) to remove dissociative Au particles or impurities, if there are. Then the product was collected by filtration, repeatedly rinsed with deionized water and ethanol. Device fabrication proceeded as follows. After mild sonication (40 kHz, 5 min), the as-synthesized CNT/silica core-shell nanowires were dispersed from an ethanol solution onto a 400 nm thick thermally oxidized silicon surface between Au/ Ti pads. Using a Strata DB235 focused-ion-beam (FIB) etching and deposition system (FEI Co.), the surface was visualized using a low beam current (1 pA) in search of the nanowires with peeled ends or discontinuous shells. Once found, one 100 nm wide Pt lead as gate (G) electrode was patterned on the silica coating and another two as source (S) and drain (D) electrodes were patterned on bare ends of the nanowire. A 30 kV Ga+ beam at 10 pA was used to decompose trimethylcyclopentadienylplatinum[CH3C5H4Pt(CH3)3] into a predetermined bridging lead. Herein, to avoid significant damage or complete destruction of the sample by the massive Ga+ ions,21 we kept the device length at 3.0 µm or greater, and the Pt deposition time around the predetermined regions of the sample was less than 30 s. The electrical properties were measured using a Wentworth Company MP1008 probe station and a Hewlett-

Figure 3. Representative SEM image of CNT/silica core-shell nanowires; the white arrows indicate blank and clean substrate.

Packard 4140B semiconductor parameter analyzer at room temperature in air. Results and Discussion Figure 2 shows a representative transmission electron microscopy (TEM; JEOL 2010 operating at 200 kV) image of the CNT-Au NP hybrids. Compared with the pristine multiwalled CNTs (MWCNTs) (50 nm, average diameter) bearing the clean surface as exhibited in the inset of Figure 2, the assembled Au nanoparticles (3.9 nm, average size) with spatially isolated feature uniformly decorated/packed the walls of CNTs with high density. Employing the convenient CVD technique and the CNT-Au NP nanohybrids as models, we further obtained the CNT/silica core-shell nanowire heterostructures as shown in Figure 3. These nanowires, with the average diameter of ca. 210 nm, take on the smooth and clean surface. Notably, the blank substrate shown by the arrows in Figure 3 is still clean after the CVD process, which implies the CVD process of silica is guided by CNT-Au NP hybrids as models. Furthermore, these nanowires are unattached each other, which makes for the individual expression of these nanowire heterostructures in two- or three-terminals electronic devices. Figure 4a,b shows typical transmission electron microscopy (TEM) image of the CNT/Silica core-shell nanowires. Consistent with the results evaluated from the above SEM image, the average thickness of the shell layer and inner core determined from TEM images are about 80 and 50 nm, respectively; the thickness of the shell material is essentially uniform. Notably, some of the CNT/silica core-shell nanowire bodies bear the peeled ends and/or discontinuous shell regions

Carbon Nanotube/Silica Core-Shell Nanowires

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Figure 5. (a) SEM image of the disordered silica thin films obtained employing pristine CNT as a model in CVD process. (b) SEM image of the mixture of the dissociative Au aggregates and the bare nanotubes obtained under the same CVD condition but without the absence of SiCl4.

Figure 4. (a, b) TEM images of CNT/silica core-shell nanowires. Several uncoated areas of the CNT are indicated by arrows. (c) HRTEM image of the nanowire. (d) EDX spectrum of CNT/silica nanowires. Inset: the SAED pattern of the nanowires. (e) A section of CNT/silica nanowires obtained by heating for 20 min in CVD process. (f) CNT/ silica nanowires obtained by heating 15 min in CVD process. (g) CNT/ Silica core-shell nanowire with both peeled ends.

as indicated by white arrows in Figure 4a. Figure 4c shows a high-resolution TEM (HRTEM; Tecnai F30 operating at 200 kV) image from the rectangular region of the nanowire in Figure 4b. It clearly illustrates a silica shell layer and the wellorderly carbon layer fringes of CNT as an inner core (ca. 0.34 nm separations). The outer shell of the nanowire, which contains Si and O (as well as C, which presumably arises from the inner CNT as the core of the nanowire), is confirmed as silica by energy-dispersive X-ray (EDX) analysis (Figure 4d). The inset of Figure 4d shows the selected area electron diffraction (SAED) pattern of the CNT/silica core-shell nanowire. Except for the (002) reflection of graphite from the core of the nanowires, the SAED pattern does not show any sets of single-crystal electron diffraction spots. The absence of the spots indicates that the silica shell is amorphous. Through regulating the heating time in the CVD process for CNT coating, we can conveniently control the thickness of the shell layer. When the heating time is 30 min, the average thickness of the shell is 80 nm (Figure 4a,b); if the heating time is decreased to 20 min,

the shell thickness is ca. 55 nm (Figure 4e); and if the heating time is 15 min, the shell thickness is 40 nm (Figure 4f). In addition, the CNT/Silica core-shell nanowire with both peeled ends (Figure 4 g) can be obtained by our method, which more facilitates the direct fabrication of top-gated FET devices as shown below. We further carried out control experiments to prepare CNT/ silica core-shell nanowires under the same CVD conditions with pristine CNTs as models. As demonstrated in Figure 5a, which shows the typical results obtained by employing pristine CNTs, the disordered silica thin films embedded with pristine CNTs were obtained. Although the detailed mechanism of coating is not known at present, the uniform Au nanoparticles on CNT-Au NP hybrids are suggested to play a guiding role for uniform coating, which seems to be relevant to the function of Au nanoparticles in silicon nanowires growth,22 and more similar to the role of nitro groups or DNA molecules on CNTs during atomic layer deposition of HfO2-gate dielectrics.23,24 In another experiment under the same CVD conditions but without the presence of SiCl4, the dissociative Au nanoparticles/ aggregates with different diameter coexisted with the bare nanotubes (Figure 5b), confirming that the silica-shell precursor is SiCl4, not silicon substrate25 in our CVD conditions. Moreover, combined with the above EDX results that Au element is absent in CNT/silica core-shell nanowires, it is apparent that the Au component of CNT-Au NP hybrids, in form of nanoparticles/aggregates, is dissociated from the nanowire heterostructures during our CVD process. FETs were then prepared using individual CNT/silica coreshell nanowire. As shown in a schematic illustration of the

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Li et al. at ambient conditions for a typical top-gated FET device made using this method. The ID decreases with increasing VGS, which indicates a p-type FET device, and is consistent with previous observations.14,27 As exhibited in Figure 6c, showing the transfer curve of the device (with 40 nm silica gate-dielectric shell layer) at a fixed VDS of -0.5 V, the drain current changes from 10-6 to 10-8 A as the VGS changes from -0.75 to 0.75 V. Notably, the drain current exceeds gate leakage current (ca. 10-12 A) by a factor of 104, which implies that silica shell layer provides good gate insulation. The subthreshold swing, defined as S ) ∂VGS/∂(log ID), is a key parameter to transistor miniaturization.28 A small S is desired for low threshold voltage and low-power operation for FETs scaled down to small sizes. We extract subthreshold swings for all of our p-type FETs in the S ) 540850 mV per decade range for VDS ) -0.5 V. The relatively improved electrical properties in our MWCNT-based devices have been achieved by uniform and compact gate-dielectric coating and subsequent top-gate-configuration design. At the same time, it is very possible that the S/D Pt electrodes were patterned/connected to two different outmost24 layers (with either metallic and semiconducting, or semiconducting and semiconducting properties, respectively) of MWCNT as the nanowire core and/or the surfaces of the nanotube are mildly oxidized/ deformed under our CVD conditions. As a result of intershell transfer and/or structural deformation,3 the silica-coated MWCNTs exhibit distinct p-type characteristics. Combined with the more improvement of device configuration, such convenient shellassembling technique should facilitate the use of MWCNTs as transistor building blocks in many fields including the control of macroscopic devices such as electromotors where larger currents have to be switched. Conclusion

Figure 6. (a) SEM image of an example of CNT/silica nanowire patterned with Pt leads. Inset: a schematic device structure of nanowirebased FETs with intrinsic silica shell as the gate dielectric. (b) ID-VDS characteristics at various gate voltages (VGS). VGS’s for each ID-VDS curve are indicated. (c) ID with changing VGS at VDS ) -0.5 V. The solid lines are meant as guides to the eyes.

fabricated FET devices (inset of Figure 6a), a MWCNT bridging the source (S) and drain (D) electrodes behaves as the active channel of FET, while the silica shell deposited with a gate (G) electrode acts as dielectric layer of FET. An example of the resulting FET device with three Pt leads patterned on the bare ends and shell layer of a core-shell nanowire using a FIB system14 is shown in Figure 6a. In our electrical transport studies on as-fabricated FET devices, we have measured many individual nanowires and find two types of behavior at room temperature: one is the metallic variety resembling those of the previously reported tubes without dependence on the gate voltage,26 the other is p-type FET properties. Herein, we present measurements on the second type of sample. Figure 6b shows a set of current versus source-drain bias curves (ID-VDS) curves under various gate voltages (VGS)

To summarize, based on the high-density and uniform assembly of Au nanoparticles on CNT surface and subsequently the convenient chemical vapor deposition technique, the nanowire heterostructures with carbon nanotube core and uniform silica insulating shell were controllably synthesized and then efficiently integrated into top-gated FET devices. Although our initial efforts have focused on silica and MWCNTs, the methodology is simpler, lower-cost, and more controllable and efficient for the uniform coating/functionalizing of CNTs with different shell layer materials such as oxide gate-dielectrics. It should be further noted that the as-synthesized core-shell nanowires, with inherent gate-dielectric shell layer, could be conveniently integrated into top-gated CNTFETs and other electronic devices with specific geometries such as vertical surround-gated CNTFETs, thus making for the development of more highly integrated circuits. Acknowledgment. The authors gratefully acknowledge financial supports from the National Natural Science Foundation of China (20573115, 90206049, 20472089, 20421101, 50673093), the Major State Basic Research Development Program and the Chinese Academy of Sciences References and Notes (1) Dresselhaus, M. S.; Dresselhaus, G.; Avouris, Ph. Carbon Nanotubes: Synthesis, Structure, Properties and Applications; Springer-Verlag: New York, 2001. (2) Tans, S. J.; Verschueren, A. R. M.; Dekker, C. Nature 1998, 393, 49. (3) Martel, R.; Schmidt, T.; Shea, H. R.; Hertel, T.; Avouris, Ph. Appl. Phys. Lett. 1998, 73, 2447. (4) Dai, H. Acc. Chem. Res. 2002, 35, 1035.

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