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Silicon Nanowire Field Effect Transistor Sensors with Minimal Sensor-to-Sensor Variations and Enhanced Sensing Characteristics Sufi Zafar,* Christopher D’Emic, Ashish Jagtiani, Ernst Kratschmer, Xin Miao,† Yu Zhu, Renee Mo, Norma Sosa, Hendrik Hamann, Ghavam Shahidi, and Heike Riel IBM T.J. Watson Research Center, Yorktown Heights, New York 10598, United States † IBM Research, 257 Fuller Road, Albany, New York 12203, United States S Supporting Information *
ABSTRACT: Silicon nanowire field effect transistor (FET) sensors have demonstrated their ability for rapid and label-free detection of proteins, nucleotide sequences, and viruses at ultralow concentrations with the potential to be a transformative diagnostic technology. Their nanoscale size gives them their ultralow detection ability but also makes their fabrication challenging with large sensor-to-sensor variations, thus limiting their commercial applications. In this work, a combined approach of nanofabrication, device simulation, materials, and electrical characterization is applied toward identifying and improving fabrication steps that induce sensor-to-sensor variations. An enhanced complementary metal-oxide-semiconductor-compatible process for fabricating silicon nanowire FET sensors on 8 in. silicon-on-insulator wafers is demonstrated. The fabricated nanowire (30 nm width) FETs with solution gates have a Nernst limit subthreshold swing (SS) of 60 ± 1 mV/decade with ∼1.7% variations, whereas literature values for SS are ≥80 mV/decade with larger (>10 times) variations. Also, their threshold voltage variations are significantly (∼3 times) reduced, compared to literature values. Furthermore, these improved FETs have significantly reduced drain current hysteresis (∼0.6 mV) and enhanced on-current to off-current ratios (∼106). These improvements resulted in nanowire FET sensors with the lowest (∼3%) reported sensor-to-sensor variations, compared to literature studies. Also, these improved nanowire sensors have the highest reported sensitivity and enhanced signal-to-noise ratio with the lowest reported defect density of 2.1 × 1018 eV−1 cm−3, in comparison to literature data. In summary, this work brings the nanowire sensor technology a step closer to commercial products for early diagnosis and monitoring of diseases. KEYWORDS: CMOS-compatible fabrication, sensor-to-sensor variations, silicon nanowire field effect transistor sensors, potentiometric sensors, pH sensing ilicon nanowire field effect transistor (FET) sensors have demonstrated their ability for fast, high sensitivity and label-free detection of proteins, nucleotide sequences, viruses, cellular signaling, and biochemical reactions.1−10 These nanowires FET sensors offer several significant advantages over large-area FET sensors. As discussed previously,4,11 nanowire FET sensors with their nanoscale size are particularly well suited for biomolecule detection at ultralow concentrations. Also, their reduced footprint makes them suitable for highdensity sensor arrays, thus enabling multiplexing from a minute sample volume.10 Furthermore, these miniaturized sensors have low power and voltage requirements and are, therefore, well suited for portable diagnostic applications such as lab-ona-chip.4 Another advantage of these nanoscale sensors is their reduced RC time constants, thus enabling observations of
molecular binding kinetics at faster rates.4 Although nanowire FET sensors have the potential to be a transformative diagnostic technology, their commercial applications remain limited due to large fabrication-induced sensor-to-sensor variations that cause reproducibility and repeatability issues.8−10,12,13 The silicon nanowire FET sensor detection ability increases with decreasing nanowire width at ultralow concentrations.4,11 However, as the nanowire width decreases, sensor-to-sensor variations increase due to fabrication challenges at the
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© 2018 American Chemical Society
Received: February 19, 2018 Accepted: June 22, 2018 Published: June 22, 2018 6577
DOI: 10.1021/acsnano.8b01339 ACS Nano 2018, 12, 6577−6587
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Cite This: ACS Nano 2018, 12, 6577−6587
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Figure 1. Device simulation results for nanowire SOI p-type FETs with long channels and trigates. (a) Schematics showing nanowire structures with uniform and varying gate dielectric thicknesses (buried oxide and silicon substrate not shown; drawings are not to scale). (b) Using schematics shown in (a), simulated dependence of drain current (ID) on the gate voltage; simulations assume zero trap density at the silicon/oxide interface and SS is the subthreshold swing. (c) Simulated dependence of threshold voltage (VT) on nanowire width for nanowires with 30 nm height, 3.2 nm uniformly thick gate dielectric, and silicon channel dopant density of 5 × 1015 cm−3.
where ID is the drain current, Gm is the transconductance, δVψ is the sensing surface potential change, and SS is the subthreshold swing in the subthreshold region. The SNR per unit bandwidth can be written as15,16
nanoscale.9,10,12,13 To address this important issue, there have been several fabrication studies with the majority of them focused on the top-down fabrication process.3,5,9,10,12,13 Data analysis methods also have been proposed for reducing the impact of sensor variability.8,10 Despite these research efforts, the nanowire FET sensor variability remains an important issue. In this study, a combined approach of nanofabrication, device simulation, materials, and electrical characterization is applied toward identifying and improving key processing steps that cause variations and degradation in silicon nanowire FET sensors. The study identifies defects near the silicon/gate dielectric interface and thickness uniformity of the gate dielectric layer over the three-dimensional nanowires as major factors causing sensor variations and degradation in nanowire FET sensors. Based on these identifications, special efforts are focused toward the formation of silicon nanowires and gate dielectric stacks that results in optimal interface and gate dielectric layers remaining uniformly thick over nanowires during subsequent processing steps. An improved complementary metal-oxide-semiconductor (CMOS)-compatible topdown process for fabricating silicon nanowire FET sensors on 8 in. silicon-on-insulator (SOI) wafers is demonstrated. The fabricated FET sensor consists of a silicon nanowire (width = height = 30 nm; length 5 μm) forming the channel, a dual layer stack of SiO2/HfO2 as the gate dielectric with HfO2 as the sensing surface, and an aqueous solution forming the top trigate. A total of 140 different sensors are characterized for statistical analysis, and the data are compared with those in the literature. The comparison shows that the improved nanowire FET sensors not only exhibit the smallest sensor-to-sensor variations despite having the narrowest width but also have the most enhanced sensor performance.
SNR per volt = Gm / SI(1 Hz)
where SI(1 Hz) is the ID noise power density at 1 Hz. From eqs 1 and 2, SS and ID noise power density are two critical FET parameters impacting sensing characteristics. These parameters predominantly depend on trap defects at and near the silicon/ gate dielectric interface,16,17 and therefore special fabrication efforts will be focused toward reducing these defects. Since these defect densities depend on the silicon/gate dielectric interface quality, processing steps that form nanowires and the gate dielectric are important for reducing both variations and degradation in SS and ID noise power density of FETs. In this study, the nanowire length is set to 5 μm to minimize short channel induced SS degradations. To gain further insights into factors impacting sensor-to-sensor variations and degradation, device simulations are performed for long channel nanowire FET sensors (see Methods for simulation details). Figure 1(a) shows the schematics for nanowire FET structures used in the simulation that explores the impact of variations in the gate dielectric thickness. Simulated results of Figure 1(b) show that SS degrades when the gate dielectric thickness varies over the three-dimensional nanowire: SS degrades by 5% when the gate dielectric is 15% thicker near the nanowire base than at the top. Hence, the gate dielectric thickness variation over a nanowire would degrade SS and would also induce SS variability if this thickness variation is different across the wafer. Figure 1(b) shows device simulation results for the threshold voltage (VT) dependence on the nanowire width for long channel devices: VT varies rapidly for nanowire width 2 nm, the HfO2 dielectric constant εHfO2 = 18 and SiO2 thickness of 1.5 nm are estimated from the linear fit (dashed line), thereby indicating that the HfO2 film is continuous with minimal SiO2 growth. Hence, the target HfO2 thickness = 3 nm is selected since thicker HfO2 is undesirable due to increasing dielectric relaxation currents and charge trapping that induce increased signal drifts at short times.21,25 Figure, 2(b) shows that the hysteresis (ΔVHys) decreases with increasing SiO2 thickness; ΔVHys is the flatband voltage shift during the double sweep of capacitance versus voltage curves. Since hysteresis increases with increasing interfacial trap density, the target dSiO2 = 2 nm with ΔVHys ≈ 0 mV is selected.
Silicon Nanowire FET Fabrication Improvements. Silicon nanowire p-type FETs are fabricated on commercially available 8 in. SOI wafers with 145 nm thick buried oxide and a 55 ± 0.2 nm thick top silicon layer of low (∼5 × 1015 cm−3) doping. Figure 3 illustrates the six sequential processing modules for fabricating silicon nanowire FET sensors. This section focuses on fabrication improvements, while processing details are discussed in the Methods section. In module I, the nanowire height is defined by etching back of the top silicon layer (SOI). The main challenge is to ensure that the etched SOI thickness is uniform to achieve minimal 6579
DOI: 10.1021/acsnano.8b01339 ACS Nano 2018, 12, 6577−6587
Article
ACS Nano
Figure 4. Silicon nanowire FET images before and after fabrication improvements. (a) Top-down SEM images of a silicon nanowire before (left) and after (right) nanowire sidewall roughness minimization. (b) Cross-sectional TEM images of silicon nanowire sidewalls before and after sidewall roughness minimization and damaged nanowire surface removal. (c) Cross-sectional TEM image of a nanowire with a SiO2/ HfO2 gate dielectric showing additional nonuniform SiO2 growth that occurs during the dopant activation anneal; the image is recorded before the SiN hard mask optimization. (d) Top-down SEM images of FETs with electron-beam lithography alignment errors, where the patterned HfO2/SiN stacks are completely (left) and partially (right) misaligned with respect to underlying silicon nanowires. (e) Top-down SEM images of three randomly selected patterned HfO2/SiN stacks with minimal misalignment after the electron beam lithography exposure optimization. (f) Cross-sectional TEM image showing a nanowire FET with residual SiN on both sides of a nanowire. (g) Cross-sectional TEM image of a SiO2/HfO2-covered silicon nanowire, where part of the HfO2 layer (as indicated by the arrow) is removed due to the overetching of the SiN hard mask. (h) Cross-sectional TEM image of a silicon nanowire FET fabricated using the improved process. (i) Cross-sectional TEM image of the Si/SiO2 interface of a nanowire FET fabricated using the improved process.
nm (see Figure S3 of Supporting Information). Figure 4(a) shows scanning electron microscopy (SEM) images of silicon nanowires measured before and after resist and electron beam dose optimization. Using these top-down SEM images, line edge roughness (LER) is estimated using commercially available SEM image analysis software:30 LER decreases from 3.43 nm to 2.40 nm after optimization. In the present study, reactive ion etching (RIE) is chosen over a wet etch because RIE is an anisotropic process with vertical sidewalls, well suited for transferring nanometer-scale features. Also, wet etches form trapezoidal-shaped nanowires with tapering silicon sidewalls with (111) silicon surface orientation that have lower mobility and higher interfacial defect densities in comparison to dryetched vertical sidewalls with (110) orientation. Furthermore, wet etching results in etching agent induced contamination, resulting in poor device reproducibility. Since RIE damages the silicon nanowire surfaces, steps are included to minimize and remove the etch-induced damage. Toward the end of the etching step, the gas mixture of HBr, helium, and O2 is further diluted by increasing helium percentage to reduce the mean ion energy, thereby minimizing plasma-induced damage to the silicon surface. Also, after the etch completion, the damaged nanowire surface layer is removed by thermal oxidization at
nanowire surface area variations. The initial SOI thickness of 55 ± 0.2 nm is thinned to 31 ± 0.9 nm, as estimated from 49point ellipsometry measurements across the wafer (see Figure S2 in Supporting Information). In module II, the main challenge is to form threedimensional silicon nanowires with minimal sidewall roughness and etch-induced damage, essential for achieving an optimal Si/SiO2 interface with negligible defect densities. Since both electron beam lithography (EBL) and etch require higher levels of process control and optimization at nanoscale (
