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Conduction mechanisms at interface of AlN/SiN dielectric stacks with AlGaN/GaN heterostructures for normallyoff high electron mobility transistors: correlating device behavior with nanoscale interfaces properties Giuseppe Greco, Patrick Fiorenza, Ferdinando Iucolano, Andrea Severino, Filippo Giannazzo, and FABRIZIO ROCCAFORTE ACS Appl. Mater. Interfaces, Just Accepted Manuscript • DOI: 10.1021/acsami.7b08935 • Publication Date (Web): 18 Sep 2017 Downloaded from http://pubs.acs.org on September 22, 2017

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ACS Applied Materials & Interfaces

Conduction mechanisms at interface of AlN/SiN dielectric stacks with AlGaN/GaN heterostructures for normally-off high electron mobility transistors: correlating device behavior with nanoscale interfaces properties

Giuseppe Greco1,*, Patrick Fiorenza1, Ferdinando Iucolano2, Andrea Severino2, Filippo Giannazzo1 and Fabrizio Roccaforte1 1

Consiglio Nazionale delle Ricerche – Istituto per la Microelettronica e Microsistemi (CNR-IMM), Strada VIII, n. 5 – Zona Industriale, 95121 Catania, Italy 2

STMicroelectronics, Stradale Primosole 50, 95121 Catania, Italy *

Corresponding author : [email protected]

Abstract In this work, the conduction mechanisms at the interface of AlN/SiN dielectric stacks with AlGaN/GaN heterostructures have been studied combining different macroscopic and nanoscale characterizations on bare materials and devices. The AlN/SiN stacks grown on the recessed region of AlGaN/GaN heterostructures have been used as gate dielectric of hybrid metal-insulatorsemiconductor high electron mobility transistors (MISHEMTs), showing a normally-off behaviour (Vth=+1.2 V), high channel mobility (204 cm2V-1s-1), and very good switching behaviour (ION/IOFF current ratio of 5-6×108 and sub-threshold swing of 90 mV/dec). However, the transistors were found to suffer from a positive shift of the threshold voltage during subsequent bias sweeps, which indicates electron trapping in the dielectric stack. To get a complete understanding of the conduction mechanisms and of the charge trapping phenomena in AlN/SiN films, nanoscale current and capacitance measurements by conductive atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) have been compared with a macroscopic temperature-dependent characterization of gate current in MIS capacitors. The nanoscale electrical analyses showed the presence of a spatially uniform distribution of electrons trapping states in the insulator, and the occurrence of a density of 7×108 cm-2 of local and isolated current spots at high bias values. These nanoscale conductive paths can be associated to electrically active defects responsible of the trapassisted current transport mechanism through the dielectric, observed by the temperature dependent characterization of the gate current. The results of this study can be relevant for future applications of AlN/SiN bilayers in GaN hybrid MISHEMT technology.

Keywords: AlN/SiN, dielectric, AlGaN/GaN heterointerface, C-AFM, nanoscale 1 ACS Paragon Plus Environment


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I. INTRODUCTION Since more than two decades, high electron mobility transistors (HEMTs) based on AlGaN/GaN heterostructures are object of investigations. In fact, the wide band-gap and high critical electric field of the material, combined with the high sheet carrier density and mobility of the twodimensional electron gas (2DEG) at the AlGaN/GaN heterointerface, make GaN-based HEMTs excellent candidates for the next generation of high power and high frequency systems1. In recent years, the largest interest has been obviously focused on AlGaN/GaN heterostructures grown on large size and low cost Si substrates 2 , which can have bright perspectives for costcompetitive power devices in the medium-voltage (200-600V) consumer electronics market. In this context, the achievement of a normally-off operation is one of the most challenging aspects in GaNHEMT technology. In fact, for power switching devices, normally-off characteristics are strongly preferred to preserve the safe operation and the drive circuit simplicity in the system3,4. Different approaches have been proposed to modify the interfacial region below the metal gate in order to obtain normally-off AlGaN/GaN HEMTs, e.g., the recession of the AlGaN barrier layer 5 , the fluorine incorporation6,7, local surface oxidation processes8,9, the p-type (Al)GaN cap layer 10,11, etc. Moreover, combining the total recession of the AlGaN layer with a gate insulation allows to obtain a normally-off hybrid metal-insulator-semiconductor high electron mobility transistor (MISHEMT). In such a device, the normally-off operation is guaranteed by the MIS channel, while a low onresistance is obtained due to the presence of the 2DEG in the access regions12. Silicon dioxide (SiO2) has been first proposed as gate dielectric in GaN-based transistors12,13,14,15. Husna et al. 16 demonstrated a transconductance peak gm = 0.11 mS/mm and an RON as low as 0.4 mΩ·cm2. However, SiO2 can induce significant negative Vth shift as gate insulator in normallyon MISHEMT 17 , as well as trapping phenomena at the interfaces and Vth instability issues in normally-off hybrid devices18,19,20. Hence, the use of high permittivity materials, e.g., Al2O321,22, NiO23, HfO2 24, 25,26 , Ta2O527, CeO2 28 in GaN-transistors, has been also considered to obtain an efficient gate leakage current suppression, without compromising the transconductance. Although normally-off MISHEMTs with high channel mobility (225 cm2V-1s-1) and high threshold voltage (+2V) have been demonstrated using Al2O329, some works reported that a high interface trap density and large amounts of fixed charges can result in a degradation of the device channel mobility30,31. Moreover, in normally-off recessed MISHEMTs the threshold voltage instabilities often observed upon bias stress are typically correlated with the presence of defects at the interface or in the dielectrics19, or with bulk traps32 Due to their high chemical compatibility with the substrate, nitrides (e.g., AlN, SiN), can be promising gate materials for GaN-based transistors. In particular, aluminium nitride (AlN) with its 2 ACS Paragon Plus Environment

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wide band-gap (6.2 eV) and reduced lattice mismatch to GaN (~2.5%), represents an ideal candidate to be grown on the GaN channel. As an example, it has been demonstrated that introducing an AlN layer between Al2O3 and GaN can promote a sharp interface with low interface trap density and moderate Vth hysteresis33. A field-effect mobility of 165 cm2V-1s-1 and a high on/off drain current ratio of ~1010 have been obtained in this case. However, AlN suffer of a high susceptibility to chemical etch in basic solutions, often used during devices processing. On the other side, silicon nitride (SiN) has been used as gate dielectric in MISHEMTs to reduce the leakage current34,35. Using SiN as gate dielectric, Oka and Nozawa36 reached a Vth > 4 V and a maximum field effect mobility of 120 cm2V-1s-1. Moreover, both AlN and SiN showed interesting performances as passivation layer on AlGaN/GaN heterostructures, reducing surface states density and limiting current collapse effects37. Only recently, AlN/SiN bilayers were used in MISHEMTs both as gate dielectric and passivation layer, exhibiting good properties in terms of current voltage (I-V) characteristics, current collapse, and dynamic RON38. However, the conduction mechanisms at interfaces with AlN/SiN stacks and the related trapping phenomena, have been not discussed in detail and, hence, deserve deeper investigations both at a macroscopic level and at the nanoscale. In this context, high resolution electrical characterization techniques based on atomic force microscopy, such as conductive atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM), are the methods of choice for mapping the electrical properties of thin gate insulators at nanoscale level 39 . As an example, C-AFM has been employed in the past to characterize the spatial distribution of damage in the SiO2 gate insulator of Si MOSFETs subjected to different types of electrical stress, after wet etching of the top electrode to get access to the dielectric surface 40 . More recently, macroscopic scale gating by easily removable ionic liquid droplets and nanoscale current measurements by C-AFM were combined to elucidate the current transport mechanisms in transition metal oxides (TiO2)41. In other cases, scanning the bare surface of a fresh (as-grown) gate insulator with a biased conductive tip was used for electrical stressing of the insulator, and local current (or capacitance) measurements on the same scan area were employed to probe the effects of this stress42. In this work, AlN/SiN stacks grown on the recessed region of AlGaN/GaN heterostructures have been used as gate dielectric of hybrid MISHEMTs. The devices showed a high positive threshold voltage (Vth=+1.2 V), a high channel mobility (204 cm2V-1s-1), and a very good ION/IOFF current ratio (5-6×108 ). The transistors were affected from a positive Vth shift during subsequent bias sweeps, which indicates electron trapping in the dielectric stack. A comprehensive understanding of the conduction mechanisms and of the trapping phenomena was obtained by nanoscale current (CAFM) and capacitance (SCM) measurements on the bare surface of the AlN/SiN insulator, which 3 ACS Paragon Plus Environment


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have been correlated to the temperature-dependent gate current measurements in macroscopic MIS capacitors. The nanoscale electrical analyses showed the presence of a spatially uniform distribution of electrons trapping states in the insulator, and the occurrence of a density of 7×108 cm-2 of local and isolated current spots at high bias values. These nanoscale conductive paths can be associated to electrically active defects responsible of the trap-assisted current transport mechanism through the dielectric, observed by the temperature dependent characterization of the gate current.

II. EXPERIMENTAL

The hybrid MISHEMT structures were fabricated on Al0.26Ga0.74N/GaN heterostructures grown on 150 mm Si(111) substrates. The thickness of the AlGaN barrier layer was 16 nm. The total recession of the AlGaN barrier layer in the gate regions has been carried out using a dry etch with a Cl-based chemistry. Then an AlN(7 nm)/ SiN(7 nm) stack has been grown by sequential metal-organic chemical vapor deposition (MOCVD), using TMAl, Si2H6 and NH3 as gaseous precursors43. The metal gate was defined using 100 nm of Ni, while Ti/Al-based metallization have been used to form Ohmic contacts onto non-recessed AlGaN regions44. The fabricated structures for the macroscopic electrical characterization had an appropriate geometry (Fat-FET), with LG = 40 µm and WG = 200 µm, in order to minimize the series resistance of the access region (dGS=4 µm and dGD=4 µm) and to accurately determine the channel mobility 45. “Ungated” regions were left on selected sample areas to perform a nanoscale analysis of the insulator by means of Atomic Force Microscopy (AFM), Scanning Capacitance Microscopy (SCM) and Conductive Atomic Force Microscopy (C-AFM). In particular, SCM analysis on these regions has been performed to monitor the charge trapping behavior in the low voltage range (from -2 to 2 V). On the other hand, C-AFM measurements were used to study at the behavior of the insulator at higher voltages, i.e., applying a voltage bias of +10 V to an AFM conductive tip on the insulator. Nanoscale electrical characterizations, i.e. CAFM and SCM measurements, have been performed using a DI3100 system by Bruker with Nanoscope V controller, equipped with the TUNA module and the SCM modules. Conductive diamond coated silicon tips (model CDTP-NCHR-50) with spring constant k = 60 N/m, purchased from Nanosensors, were used for these electrical analyses, as they ensure high durability of the coating during subsequent scans performed on the AlN/SiN insulator stack. All the measurements were performed in air in the laboratory ambient conditions. Schematics of Fat-FETs devices used for the macroscopic electrical measurements and of the “ungated” samples areas used for the nanoscale analysis are shown in Fig. 1a and 1b, respectively. 4 ACS Paragon Plus Environment

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Fig. 1: Schematics of the AlGaN/GaN recessed Fat-FET using AlN/SiN as gate dielectric (a) and of the “ungated” samples used to perform the nanoscale analysis by C-AFM and SCM (b).

3. RESULTS AND DISCUSSION

3.1 Electrical characterization of the MISHEMT transistor

The transfer characteristics IDS-VGS of the transistor acquired at VDS=0.5 V are reported in Fig. 2a both on semilogarithmic (left axis) and linear scale (right axis). From the transcharacteristics in linear scale a positive threshold voltage Vth ≈ +1.2 V (i.e. a normally-off behavior) can be extrapolated by fitting of the linear region of the curves, as shown in Fig. 2a. The semilog scale curve shows a ION/IOFF current ratio in the order of 5-6×108 and a sub-threshold swing of 90 mV/dec, demonstrating excellent switching characteristics of the MISHEMT transistor. Fig. 2b, left axis, shows the device transconductance gm=dIDS/dVGS as a function of VGS. From the maximum value of gm, a peak field effect mobility of 180 cm2V-1s-1 was estimated using the expression

µ=

gm L WC insVDS

Eq. 1

where Cins = 3.35×10-7 F/cm2 is the gate insulator capacitance obtained by C-V measurements of the gate-drain capacitor. Clearly, although Fat-FET structures were used, this channel mobility value can be affected, to some extent, by the resistance of the access regions. Hence, in order to estimate the mobility value µ0 corrected by the effect of this resistive contribution, a plot of ID/gm1/2 46 is also reported in Fig.2b, right axis. From the expression of 5 ACS Paragon Plus Environment


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I DS gm

=

Wµ 0CinsVDS (VGS − Vth ) L

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Eq. 2

a value of µ0=204 cm2V-1s-1 was calculated by the slope of the linear fit, as illustrated in Fig. 2b. This mobility values is comparable to the largest reported values in the literature for hybrid MISHEMT devices29. Finally, the device output characteristics IDS-VDS for gate bias values VGS ranging from -2 to + 8 V are shown in Fig.2c. From the IDS-VDS characteristics at VGS= +3 V (corresponding to the linear region of the transfer characteristics) a series resistance RON = 320 Ω·mm can be estimated, which results in a sheet resistance of the channel region of 7.8 kΩ/sq after subtraction of the contribution of the access regions. The electrical characteristics of Fig. 2 demonstrate very good switching performances of the MISHEMT transistor with AlN/SiN gate insulator. However, threshold voltage instability due to electron trapping in the dielectric stack and defects-mediated conduction through this insulator can occur in the system. In the following, these aspects will be discussed in details by a combination of macroscopic and nanoscale electrical analyses.

Fig. 2: Transfer characteristics IDS-VGS at VDS=+0.5 V, reported in semi-log scale, left axis, and linear scale, right axis (a). Plot of the transconductance gm=dIDS/dVGS (left axis) and of IDS/gm1/2 (right axis) vs. VGS (b). A peak electron mobility µpeak=180 cm2V-1s-1 was evaluated from the maximum of gm, whereas a mobility value µ0=204 cm2V-1s-1 corrected for the access resistance contribution was extracted from the slope of the IDS/gm1/2 plot. Output characteristics IDS-VDS for gate bias values VGS from -2 to +8 V (c). First of all, Fig. 3a and b show the transfer characteristic IDS-VGS (both on linear and semilog scale) acquired at VDS = 0.5 V, considering a series of three subsequent gate voltage sweeps in the range from -2 V to +3 V (a) and from -2 V to +8 V (b), respectively. It is worth noting that only a slight positive shift of the transfer characteristics is observed when the gate voltage is subsequently swept three times from -2 V to +3 V (Fig. 3a). This behavior indicates that the electron trapping phenomena have a small impact on the threshold voltage stability at these bias level. On the other

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hand, when the gate voltage is swept from -2 V to +8 V (Fig. 3b), a considerable positive shift of the IDS-VGS curves can be observed between the first measurement (performed on a fresh device) and the second one, whereas no further shifts are observed in the following measurements. Using the capacitance of the gate-drain capacitor (Cins = 3.35×10-7 F/cm2) and the shift of the threshold voltage (1.7 V) allowed us to quantify the density of negative trapped charge of Qtrap =3.5×1012 cm-2.

Fig. 3: Transfer characteristics IDS-VGS at VDS=+0.5 V, reported in semi-log scale (left axis) and linear scale (right axis), for three subsequent gate voltage sweeps in the range from -2 V to +3 V (a) and from -2 V to +8 V (b).

3.2 Charge trapping phenomena and current transport through AlN/SiN stacks at the nanoscale

To further investigate the charge trapping effects and current transport through the AlN/SiN dielectric stack, nanoscale electrical measurements have been carried out on “ungated” devices, using either C-AFM or SCM (see schematic in Fig.1 b). Fig. 4 shows a set of local I-Vtip curves collected by C-AFM with the tip on a fixed position of the insulator (i.e., forming a nano-MIS capacitor), by sequentially sweeping 10 times the tip bias (Vtip) from 0 to +10V. For low voltage values applied to the tip (Vtip < 3V), the measured current is below the current sensor detection limit (about 0.03 pA). Hence, in this low bias range C-AFM is not suitable for the nanoscale electrical 7 ACS Paragon Plus Environment


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investigation of the 14 nm thick AlN/SiN dielectric stack. To this purpose, local capacitance measurements by SCM can be employed, as discussed later on in this section. On the other hand, for tip bias values >3V, an increase of the current of about two orders of magnitude is observed in the local I-V curves. Interestingly, a positive shift of the curves occurs between the 1st and the 2nd ramp, whereas it tends to stabilize during the following ramps. This result suggests that the electron trapping at high Vtip values (+10V) saturates in the early stage of the stress.

Fig. 4: Series of local I-Vtip curves collected by C-AFM with the tip on a fixed position of the AlN/SiN insulator, by sequentially sweeping 10 times the tip bias (Vtip) from 0 to +10V. The 1st and the following measurements are indicated. The C-AFM sensor detection limit is also shown by a horizontal dashed line. The representative I-Vtip characteristics in Fig.4 provide information on the current transport and electron trapping phenomena in the insulator at a single tip position. In order to get information on the lateral uniformity of the conduction properties, current maps have been collected by scanning the C-AFM tip on the insulator surface at a fixed bias (Vtip=+10V). The morphological AFM scan of the dielectric stack (see Fig. 5a) was acquired simultaneously to the current maps. It shows a smooth surface, free from macroscopic features and characterized by a root mean square (RMS) roughness of 0.46 nm in a 2×2 µm2 region. On the other hand, the current map acquired during the 1st scan on the same area (Fig. 5b) shows the presence of small black spots, in which a preferential 8 ACS Paragon Plus Environment

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current conduction is observed. These features do not exhibit a clear correlation with the morphology and can be likely associated to electrically active defects in the insulator. Their density was estimated to be 7×108 cm-2 from the C-AFM current map. In order to understand the effect of a second scan of the dielectric surface with the biased tip, Fig.5 c shows a C-AFM measurement carried out on a larger (5×5 µm2) area, which includes the 2×2 µm2 region (“dashed square”) that was previously subjected to the first scan (shown in Fig. 5b). Evidently, a different conductivity is observed in Fig. 5c between the fresh region (i.e., outside the dashed square) and the region that had been already subjected to the positive tip bias stress (i.e., inside dashed square). In particular, a lower current level is locally measured inside the dashed square region, which is consistent with the positive shift of the local I-Vtip characteristics shown in Fig.4. This local current reduction can be associated to uniformly distributed charge trapping occurring within the insulator.

Fig. 5: The morphology (AFM) (a) and relative current map (C-AFM) (b) in a scale of 2×2 µm2 on a fresh insulator. Comparison between fresh and stressed areas of the insulator on a 5×5 µm2 region (c). The dashed square indicates the stressed 2×2 µm2 region, and it is surrounded by a fresh region. As previously discussed, C-AFM analyses are not suitable for nanoscale electrical characterization of the 14 nm thick AlN/SiN dielectrics for low tip bias values (Vtip

SiN Dielectric Stacks with

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